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| ibm powernp? np2g network processor preliminary february 12, 2003 ?
? 0.1 copyright and disclaimer ? copyright international business machines corporation 2003 all rights reserved us government users restricted rights - us e, duplication or disclosure restricted by gsa adp schedule contract with ibm corp. printed in the united states of america february 2003 the following are trademarks of international business machines corporation in the united stat es, or other countries, or both. ibm ibm logo powerpc powernp ieee and ieee 802 are r egistered trademarks of ieee in all cases. other company, product and service names ma y be trademarks or service marks of others. all information contained in this document is subject to ch ange without notice. the products described in this document are not intended for use in applications su ch as implantation, life support, or other hazardous uses where malfunction could result in death, bodily injury, or catastrophic property damage. the information contained in this document does not affect or change ibm product specifications or warranties. no thing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third partie s. all information contained in this docu- ment was obtained in specific environment s, and is presented as an illustration . the results obtained in other operating environments may vary. while the information contained herein is believed to be a ccurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representati ons or warranties of accuracy or completeness are made. the information contained in this document is prov ided on an ?as is? basis. in no event will ibm be liable for damages arising directly or indirectly from any use of the information contained in this document. ibm microelectronics division 2070 route 52, bldg. 330 hopewell junction, ny 12533-6351 the ibm home page can be found at http://www.ibm.com the ibm microelectronics division home page can be found at http://www.ibm.com/chips np2_ds_title.fm.01 february 12, 2003 note: this document contains information on products in the sampling and/or initial production phases of development. this information is subject to change withou t notice. verify with your ibm field applications engi- neer that you have the latest version of this document before finalizing a design. ibm powernp np2g preliminary network processor np2_ds_toc.fm.01 february 12, 2003 contents page 3 of 539 contents about this book .......... ................ .............. .............. .............. .............. .............. ........... 25 who should read this manual .................................................................................................. ......... 25 related publications ......................................................................................................... ................... 25 conventions used in this manual .............................................................................................. ......... 25 1. general information ............... ................ .............. .............. .............. .............. ........... 27 1.1 features .................................................................................................................. ........................ 27 1.2 ordering information ...................................................................................................... ................. 28 1.3 overview .................................................................................................................. ....................... 29 1.4 np2g-based systems ........................................................................................................ ............ 29 1.5 structure ................................................................................................................. ......................... 31 1.5.1 epc structure ........................................................................................................... ............. 32 1.5.1.1 coprocessors .......................................................................................................... ....... 33 1.5.1.2 enhanced threads ...................................................................................................... ... 33 1.5.1.3 hardware accelerators ................................................................................................. .. 34 1.5.2 np2g memory ............................................................................................................. .......... 34 1.6 data flow ................................................................................................................. ....................... 35 1.6.1 basic data flow ......................................................................................................... ............ 35 1.6.2 data flow in the epc .................................................................................................... ........ 36 2. physical description .... ................. ................ ................ ................. ................ ........... 39 2.1 pin information ........................................................................................................... ..................... 40 2.1.1 ingress-to-egress wrap (iew) pins ...................................................................................... 41 2.1.2 flow control interface pins ............................................................................................. ...... 41 2.1.3 zbt interface pins ...................................................................................................... ........... 42 2.1.4 ddr dram interface pins ................................................................................................. ... 45 2.1.4.1 d3, d2, and d0 interface pins ........................................................................................ 51 2.1.4.2 d4_0 and d4_1 interface pins ....................................................................................... 53 2.1.4.3 d6_x interface pins ................................................................................................... ..... 54 2.1.4.4 ds1 and ds0 interface pins .......................................................................................... 5 5 2.1.5 pmm interface pins ...................................................................................................... ......... 56 2.1.5.1 tbi bus pins .......................................................................................................... ......... 59 2.1.5.2 gmii bus pins ......................................................................................................... ....... 63 2.1.5.3 smii bus pins ......................................................................................................... ........ 65 2.1.6 pci pins ................................................................................................................ ................. 71 2.1.7 management bus interface pins ........................................................................................... 73 2.1.8 miscellaneous pins ...................................................................................................... .......... 75 2.1.9 pll filter circuit ...................................................................................................... .............. 80 2.1.10 thermal i/o usage ...................................................................................................... ........ 80 2.1.10.1 temperature calculation .............................................................................................. 81 2.1.10.2 measurement calibration ............................................................................................. 81 2.2 clocking domains .......................................................................................................... ................. 82 2.3 mechanical specifications ................................................................................................. .............. 84 2.4 ieee 1149 (jtag) compliance ................ ................ ................. ................ ................ .............. ....... 86 2.4.1 statement of jtag compliance ............................................................................................ 86 2.4.2 jtag compliance mode .................................................................................................... ... 86 ibm powernp np2g network processor preliminary contents page 4 of 539 np2_ds_toc.fm.01 february 12, 2003 2.4.3 jtag implementation specifics ........................................................................................... .. 86 2.4.4 brief overview of jtag instructions ..................................................................................... . 87 2.4 signal pin lists .......................................................................................................... ...................... 86 3. physical mac multiplexer ......... ................ ................ ................. ................ ............. 109 3.1 ethernet overview ......................................................................................................... ................ 110 3.1.1 ethernet interface timing diagrams .................................................................................... 1 10 3.1.2 ethernet counters ....................................................................................................... ......... 112 3.1.3 ethernet support ........................................................................................................ .......... 117 3.2 pos overview .............................................................................................................. ................. 118 3.2.1 pos timing diagrams ..................................................................................................... .... 119 3.2.2 pos counters ............................................................................................................ .......... 122 3.2.3 pos support ............................................................................................................. ........... 126 4. ingress enqueuer / dequeuer / scheduler ............ .............. .............. ............ ........ 127 4.1 overview .................................................................................................................. ..................... 127 4.2 operation ................................................................................................................. ...................... 128 4.2.1 operational details ..................................................................................................... ......... 130 4.3 ingress flow control ...................................................................................................... ............... 132 4.3.1 flow control hardware fa cilities ........................................................................................ . 132 4.3.2 hardware function ....................................................................................................... ........ 134 4.3.2.1 exponentially weighted moving average (ewma) ...................................................... 134 4.3.2.2 flow control hardware actions .................................................................................... 134 5. ingress-to-egress wrap .............. ................ ................. ................ ................. .......... 135 5.1 ingress cell data mover ................................................................................................... ............. 135 5.1.1 cell header ............................................................................................................. ............. 136 5.1.2 frame header ............................................................................................................ .......... 138 5.2 ingress cell interface .................................................................................................... ................ 139 5.3 egress cell interface ..................................................................................................... ................ 140 5.4 egress cell data mover .................................................................................................... ............ 140 6. egress enqueuer / deq ueuer / scheduler ........... .............. .............. .............. ........ 141 6.1 functional blocks ......................................................................................................... ................. 142 6.2 operation ................................................................................................................. ...................... 144 6.3 egress flow control ....................................................................................................... ............... 147 6.3.1 flow control hardware fa cilities ........................................................................................ . 147 6.3.2 remote egress status bus ................................................................................................ .. 149 6.3.2.1 bus sequence and timing ........................................................................................... 149 6.3.2.2 configuration ......................................................................................................... ....... 150 6.3.3 hardware function ....................................................................................................... ........ 151 6.3.3.1 exponentially weighted moving average ..................................................................... 151 6.3.3.2 flow control hardware actions .................................................................................... 151 6.4 the egress scheduler ...................................................................................................... ............. 152 6.4.1 egress scheduler components ........................................................................................... 1 54 6.4.1.1 scheduling calendars .................................................................................................. 154 6.4.1.2 flow queues ........................................................................................................... ..... 155 ibm powernp np2g preliminary network processor np2_ds_toc.fm.01 february 12, 2003 contents page 5 of 539 6.4.1.3 target port queues .................................................................................................... .. 157 6.4.2 configuring flow queues ................................................................................................. ... 158 6.4.2.1 additional configuration notes ..................................................................................... 15 8 6.4.3 scheduler accuracy and capacity ....................................................................................... 1 58 7. embedded processor complex .......... ................ .............. .............. .............. ......... 161 7.1 overview .................................................................................................................. ..................... 161 7.1.1 thread types ............................................................................................................ .......... 165 7.2 dyadic protocol processor unit (dppu) ..................................................................................... .. 166 7.2.1 core language processor (clp) ........................................................................................ 16 7 7.2.1.1 core language processor address map ..................................................................... 169 7.2.2 clp opcode formats ...................................................................................................... .... 171 7.2.3 dppu coprocessors ....................................................................................................... .... 171 7.2.4 shared memory pool ...................................................................................................... ..... 172 7.3 clp opcode formats ........................................................................................................ ........... 173 7.3.1 control opcodes ......................................................................................................... ......... 173 7.3.1.1 nop opcode ............................................................................................................ ..... 174 7.3.1.2 exit opcode ........................................................................................................... ....... 174 7.3.1.3 test and branch opcode ............................................................................................. 17 4 7.3.1.4 branch and link opcode .............................................................................................. 1 75 7.3.1.5 return opcode ......................................................................................................... .... 176 7.3.1.6 branch register opcode .............................................................................................. 1 76 7.3.1.7 branch pc relative opcode ........................................................................................ 176 7.3.1.8 branch reg+off opcode .............................................................................................. 17 7 7.3.2 data movement opcodes ................................................................................................... . 178 7.3.2.1 memory indirect opcode .............................................................................................. 1 82 7.3.2.2 memory address indirect opcode ................................................................................ 183 7.3.2.3 memory direct opcode ................................................................................................ 1 84 7.3.2.4 scalar access opcode ................................................................................................. 184 7.3.2.5 scalar immediate opcode ............................................................................................ 18 5 7.3.2.6 transfer quadword opcode ......................................................................................... 185 7.3.2.7 zero array opcode ..................................................................................................... .. 186 7.3.3 coprocessor execution opcodes ........................................................................................ 18 7 7.3.3.1 execute direct opcode ................................................................................................ 188 7.3.3.2 execute indirect opcode .............................................................................................. 189 7.3.3.3 execute direct conditional opcode ............................................................................. 189 7.3.3.4 execute indirect conditional opcode ........................................................................... 190 7.3.3.5 wait opcode ........................................................................................................... ...... 190 7.3.3.6 wait and branch opcode ............................................................................................. 19 1 7.3.4 alu opcodes ............................................................................................................. ......... 192 7.3.4.1 arithmetic immediate opcode ...................................................................................... 192 7.3.4.2 logical immediate opcode ........................................................................................... 19 5 7.3.4.3 compare immediate opcode ....................................................................................... 195 7.3.4.4 load immediate opcode .............................................................................................. 19 6 7.3.4.5 arithmetic register opcode ......................................................................................... 19 9 7.3.4.6 count leading zeros opcode ...................................................................................... 201 7.4 dppu coprocessors ......................................................................................................... ............ 202 7.4.1 tree search engine coprocessor ....................................................................................... 20 3 7.4.2 data store coprocessor .................................................................................................. .... 203 7.4.2.1 data store coprocessor address map ......................................................................... 204 ibm powernp np2g network processor preliminary contents page 6 of 539 np2_ds_toc.fm.01 february 12, 2003 7.4.2.2 data store coprocessor commands ............................................................................ 210 7.4.3 control access bus (cab) coprocessor ............................................................................. 220 7.4.3.1 cab coprocessor address map ................................................................................... 220 7.4.3.2 cab access to np2g structures ................................................................................. 221 7.4.3.3 cab coprocessor commands ..................................................................................... 222 7.4.4 enqueue coprocessor ..................................................................................................... .... 223 7.4.4.1 enqueue coprocessor address map ............................................................................ 224 7.4.4.2 enqueue coprocessor commands .............................................................................. 235 7.4.5 checksum coprocessor .................................................................................................... ... 241 7.4.5.1 checksum coprocessor address map ......................................................................... 241 7.4.5.2 checksum coprocessor commands ............................................................................ 242 7.4.6 string copy coprocessor ................................................................................................. .... 246 7.4.6.1 string copy coprocessor address map ....................................................................... 246 7.4.6.2 string copy coprocessor commands .......................................................................... 246 7.4.7 policy coprocessor ...................................................................................................... ........ 247 7.4.7.1 policy coprocessor address map ................................................................................ 247 7.4.7.2 policy coprocessor commands ................................................................................... 247 7.4.8 counter coprocessor ..................................................................................................... ...... 248 7.4.8.1 counter coprocessor address map ............................................................................. 248 7.4.8.2 counter coprocessor commands ................................................................................ 249 7.4.9 coprocessor response bus ................................................................................................ 252 7.4.9.1 coprocessor response bus address map ................................................................... 252 7.4.9.2 coprocessor response bus commands ..................................................................... 252 7.4.9.3 14-bit coprocessor response bus ............................................................................... 253 7.4.10 semaphore coprocessor .................................................................................................. . 253 7.4.10.1 semaphore coprocessor commands ........................................................................ 253 7.4.10.2 error conditions ..................................................................................................... ..... 255 7.4.10.3 software use models ................................................................................................. 256 7.5 interrupts and timers ..................................................................................................... ............... 257 7.5.1 interrupts .............................................................................................................. ................ 257 7.5.1.1 interrupt vector registers ............................................................................................ . 257 7.5.1.2 interrupt mask registers .............................................................................................. 257 7.5.1.3 interrupt target registers ............................................................................................ . 257 7.5.1.4 software interrupt registers ......................................................................................... 257 7.5.2 timers .................................................................................................................. ................ 258 7.5.2.1 timer interrupt counters .............................................................................................. 258 7.6 dispatch unit ............................................................................................................. .................... 259 7.6.1 port configuration memory ............................................................................................... ... 261 7.6.1.1 port configuration memory index definition ................................................................. 261 7.6.2 port configuration memory contents definition ................................................................... 262 7.6.3 completion unit ......................................................................................................... .......... 263 7.7 hardware classifier ....................................................................................................... ................ 264 7.7.1 ingress classification .................................................................................................. ......... 264 7.7.1.1 ingress classification input .......................................................................................... . 264 7.7.1.2 ingress classification output ........................................................................................ 265 7.7.2 egress classification ................................................................................................... ......... 269 7.7.2.1 egress classification input ........................................................................................... 269 7.7.2.2 egress classification output ........................................................................................ 2 70 7.7.3 completion unit label generation ....................................................................................... 271 7.8 policy manager ............................................................................................................ .................. 272 ibm powernp np2g preliminary network processor np2_ds_toc.fm.01 february 12, 2003 contents page 7 of 539 7.9 counter manager ........................................................................................................... ............... 275 7.9.1 counter manager usage ................................................................................................... .. 277 7.10 semaphore manager ........................................................................................................ .......... 283 8. tree search engi ne ................. .............. .............. .............. .............. .............. ......... 285 8.1 overview .................................................................................................................. ..................... 285 8.1.1 addressing control store (cs) ........................................................................................... . 285 8.1.2 d6 control store. ....................................................................................................... .......... 286 8.1.3 logical memory views of d6 .............................................................................................. . 286 8.1.4 control store use restrictions .......................................................................................... .. 287 8.1.5 object shapes ........................................................................................................... .......... 288 8.1.6 illegal memory access ................................................................................................... ...... 290 8.1.7 memory range checking (address bounds check) ........................................................... 291 8.2 trees and tree searches ................................................................................................... .......... 292 8.2.1 input key and color register for fm and lpm trees ......................................................... 293 8.2.2 input key and color register for smt trees ...................................................................... 293 8.2.3 direct table ............................................................................................................ ............. 294 8.2.3.1 pattern search control blocks (pscb) ........................................................................ 294 8.2.3.2 leaves and compare-at-end operation ...................................................................... 295 8.2.3.3 cascade/cache ......................................................................................................... ... 295 8.2.3.4 cache flag and nrpscbs registers ........................................................................... 295 8.2.3.5 cache management ..................................................................................................... 295 8.2.3.6 search output ......................................................................................................... ..... 296 8.2.4 tree search algorithms .................................................................................................. ..... 296 8.2.4.1 fm trees .............................................................................................................. ........ 296 8.2.4.2 lpm trees ............................................................................................................. ....... 297 8.2.4.3 lpm pscb structure in memory .................................................................................. 297 8.2.4.4 lpm compact pscb support ...................................................................................... 298 8.2.4.5 lpm trees with multibit compare ................................................................................ 300 8.2.4.6 smt trees ............................................................................................................. ....... 303 8.2.4.7 compare-at-end operation .......................................................................................... 304 8.2.4.8 ropes ................................................................................................................. .......... 305 8.2.4.9 aging ................................................................................................................. ........... 306 8.2.5 tree configuration and initialization ................................................................................... . 307 8.2.5.1 the ludeftable ........................................................................................................ ... 307 8.2.5.2 tse free lists (tse_fl) ............................................................................................. 3 10 8.2.6 tse registers and register map ........................................................................................ 3 11 8.2.7 tse instructions ........................................................................................................ .......... 316 8.2.7.1 fm tree search (ts_fm) ............................................................................................ 317 8.2.7.2 lpm tree search (ts_lpm) ........................................................................................ 318 8.2.7.3 smt tree search (ts_smt) ....................................................................................... 320 8.2.7.4 memory read (mrd) ................................................................................................... 3 21 8.2.7.5 memory write (mwr) ................................................................................................... 322 8.2.7.6 hash key (hk) ......................................................................................................... .... 323 8.2.7.7 read ludeftable (rdludef) .................................................................................... 324 8.2.7.8 compare-at-end (compend) ..................................................................................... 326 8.2.7.9 distinguish position for fast table update (distpos_gdh) ..................................... 327 8.2.7.10 read pscb for fast table update (rdpscb_gdh) ................................................ 328 8.2.7.11 write pscb for fast table update (wrpscb_gdh) ............................................... 330 8.2.7.12 setpatbit_gdh ........................................................................................................ .. 331 ibm powernp np2g network processor preliminary contents page 8 of 539 np2_ds_toc.fm.01 february 12, 2003 8.2.8 gth hardware assist instructions ....................................................................................... 333 8.2.8.1 hash key gth (hk_gth) ........................................................................................... 334 8.2.8.2 read ludeftable gth (rdludef gth) ................................................................... 334 8.2.8.3 tree search enqueue free list (tsenqfl) ............................................................... 335 8.2.8.4 tree search dequeue free list (tsdqfl) .................................................................. 336 8.2.8.5 read current leaf from rope (rclr) ......................................................................... 336 8.2.8.6 advance rope with optional delete leaf (ardl) ........................................................ 337 8.2.8.7 tree leaf insert rope (tlir) ....................................................................................... 33 8 8.2.8.8 clear pscb (clrpscb) .............................................................................................. 338 8.2.8.9 read pscb (rdpscb) ................................................................................................ 339 8.2.8.10 write pscb (wrpscb) ............................................................................................. 339 8.2.8.11 push pscb (pushpscb) ......................................................................................... 340 8.2.8.12 distinguish (distpos) ............................................................................................... 340 8.2.8.13 tsr0 pattern (tsr0pat) .......................................................................................... 341 8.2.8.14 pattern 2dta (pat2dta) .......................................................................................... 342 8.2.9 hash functions .......................................................................................................... .......... 342 9. serial / parallel manager interface ......... .............. .............. .............. .............. ........ 351 9.1 spm interface components .................................................................................................. ........ 351 9.2 spm interface data flow ................................................................................................... ........... 352 9.3 spm interface protocol .................................................................................................... ............. 354 9.4 spm cab address space ..................................................................................................... ........ 356 9.4.1 byte access space ....................................................................................................... ....... 356 9.4.2 word access space ....................................................................................................... ...... 356 9.4.3 eeprom access spac e ................ ................ ................ ................ ............. ............. ........... . 357 9.4.3.1 eeprom single-byte access ................ ................ ................ ................ ................ ...... 357 9.4.3.2 eeprom 2-byte access . ................ ................. ................ ................ ............. ............... 358 9.4.3.3 eeprom 3-byte access . ................ ................. ................ ................ ............. ............... 358 9.4.3.4 eeprom 4-byte access . ................ ................. ................ ................ ............. ............... 359 10. embedded powerpc? subsystem .. ............... .............. ............... .............. .......... 361 10.1 description .............................................................................................................. .................... 361 10.2 processor local bus and device control register buses .......................................................... 362 10.2.1 processor local bus (plb) .............................................................................................. .. 362 10.2.2 device control register (dcr) bus ................................................................................... 36 3 10.3 plb address map .......................................................................................................... ............. 364 10.4 cab address map .......................................................................................................... ............. 366 10.5 universal interrupt controller (uic) macro ............................................................................... ... 367 10.6 pci/plb bridge macro ..................................................................................................... ........... 368 10.7 cab interface macro ...................................................................................................... ............. 372 10.7.1 powerpc cab address (pwrpc_cab_addr) register ..................................................... 374 10.7.2 powerpc cab data (pwrpc_cab_data) register ........................................................... 374 10.7.3 powerpc cab control (pwrpc_cab_cntl) register ........................................................ 375 10.7.4 powerpc cab status (pwrpc_cab_status) register ...................................................... 375 10.7.5 powerpc cab mask (pwrpc_cab_mask) register ......................................................... 376 10.7.6 powerpc cab write under mask data (pwrpc_cab_wum_data) ................................ 377 10.7.7 pci host cab address (host_cab_addr) register .......................................................... 377 10.7.8 pci host cab data (host_cab_data) register ............................................................... 378 10.7.9 pci host cab control (host_cab_cntl) register ............................................................. 378 ibm powernp np2g preliminary network processor np2_ds_toc.fm.01 february 12, 2003 contents page 9 of 539 10.7.10 pci host cab status (host_cab_status) register ........................................................ 379 10.7.11 pci host cab mask (host_cab_mask) register ........................................................... 379 10.7.12 pci host cab write under mask data (host_cab_wum_data) register .................... 380 10.8 mailbox communications and dram interface macro ............................................................... 381 10.8.1 mailbox communications between pci host and powerpc subsystem .......................... 382 10.8.2 pci interrupt status (pci_interr_status) register ............................................................. 384 10.8.3 pci interrupt enable (pci_interr_ena) register ............................................................... 385 10.8.4 powerpc subsystem to pci host message resource (p2h_msg_resource) register .. 386 10.8.5 powerpc subsystem to host message address (p2h_msg_addr) register ................... 386 10.8.6 powerpc subsystem to host doorbell (p2h_doorbell) register ...................................... 387 10.8.7 host to powerpc subsystem message address (h2p_msg_addr) register ................... 388 10.8.8 host to powerpc subsystem doorbell (h2p_doorbell) register ...................................... 389 10.8.9 mailbox communications between powerpc subsystem and epc ................................. 390 10.8.10 epc to powerpc subsystem resource (e2p_msg_resource) register ....................... 391 10.8.11 epc to powerpc subsystem message address (e2p_msg_addr) register ................. 392 10.8.12 epc to powerpc subsystem doorbell (e2p_doorbell) register .................................... 393 10.8.13 epc interrupt vector register ......................................................................................... 394 10.8.14 epc interrupt mask register ........................................................................................... 394 10.8.15 powerpc subsystem to epc message address (p2e_msg_addr) register ................. 395 10.8.16 powerpc subsystem to epc doorbell (p2e_doorbell) register .................................... 396 10.8.17 mailbox communications between pci host and epc ................................................... 397 10.8.18 epc to pci host resource (e2h_msg_resource) register .......................................... 398 10.8.19 epc to pci host message address (e2h_msg_addr) register ..................................... 399 10.8.20 epc to pci host doorbell (e2h_doorbell) register ....................................................... 400 10.8.21 pci host to epc message address (h2e_msg_addr) register ..................................... 402 10.8.22 pci host to epc doorbell (h2e_doorbell) register ....................................................... 403 10.8.23 message status (msg_status) register .......................................................................... 404 10.8.24 powerpc boot redirection instruction registers (boot_redir_inst) ............................... 406 10.8.25 powerpc machine check (pwrpc_mach_chk) register ............................................... 407 10.8.26 parity error status and reporting .................................................................................... 407 10.8.27 slave error address regi ster (sear) ...... ................ ................ ................. ................ ...... 408 10.8.28 slave error status regist er (sesr) ......... ................ ................ ................. ................ ...... 409 10.8.29 parity error counter (perr_count) register .................................................................... 410 10.9 system start-up and initialization ....................................................................................... ........ 411 10.9.1 np2g resets ............................................................................................................ ......... 411 10.9.2 systems initialized by external pci host processors ....................................................... 412 10.9.3 systems with pci host processors and initialized by powerpc subsystem .................... 413 10.9.4 systems without pci host processors and initialized by powerpc subsystem .............. 414 10.9.5 systems without pci host or delayed pci configuration and initialized by epc ............ 415 11. reset and initialization ................... ................. ................ .............. .............. ......... 417 11.1 overview ................................................................................................................. .................... 417 11.2 step 1: set i/os ......................................................................................................... .................. 419 11.3 step 2: reset the np2g ................................................................................................... ........... 420 11.4 step 3: boot ............................................................................................................. ................... 421 11.4.1 boot the embedded processor complex (epc) ................................................................ 421 11.4.2 boot the powerpc ....................................................................................................... ...... 421 11.4.3 boot summary ........................................................................................................... ........ 421 11.5 step 4: setup 1 .......................................................................................................... ................. 422 ibm powernp np2g network processor preliminary contents page 10 of 539 np2_ds_toc.fm.01 february 12, 2003 11.6 step 5: diagnostics 1 .................................................................................................... .............. 423 11.7 step 6: setup 2 .......................................................................................................... .................. 424 11.8 step 7: hardware initialization .......................................................................................... ........... 425 11.9 step 8: diagnostics 2 .................................................................................................... .............. 425 11.10 step 9: operational ..................................................................................................... .............. 426 11.11 step 10: configure ...................................................................................................... .............. 426 11.12 step 11: initialization complete ........................................................................................ ......... 427 12. debug facilities ............. ................. ................ ................ ............... .............. .......... 429 12.1 debugging picoprocessors ................................................................................................. ........ 429 12.1.1 single step ............................................................................................................ ............. 429 12.1.2 break points ........................................................................................................... ............ 429 12.1.3 cab accessible registers ............................................................................................... .. 429 12.2 riscwatch ................................................................................................................ .................. 430 13. configuration .......... ................. ................ ................ ................. ................ ............. 431 13.1 memory configuration ..................................................................................................... ............ 431 13.1.1 memory configuration register (memory_config) ............................................................ 432 13.1.2 dram parameter register (dram_parm) ....................................................................... 434 13.1.3 delay calibration registers ............................................................................................ ... 439 13.2 toggle mode register ..................................................................................................... ............ 444 13.3 bci format register ...................................................................................................... .............. 444 13.3.1 toggle mode ............................................................................................................ .......... 446 13.3.1.1 dsu information ...................................................................................................... ... 446 13.3.1.2 enqe command and qclass 5 or 6 ........................................................................... 447 13.4 egress reassembly sequence check register (e_reassembly_seq_ck) ............................... 448 13.5 aborted frame reassembly action control register (afrac) ................................................. 448 13.6 packing registers ........................................................................................................ ............... 449 13.6.1 packing control register (pack_ctrl) ................................................................................ 44 9 13.6.2 packing delay register (pack_dly) ................................................................................... 45 0 13.7 initialization control registers ......................................................................................... ............ 451 13.7.1 initialization register (init) ........................................................................................ ......... 451 13.7.2 initialization done register (init_done) ............................................................................ 4 52 13.8 np2g ready register (npr_ready) ........................................................................................ 453 13.9 phase-locked loop registers .............................................................................................. ...... 454 13.9.1 phase-locked loop fail register (pll_lock_fail) ........................................................... 454 13.10 software controlled reset register (soft_reset) .................................................................... 455 13.11 ingress free queue threshold configuration ........................................................................... 45 5 13.11.1 bcb_fq threshold registers ......................................................................................... 45 5 13.11.2 bcb_fq threshold for guided traffic (bcb_fq_th_gt) .............................................. 455 13.11.3 bcb_fq_threshold_0 register (bcb_fq_th_0) .......................................................... 456 13.11.4 bcb_fq_threshold_1 register (bcb_fq_th_1) .......................................................... 457 13.11.5 bcb_fq_threshold_2 register (bcb_fq_th_2) .......................................................... 457 13.12 i-gdq threshold register (i-gdq_th) ..................................................................................... 458 13.13 ingress target dmu data storage map register (i_tdmu_dsu) .......................................... 459 13.14 embedded processor complex configuration .......................................................................... 460 13.14.1 powerpc core reset register (powerpc_reset) .......................................................... 460 13.14.2 powerpc boot redirection instruction registers (boot_redir_inst) ............................... 461 ibm powernp np2g preliminary network processor np2_ds_toc.fm.01 february 12, 2003 contents page 11 of 539 13.14.3 watch dog reset enable register (wd_reset_ena) ..................................................... 462 13.14.4 boot override register (boot_override) ......................................................................... 463 13.14.5 thread enable register (thread_enable) ...................................................................... 464 13.14.6 gfh data disable register (gfh_data_dis) ................................................................. 464 13.14.7 ingress maximum dcb entries (i_max_dcb) ................................................................. 465 13.14.8 egress maximum dcb entries (e_max_dcb) ................................................................ 465 13.14.9 ordered semaphore enable register (ordered_sem_ena) ........................................... 466 13.14.10 enhanced classification enable register (enh_hwc_ena) ......................................... 467 13.15 flow control structures ................................................................................................. ............ 468 13.15.1 ingress flow control hardware structures ...................................................................... 468 13.15.1.1 ingress tr ansmit probability memory register (i_tx_prob_mem) .......................... 468 13.15.1.2 ingress pseudorandom number register (i_rand_num) ........................................ 469 13.15.1.3 free queue thresholds register (fq_th) .............................................................. 469 13.15.2 egress flow control structures ....................................................................................... 470 13.15.2.1 egress transmit prob ability memory (e_tx_prob_mem) register .......................... 470 13.15.2.2 egress pseudorandom number (e_rand_num) ..................................................... 471 13.15.2.3 p0 twin count threshold (p0_twin_th) ................................................................. 471 13.15.2.4 p1 twin count threshold (p1_twin_th) ................................................................. 471 13.15.2.5 egress p0 twin count ewma threshold register (e_p0_twin_ewma_th) ......... 472 13.15.2.6 egress p1 twin count ewma threshold register (e_p1_twin_ewma_th) ......... 472 13.15.3 exponentially weighted moving average constant (k) register (ewma_k) ................. 473 13.15.4 exponentially weighted moving average sample period (t) register (ewma_t) ......... 474 13.15.5 flow control force discard register (fc_force_discard) ............................................. 475 13.16 egress cdm stack threshold register (e_cdm_stack_th) .................................................. 476 13.17 free queue extended stack maximum size (fq_es_max) register ..................................... 477 13.18 egress free queue thresholds ............................................................................................ .... 478 13.18.1 fq_es_threshold_0 register (fq_es_th_0) .............................................................. 478 13.18.2 fq_es_threshold_1 register (fq_es_th_1) .............................................................. 479 13.18.3 fq_es_threshold_2 register (fq_es_th_2) .............................................................. 479 13.19 egress frame data queue thresholds (e_grx_gbx_th) ....................................................... 480 13.20 discard flow qcb register (discard_qcb) ............................................................................. 481 13.21 bandwidth allocation register (bw_alloc_reg) ....................................................................... 482 13.22 miscellaneous controls register (misc_cntrl) .................................................................... 483 13.23 frame control block fq size register (fcb_fq_max) .......................................................... 484 13.24 data mover unit (dmu) configuration registers ...................................................................... 485 13.25 frame pad configuration register (dmu_pad) ........................................................................ 489 13.26 ethernet jumbo frame size register (en_jumbo_fs) ........................................................... 489 13.27 qd accuracy register (qd_acc) ........................................................................................... ... 490 13.28 packet over sonet control register (pos_ctrl) ................................................................... 491 13.28.1 initial crc value determination ...................................................................................... 493 13.29 packet over sonet maximum frame size (pos_max_fs) ................................................... 495 13.30 ethernet encapsulation type register for control (e_type_c) ............................................... 496 13.31 ethernet encapsulation type register for data (e_type_d) ................................................... 496 13.32 source address array (sa_array) ........................................................................................ ... 497 13.33 destination address array (da_array) .................................................................................... . 498 13.34 programmable i/o register (pio_reg) .................................................................................... 499 13.35 ingress-to-egress wrap configuration registers ...................................................................... 500 13.35.1 iew configuration 1 register (iew_config1) ................................................................. 500 ibm powernp np2g network processor preliminary contents page 12 of 539 np2_ds_toc.fm.01 february 12, 2003 13.35.2 iew configuration 2 register (iew_config2) .................................................................. 500 13.35.3 iew initialization register (iew_init) ............................................................................... 501 14. electrical and thermal sp ecifications ............ .............. ............... .............. .......... 503 14.1 driver specifications .................................................................................................... ................ 522 14.2 receiver specifications .................................................................................................. ............. 524 14.3 other driver and receiver specifications ................................................................................. .. 526 15. glossary of terms and abbreviations ........ ................ ................. .............. .......... 529 revision log ............. ................ ................ .............. .............. ............... .............. .......... 5 39 ibm powernp np2g preliminary network processor np2_ds_lot.fm.01 february 12, 2003 page 13 of 539 list of tables table 2-1. signal pin functions ................................................................................................ .................... 40 table 2-2. ingress-to-egress wrap (iew) pins ................................................................................... ......... 41 table 2-3. flow control pins ................................................................................................... ..................... 41 table 2-4. z0 zbt sram interface pins .......................................................................................... ............ 42 table 2-5. z1 zbt sram interface pins .......................................................................................... ............ 42 table 2-6. zbt sram timing diagram legend (for figure 2-2 ) .................................................................. 44 table 2-7. ddr timing diagram legend (for figure 2-3 , figure 2-4 , and figure 2-5 ) ................................ 48 table 2-8. ddr timing diagram legend (for figure 2-3 , figure 2-4 , and figure 2-5 ) ................................ 49 table 2-9. ddr timing diagram legend (for figure 2-3 , figure 2-4 , and figure 2-5 ) ................................ 50 table 2-10. d3 and d2 interface pins ........................................................................................... ............... 51 table 2-11. d0 memory pins ..................................................................................................... ................... 52 table 2-12. d4_0 and d4_1 interface pins ....................................................................................... ........... 53 table 2-13. d6_5, d6_4, d6_3, d6_2, d6_1, and d6_0 memory pins ........................................................ 54 table 2-14. ds1 and ds0 interface pins ......................................................................................... ............ 55 table 2-15. pmm interface pins ................................................................................................. .................. 56 table 2-16. pmm interface pin multiplexing ..................................................................................... ............ 57 table 2-17. pmm interface pins: debug (dmu_d only) ............................................................................. .59 table 2-18. parallel data bit to 8b/10b position mapping (tbi interface) ................................................... 59 table 2-19. pmm interface pins: tbi mode ....................................................................................... .......... 59 table 2-20. tbi timing diagram legend (for figure 2-8 ) ............................................................................ 62 table 2-21. pmm interface pins: gmii mode ...................................................................................... ......... 63 table 2-22. gmii timing diagram legend (for figure 2-9 ) .......................................................................... 65 table 2-23. pmm interface pins: smii mode ...................................................................................... .......... 65 table 2-24. smii timing diagram legend (for figure 2-10 ) ......................................................................... 66 table 2-25. pos signals ........................................................................................................ ...................... 67 table 2-26. pos timing diagram legend (for figure 2-11 and figure 2-12 ) .............................................. 70 table 2-27. pci pins ........................................................................................................... ......................... 71 table 2-28. pci timing diagram legend (for figure 2-13 ) .......................................................................... 73 table 2-29. management bus pins ................................................................................................ .............. 73 table 2-30. spm bus timing diagram legend (for figure 2-14 ) ................................................................. 74 table 2-31. miscellaneous pins ................................................................................................. ................... 75 table 2-32. signals requiring pull-up or pull-down ............................................................................. ....... 77 table 2-33. pins requiring connections to other pins ........................................................................... ..... 78 table 2-34. alternate wiring for pins requiring connections to other pins ................................................ 79 table 2-35. mechanical specifications .......................................................................................... ............... 85 table 2-36. jtag compliance-enable inputs ...................................................................................... ........ 86 table 2-37. implemented jtag public instructions ............................................................................... ...... 86 table 2-38. complete signal pin listing by signal name ......................................................................... ... 88 ibm powernp np2g network processor preliminary page 14 of 539 np2_ds_lot.fm.01 february 12, 2003 table 2-39. complete signal pin listing by grid position ....................................................................... .....98 table 3-1. ingress ethernet counters ........................................................................................... ..............112 table 3-2. egress ethernet counters ............................................................................................ .............114 table 3-3. ethernet support .................................................................................................... ....................117 table 3-4. dmu and framer configurations ....................................................................................... ........118 table 3-5. receive counter ram addresses for ingress pos mac .........................................................122 table 3-6. transmit counter ram addresses for egress pos mac .........................................................124 table 3-7. pos support ......................................................................................................... .....................126 table 4-1. flow control hardware facilities ........ ............................................................................ ...........133 table 5-1. cell header fields .................................................................................................. ...................137 table 5-2. frame header fields ................................................................................................. ................139 table 6-1. flow control hardware facilities ........ ............................................................................ ...........148 table 6-2. flow queue parameters ............................................................................................... .............152 table 6-3. valid combinations of scheduler parameters .......................................................................... .152 table 6-4. configure a flow qcb ................................................................................................ ...............158 table 7-1. core language processor address map ................................................................................. ..169 table 7-2. shared memory pool .................................................................................................. ...............172 table 7-3. condition codes (cond field) ........................................................................................ ...........173 table 7-4. aluop field definition .............................................................................................. ..................193 table 7-5. lop field definition ................................................................................................ ....................195 table 7-6. arithmetic opcode functions ......................................................................................... ............199 table 7-7. coprocessor instruction format ...................................................................................... ..........203 table 7-8. data store coprocessor address map .................................................................................. ....204 table 7-9. ingress datapool byte address definitions ........................................................................... ....206 table 7-10. egress frames datapool quadword addresses .....................................................................208 table 7-11. datapool byte addressing with cell header skip ...................................................................20 9 table 7-12. number of frame-bytes in the datapool .............................................................................. ...210 table 7-13. wreds input ........................................................................................................ ..................212 table 7-14. wreds output ....................................................................................................... .................212 table 7-15. rdeds input ........................................................................................................ ...................213 table 7-16. rdeds output ....................................................................................................... .................214 table 7-17. wrids input ........................................................................................................ ....................214 table 7-18. wrids output ....................................................................................................... ..................214 table 7-19. rdids input ........................................................................................................ .....................215 table 7-20. rdids output ....................................................................................................... ...................215 table 7-21. rdmoree input ...................................................................................................... ...............216 table 7-22. rdmoree output ..................................................................................................... ..............216 table 7-23. rdmorei input ...................................................................................................... .................217 table 7-24. rdmorei output ..................................................................................................... ...............217 ibm powernp np2g preliminary network processor np2_ds_lot.fm.01 february 12, 2003 page 15 of 539 table 7-25. leasetwin output ................................................................................................... ............. 218 table 7-26. edirty inputs ...................................................................................................... .................. 218 table 7-27. edirty output ...................................................................................................... ................. 219 table 7-28. idirty inputs ...................................................................................................... .................... 220 table 7-29. idirty output ...................................................................................................... ................... 220 table 7-30. cab coprocessor address map ........................................................................................ ..... 220 table 7-31. cab address field definitions ...................................................................................... .......... 221 table 7-32. cab address, functional island encoding ............................................................................ .. 221 table 7-33. cabarb input ....... ................ ................ ................. ................ ................ ............... .................. 222 table 7-34. cabaccess input ...... ................ ................ ................ ................ ................ .............. ............. 223 table 7-35. cabaccess output ... ................ ................ ................ ................ ................ ................ ........... 223 table 7-36. enqueue coprocessor address map .................................................................................... .. 224 table 7-37. ingress fcbpage description ........................................................................................ ......... 225 table 7-38. egress fcbpage description ......................................................................................... ......... 229 table 7-39. enqe target queues ................................................................................................. ............ 236 table 7-40. egress target queue selection coding ............................................................................... ... 236 table 7-41. egress target queue parameters ..................................................................................... ..... 237 table 7-42. type field for discard queue ....................................................................................... .......... 237 table 7-43. enqe command input ................................................................................................. ........... 237 table 7-44. egress queue class definitions ..................................................................................... ......... 238 table 7-45. enqi target queues ................................................................................................. .............. 238 table 7-46. ingress target queue selection coding .............................................................................. ... 239 table 7-47. ingress target queue fcbpage parameters ......................................................................... 239 table 7-48. enqi command input ................................................................................................. ............ 239 table 7-49. ingress-queue class definition ..................................................................................... .......... 240 table 7-50. enqclr command input ............................................................................................... ........ 240 table 7-51. enqclr output ...................................................................................................... ................ 240 table 7-52. release_label output ............... ................ ................ ................ ................. ............... ........ 240 table 7-53. checksum coprocessor address map ................................................................................... . 241 table 7-54. gengen/gengenx command inputs ................................................................................. 243 table 7-55. gengen/gengenx/genip/genipx command outputs .................................................... 243 table 7-56. genip/genipx command inputs ........................................................................................ .. 244 table 7-57. chkgen/chkgenx command inputs .................................................................................. 244 table 7-58. chkgen/chkgenx/chkip/chkipx command outputs ..................................................... 245 table 7-59. chkip/chkipx command inputs ........................................................................................ ... 245 table 7-60. string copy coprocessor address map ................................................................................ .. 246 table 7-61. strcopy command input .............................................................................................. ........... 246 table 7-62. strcopy command output ............................................................................................. ......... 247 table 7-63. policy coprocessor address map ..................................................................................... ...... 247 ibm powernp np2g network processor preliminary page 16 of 539 np2_ds_lot.fm.01 february 12, 2003 table 7-64. polaccess input .................................................................................................... ...................248 table 7-65. polaccess output ................................................................................................... .................248 table 7-66. counter coprocessor address map .................................................................................... ....248 table 7-67. ctrinc input ....................................................................................................... .......................249 table 7-68. ctrrinc input ...................................................................................................... ......................250 table 7-69. ctradd input ....................................................................................................... ......................250 table 7-70. ctrradd input ...................................................................................................... ....................250 table 7-71. ctrrd/ctrrdclr input ............................................................................................... ................251 table 7-72. ctrrd/ctrrdclr output .............................................................................................. ...............251 table 7-73. ctrwr15_0/ctrwr31_16 input ......................................................................................... .........251 table 7-74. coprocessor response bus coprocessor address map ........................................................252 table 7-75. coprocessor response bus coprocessor command summary .............................................252 table 7-76. crbsetbusy output .................................................................................................. ................252 table 7-77. 14-bit response bus bit and cycle definition ....................................................................... ..253 table 7-78. semaphore lock input ............................................................................................... ..............254 table 7-79. semaphore unlock input ............................................................................................. ............254 table 7-80. reservation release input .......................................................................................... ............254 table 7-81. priority assignments for the dispatch unit queue arbiter .......................................................260 table 7-82. port configuration memory index .................................................................................... ........261 table 7-83. relationship between sp field, queue, and port configuration memory index .....................262 table 7-84. port configuration memory content .................................................................................. ......262 table 7-85. protocol identifiers ............................................................................................... ....................265 table 7-86. hccia table ........................................................................................................ ....................266 table 7-87. protocol identifiers for frame encapsulation types ................................................................2 67 table 7-88. general purpose register bit definitions for ingress classification flags ..............................268 table 7-89. flow control information values .................................................................................... ..........269 table 7-90. hccia index definition ............................................................................................. ...............270 table 7-91. general purpose register 1 bit definitions for egress classification flags ............................270 table 7-92. completion unit label .............................................................................................. ...............271 table 7-93. polcb field definitions ............................................................................................ ................273 table 7-94. counter manager components ......................................................................................... ......277 table 7-95. counter types ...................................................................................................... ...................277 table 7-96. counter actions .................................................................................................... ...................277 table 7-97. counter definition entry format .................................................................................... ..........278 table 7-98. counter manager passed parameters .................................................................................. ..281 table 7-99. counter manager use of address bits ................................................................................ .....281 table 8-1. control store address mapping for tse references ................................................................285 table 8-2. cs address map and use .............................................................................................. ...........285 table 8-3. plb and d6 control store addressing ................................................................................. .....287 ibm powernp np2g preliminary network processor np2_ds_lot.fm.01 february 12, 2003 page 17 of 539 table 8-4. dtentry, pscb, and leaf shaping ..................................................................................... ...... 288 table 8-5. height, width, and offset restrictions for tse objects ............................................................ 29 0 table 8-6. fm and lpm tree fixed leaf formats .................................................................................. ... 292 table 8-7. smt tree fixed leaf formats ......................................................................................... ......... 292 table 8-8. search input parameters ............................................................................................. ............. 293 table 8-9. cache status registers .............................................................................................. ............... 295 table 8-10. search output parameters ........................................................................................... ........... 296 table 8-11. dtentry and pscbline formats ....................................................................................... ..... 296 table 8-12. lpm dtentry and pscbline formats ................................................................................... . 297 table 8-13. nlasmt field format ................................................................................................ ............. 304 table 8-14. compdeftable entry format .......................................................................................... ........ 305 table 8-15. ludeftable rope parameters ......................................................................................... ....... 306 table 8-16. nlarope field format ............................................................................................... ............. 307 table 8-17. ludeftable entry definitions ....................................................................................... ........... 307 table 8-18. free list entry definition ......................................................................................... ................ 310 table 8-19. tse scalar registers for gth only .................................................................................. ...... 311 table 8-20. tse array registers for all gxh .................................................................................... ......... 313 table 8-21. tse registers for gth (tree management) ........................................................................... 3 13 table 8-22. tse scalar registers for gdh and gth ............................................................................... . 313 table 8-23. pscb register format ............................................................................................... ............. 314 table 8-24. tse gth indirect registers ......................................................................................... ........... 314 table 8-25. address map for pscb0-2 registers in gth ......................................................................... 31 5 table 8-26. general tse instructions ........................................................................................... ............. 316 table 8-27. fm tree search input operands ...................................................................................... ....... 317 table 8-28. fm tree search results (tsr) output ................................................................................ ... 317 table 8-29. lpm tree search input operands ..................................................................................... ..... 318 table 8-30. lpm tree search results output ..................................................................................... ...... 319 table 8-31. smt tree search input operands ..................................................................................... ..... 320 table 8-32. smt tree search results output ..................................................................................... ...... 320 table 8-33. memory read input operands ......................................................................................... ....... 321 table 8-34. memory read output results ......................................................................................... ........ 322 table 8-35. memory write input operands ........................................................................................ ........ 323 table 8-36. hash key input operands ............................................................................................ ........... 323 table 8-37. hash key output results ............................................................................................ ............ 324 table 8-38. rdludef input operands ............................................................................................. ......... 325 table 8-39. rdludef output results ............................................................................................. .......... 325 table 8-40. compend input operands ............................................................................................. ....... 326 table 8-41. compend output results ............................................................................................. ........ 326 table 8-42. distpos_gdh input operands ......................................................................................... .... 327 ibm powernp np2g network processor preliminary page 18 of 539 np2_ds_lot.fm.01 february 12, 2003 table 8-43. distpos_gdh output results ......................................................................................... .....328 table 8-44. rdpscb_gdh input operands .......................................................................................... ....329 table 8-45. rdpscb_gdh output results .......................................................................................... .....330 table 8-46. wrpscb_gdh input operands .......................................................................................... ...330 table 8-47. wrpscb_gdh output results .......................................................................................... ....331 table 8-48. setpatbit_gdh input operands ....................................................................................... .......332 table 8-49. setpatbit_gdh output results ....................................................................................... ........332 table 8-50. general gth instructions ........................................................................................... .............333 table 8-51. hash key gth input operands ........................................................................................ .......334 table 8-52. hash key gth output results ........................................................................................ ........334 table 8-53. rdludef_gth input operands ......................................................................................... ...335 table 8-54. rdludef_gth output results ......................................................................................... ....335 table 8-55. tsenqfl input operands ............................................................................................. .........335 table 8-56. tsenqfl output results ............................................................................................. ..........335 table 8-57. tsdqfl input operands .............................................................................................. ...........336 table 8-58. tsdqfl output results .............................................................................................. ............336 table 8-59. rclr input operands ................................................................................................ .............337 table 8-60. rclr output results ................................................................................................ ..............337 table 8-61. ardl input operands ................................................................................................ .............337 table 8-62. ardl output results ................................................................................................ ..............338 table 8-63. tlir input operands ................................................................................................ ...............338 table 8-64. tlir output results ................................................................................................ ................338 table 8-65. clrpscb input operands ............................................................................................. .........338 table 8-66. clrpscb output results ............................................................................................. ..........339 table 8-67. rdpscb input operands .............................................................................................. ..........339 table 8-68. rdpscb output results .............................................................................................. ...........339 table 8-69. wrpscb input operands .............................................................................................. .........340 table 8-70. pushpscb input operands ............................................................................................ .......340 table 8-71. pushpscb output results ............................................................................................ ........340 table 8-72. distpos input operands ............................................................................................. ..........341 table 8-73. distpos output results ............................................................................................. ...........341 table 8-74. tsr0pat input operands ............................................................................................. ..........341 table 8-75. tsr0pat output results ............................................................................................. ...........341 table 8-76. pat2dta input operands ............................................................................................. ..........342 table 8-77. pat2dta output results ............................................................................................. ...........342 table 8-78. general hash functions ............................................................................................. .............342 table 9-1. field definitions for cab addresses ................................................................................. .........357 table 10-1. plb master connections ............................................................................................. ............362 table 10-2. device control registers ........................................................................................... ..............363 ibm powernp np2g preliminary network processor np2_ds_lot.fm.01 february 12, 2003 page 19 of 539 table 10-3. address map for cab interface macro ................................................................................ .... 364 table 10-4. plb address map for mailbox and dram interface macro .................................................... 364 table 10-5. cab address map for mailbox and dram interface macro .................................................... 366 table 10-6. uic interrupt assignments .......................................................................................... ............ 367 table 10-7. np2g pci device configuration header values .................................................................... 368 table 10-8. plb address map for pci/plb macro .................................................................................. .. 368 table 10-9. pci/plb bridge macro configuration registers ...................................................................... 3 70 table 10-10. reset domains ..................................................................................................... ................. 411 table 11-1. reset and initialization sequence .................................................................................. ......... 417 table 11-2. set i/os checklist ................................................................................................. ................... 419 table 11-3. setup 1 checklist .................................................................................................. .................. 422 table 11-4. diagnostics 1 checklist ............................................................................................ ............... 423 table 11-5. setup 2 checklist .................................................................................................. .................. 424 table 11-6. hardware initialization checklist .................................................................................. ........... 425 table 11-7. diagnostic 2 checklist ............................................................................................. ................ 425 table 11-8. configure checklist ................................................................................................ ................. 426 table 14-1. absolute maximum ratings ........................................................................................... .......... 503 table 14-2. input capacitance (pf) ............................................................................................. ............... 503 table 14-3. operating supply voltages .......................................................................................... ............ 521 table 14-4. operating supply currents .......................................................................................... ............ 521 table 14-5. thermal characteristics ............................................................................................ .............. 521 table 14-6. definition of terms ................................................................................................ .................. 522 table 14-7. 1.8 v cmos driver dc voltage specifications ....................................................................... 5 22 table 14-8. 1.8 v cmos driver minimum dc currents at rated voltage ................................................. 522 table 14-9. 2.5 v cmos driver dc voltage specifications ....................................................................... 5 22 table 14-10. 2.5 v cmos driver minimum dc currents at rated voltage ............................................... 522 table 14-11. 3.3 v-tolerant 2.5 v cmos driver dc voltage specifications ............................................. 523 table 14-12. 3.3 v lvttl driver dc voltage specifications ..................................................................... 5 23 table 14-13. 3.3 v lvttl/5.0 v-tolerant driver dc voltage specifications ............................................. 523 table 14-14. 3.3 v lvttl driver minimum dc currents at rated voltage ............................................... 523 table 14-15. 1.8 v cmos receiver dc voltage specifications ................................................................ 524 table 14-16. 2.5 v cmos receiver dc voltage specifications ................................................................ 524 table 14-17. 3.3 v lvttl receiver dc voltage specifications ................................................................ 524 table 14-18. 3.3 v lvttl / 5 v tolerant receiver dc voltage specifications .......................................... 524 table 14-19. receiver maximum input leakage dc current input specifications .................................... 524 table 14-20. lvds receiver dc specifications ................................................................................... ..... 526 table 14-21. sstl2 dc specifications ........................................................................................... ........... 526 ibm powernp np2g network processor preliminary page 20 of 539 np2_ds_lot.fm.01 february 12, 2003 ibm powernp np2g preliminary network processor np2_ds_lof.fm.01 february 12, 2003 page 21 of 539 list of figures figure 1-1. function placement in an np2g-based system ....................................................................... 30 figure 1-2. np2g major functional blocks ....................................................................................... ........... 32 figure 1-3. data flow overview ................................................................................................. .................. 35 figure 1-4. basic data flow in the epc ......................................................................................... .............. 36 figure 2-1. device interfaces .................................................................................................. ..................... 39 figure 2-2. zbt sram timing diagram ............................................................................................ ........... 43 figure 2-3. ddr control timing diagram ................ ......................................................................... ........... 45 figure 2-4. ddr read timing diagram ................... ......................................................................... ........... 46 figure 2-5. ddr write output timing diagram .................................................................................... ........ 47 figure 2-6. np2g dmu bus clock connections ..................................................................................... ..... 58 figure 2-7. np2g dmu bus clock connections (pos overview) ............................................................... 59 figure 2-8. tbi timing diagram ................................................................................................. .................. 61 figure 2-9. gmii timing diagram ................................................................................................ ................. 64 figure 2-10. smii timing diagram ............................................................................................... ................ 66 figure 2-11. pos transmit timing diagram ....................................................................................... ......... 68 figure 2-12. pos receive timing diagram ........................................................................................ ......... 69 figure 2-13. pci timing diagram ................................................................................................ ................. 72 figure 2-14. spm bus timing diagram ............................................................................................ ............ 74 figure 2-15. alternate wiring for pins requiring connection to other pins ................................................. 79 figure 2-16. pll filter circuit diagram ........................................................................................ ................ 80 figure 2-17. thermal monitor ................................................................................................... .................... 80 figure 2-18. clock generation and distribution ................................................................................. .......... 82 figure 2-19. pins diagram ...................................................................................................... ...................... 83 figure 2-20. mechanical diagram ................................................................................................ ................ 84 figure 3-1. pmm overview ....................................................................................................... .................. 109 figure 3-2. ethernet mode ...................................................................................................... .................... 110 figure 3-3. smii timing diagram ................................................................................................ ............... 110 figure 3-4. gmii timing diagram ................................................................................................ ............... 111 figure 3-5. tbi timing diagram ................................................................................................. ................ 111 figure 3-6. gmii pos mode timing diagram ....................................................................................... ..... 112 figure 3-7. oc-3 / oc-3c / oc-12 configuration ................................................................................. ...... 118 figure 3-8. receive pos8 interface timing for 8-bit data bus (oc-3c) .................................................... 119 figure 3-9. transmit pos8 interface timing for 8-bit data bus (oc-3c) ................................................... 120 figure 3-10. receive pos8 interface timing for 8-bit data bus (oc-12c) ................................................ 120 figure 3-11. transmit pos8 interface timing for 8-bit data bus (oc-12c) ............................................... 121 figure 4-1. logical organization of ingress eds data flow management ................................................ 128 figure 4-2. sof ring structure ................................................................................................. ................. 130 figure 4-3. ingress eds logical structure ...................................................................................... ........... 131 ibm powernp np2g network processor preliminary page 22 of 539 np2_ds_lof.fm.01 february 12, 2003 figure 5-1. ingress-to egress wrap functional blocks ........................................................................... ....135 figure 5-2. cell header format ................................................................................................. .................136 figure 5-3. frame header format ................................................................................................ ..............138 figure 6-1. egress eds functional blocks ....................................................................................... ..........142 figure 6-2. cell formats and storage in the egress ds .......................................................................... ...145 figure 6-3. tpq, fcb, and egress frame example ................................................................................. .146 figure 6-4. res bus timing ..................................................................................................... ..................149 figure 6-5. the egress scheduler ............................................................................................... ...............153 figure 7-1. embedded processor complex block diagram .......................................................................164 figure 7-2. dyadic protocol processor unit functional blocks ................................................................... 167 figure 7-3. core language processor ............................................................................................ ............169 figure 7-4. ot5 field definition: loading halfword/word gprs from a halfword/word array ....................178 figure 7-5. ot5 field definition: loading gpr byte from array byte .........................................................179 figure 7-6. ot5 field definition: loading gpr halfword/word from array byte .........................................180 figure 7-7. ot5 field definition: store gpr byte/halfword/word to array byte/halfword/word .................181 figure 7-8. ot3i field definition .............................................................................................. .....................194 figure 7-9. ot2i field definition: compare halfword/word immediate ........................................................196 figure 7-10. ot4i field definition load immediate halfword/word .............................................................197 figure 7-11. ot4i field definition: load immediate byte ........................................................................ .....198 figure 7-12. ot3r field definition ............................................................................................. ....................200 figure 7-13. a frame in the ingress data store ................................................................................. ........207 figure 7-14. frame in the egress data store .................................................................................... .........208 figure 7-15. ingress fcbpage format ............................................................................................ ...........225 figure 7-16. egress fcbpage format ............................................................................................. ..........228 figure 7-17. dispatch unit ..................................................................................................... .....................259 figure 7-18. split between picocode and hardware for the policy manager ..............................................272 figure 7-19. counter manager block diagram ..................................................................................... ......276 figure 7-20. counter definition entry .......................................................................................... ...............279 figure 7-21. counter blocks and sets ........................................................................................... .............280 figure 8-1. example shaping dimensions ......................................................................................... .........289 figure 8-2. effects of using a direct table .................................................................................... .............294 figure 8-3. example of lpm pscb detail layout in memory .....................................................................298 figure 8-4. example of lpm pscb and compact lpm pscb layout in memory .....................................300 figure 8-5. lpm multibit nbt pscb detail layout ................................................................................ .....302 figure 8-6. example multibit lpm tree layout ................................................................................... ........303 figure 8-7. example input key and leaf pattern fields .......................................................................... ...304 figure 8-8. rope structure ..................................................................................................... ....................306 figure 8-9. general layout of tse fields in shared memory pool ............................................................316 figure 8-10. general layout of tse rdludef in shared memory pool ..................................................325 ibm powernp np2g preliminary network processor np2_ds_lof.fm.01 february 12, 2003 page 23 of 539 figure 8-11. shared memory pool with distpos_gdh command subfields .......................................... 327 figure 8-12. shared memory pool with pscb subfields ........................................................................... 3 28 figure 8-13. no-hash function .................................................................................................. ................ 343 figure 8-14. 192-bit ip hash function .......................................................................................... ............. 343 figure 8-15. mac hash function ................................................................................................. .............. 344 figure 8-16. network dispatcher hash function .................................................................................. ...... 345 figure 8-17. 48-bit mac hash function .......................................................................................... ........... 346 figure 8-18. 60-bit mac hash function .......................................................................................... ........... 347 figure 8-19. 8-bit hash function ............................................................................................... ................. 348 figure 8-20. 12-bit hash function .............................................................................................. ................ 348 figure 8-21. 16 bit hash function .............................................................................................. ................ 349 figure 9-1. spm interface block diagram ........................................................................................ .......... 351 figure 9-2. epc boot image in external eeprom .. ................. ................ ................ ................ ............... .. 353 figure 9-3. spm bit timing ..................................................................................................... ................... 354 figure 9-4. spm interface write protocol ....................................................................................... ............ 354 figure 9-5. spm interface read protocol ........................................................................................ ........... 355 figure 10-1. powerpc subsystem block diagram ................................................................................... .. 361 figure 10-2. polled access flow diagram ........................................................................................ ......... 373 figure 11-1. system environments ............................................................................................... ............. 418 figure 13-1. np2g memory subsystems ............................................................................................ ....... 431 figure 14-1. 3.3 v lvttl / 5 v tolerant bp33 and ip33 receiver input current/voltage curve .............. 525 ibm powernp np2g network processor preliminary page 24 of 539 np2_ds_lof.fm.01 february 12, 2003 ibm powernp np2g preliminary network processor np2_ds_preface.fm.01 february 12, 2003 about this book page 25 of 539 about this book this datasheet describes the ibm powernp np2g and explains the basics of building a system using it. a terms and abbreviations list is provided in section 15. glossary of terms and abbreviations on page 529. who should read this manual this datasheet provides information for network hardware engineers and programmers using the np2g to develop interconnect solutions for internet or enterprise network providers. it includes an overview of data flow through the device and desc riptions of each functional block. in ad dition, it provides electrical, physical, thermal, and configuration information about the device. related publications ibm powerpc 405gp embedded processor user?s manual ( http://www-3.ibm.com/chips/techlib/techlib.nsf/products/powerpc_405gp_embedded_processor ) pci specification, version 2.2 ( http://www.pcisig.com ) conventions used in this manual the following conventions are used in this manual. 1. the bit notation in the following sections is non-ibm, meaning that bit zero is the least significant bit and bit 31 is the most significant bit in a 4-byte word. section 2. physical description section 3. physical mac multiplexer section 4. ingress enqueuer / dequeuer / scheduler section 5. ingress-to-egress wrap section 6. egress enqueuer / dequeuer / scheduler section 7. embedded processor complex section 9. serial / parallel manager interface 2. the bit notation in section 8. tree search engine and section 10. embedded powerpc? subsystem is ibm-standard, meaning that bit 31 is the least significant bit and bit zero is the most significant bit in a 4-byte word. 3. nibble numbering is the same as byte numbering. the left-most nibble is most significant and starts at zero. 4. all counters wrap back to zero when they exceed their maximum values. exceptions to this rule are noted in the counter definitions. 5. overbars (txenb , for example) designate signals that are asserted ?low.? ibm powernp np2g network processor preliminary about this book page 26 of 539 np2_ds_preface.fm.01 february 12, 2003 6. numeric notation is as follows: hexadecimal values are preceded by x or x. for example: x?0b00?. binary values in text are either spelled out (zero and one) or appear in quotation marks. for example: ?10101?. binary values in the default and description columns of the register sections are often isolated from text as in this example: 0: no action on read access 1: auto-reset interrupt request register upon read access 7. field length conventions are as follows: 1 byte = 8 bits 1 word = 4 bytes 1 double word (dw) = 2 words = 8 bytes 1 quadword (qw) = 4 words = 16 bytes 8. for signal and field definitions, when a field is designated as ?reserved?: it must be sent as zero as an input into the np2g, ei ther as a signal i/o or a value in a reserved field of a control block used as input to a picocode process. it must not be checked or modified as an output from the np2g, either as a signal i/o or a value in a reserved field of a control block used as input to an external code process. its use as code point results in unpredictable behavior. np2_ds_sec01_over.fm.01 february 12, 2003 ibm powernp np2g preliminary network processor general information page 27 of 539 1. general information 1.1 features 4.5 million packets per second (mpps) layer 2 and layer 3 switching. six dyadic protocol processor units (dppus) - two picocode processors per dppu - 10 shared coprocessors per dppu - four threads per dppu - zero context switching overhead between threads embedded powerpc ? processor and external 33/66 mhz 32-bit pci bus for enhanced design flexibility. - supports riscwatch through the jtag interface integrated ethernet and packet over sonet (pos) medium access controls (macs) - up to two gigabit ethernet (plus a gigabit uplink/control point attachment port) or 20 fast ethernet ports, accessed through serial media-independent (smii), gigabit media-independent (gmii), and ten-bit (tbi) interfaces, that support industry stan- dard physical layer devices - 36 ethernet statistics counters per mac - up to one million softw are-defin ed, hard- ware-assisted counters, enabling support of many standard management information bases (mibs) at wire speed - 8 oc-3c, 2 oc-12, or 2 oc-12c (plus an oc-12 or oc-12c uplink/control point attachment port) integrated pos interfaces that support industry standard pos framers - hardware vlan support (detection, tag insertion and deletion). advanced flow control mechanisms that tolerate high rates of temporary oversubscription without tcp collapse. fast lookups and powerful search engines based on geometric hash functions that yield lower collision rates than conventional bit- scrambling methods. hardware support for port mirroring. mirrored traffic can share bandwidth with user traffic or use a separate data path, eliminating the normal penalty for port mirroring. support for jumbo frames. - maximum length determined by the value in the ethernet jumbo frame size register (see section 13.26 on page 489). the value is increased by four octets for vlan tagged frames. hardware-managed, software-configured band- width allocation control of 2047 concurrent com- munication flows. serial management interface to support physical layer devices, board, and box functions ibm sa-27e, 0.18 m technology. voltage ratings: - 1.8 v supply voltage - 2.5 v and 3.3 v compatibility with drivers and receivers - 1.25 v reference voltage for sstl drivers 1088-pin bottom surface metallurgy - ceramic column grid array ( bsm-ccga) package with 815 signal i/o. ieee ? 1149.1a jtag compliant. . ibm powernp np2g network processor preliminary general information page 28 of 539 np2_ds_sec01_over.fm.01 february 12, 2003 1.2 ordering information part number description ibm32np160epxcaa133 ibm powernp np2ga (r1.0) network processor IBM32NP160EPXCAB133 ibm powernp np2gb (r2.0) network processor ibm powernp np2g preliminary network processor np2_ds_sec01_over.fm.01 february 12, 2003 general information page 29 of 539 1.3 overview the ibm powernp? np2g network processor enables network hardware designers to create fast, powerful, and scalable systems. the np2g contains an embedded processor complex (epc) in which processors and coprocessors work with hardware accelerators to increase processing speed and power. additional features, such as integrated search engines, variable packet length schedulers, and support for qos functions, support the needs of customers who require high function, high capacity, media-rate switching. the epc is the heart of the np2g, evaluating, defining, and processing data. it maximizes the speed and processing power of the device and provides it with functionality above that of an independent switching device. within the epc, six dyadic protocol processo r units (dppus) combine picocode processors, copro- cessors, and hardware accelerators to support functions such as high-speed pattern search, data manipula- tion, internal chip management, frame parsing, and data prefetching. the np2g provides fast switching by integrating switching engine, search engine, and security functions on one device. it supports layer 2 and 3 ethernet frame switching, and includes three priority levels for port mirroring, high priority user frames, and low priority frames. it supports ethernet, packet over sonet (pos), and point-to-point protocol (ppp) protocols. because of the device?s ability to enforce hundreds of rules with complex range and action specifications, np2g-based systems are uniquely suited for server clusters. systems developed with the np2g use a distributed software model. to support this model, the device hard- ware and code development suite in clude on-chip debugger fa cilities, a picocode assembler, and a pico- code and system simulator, all of which can decrease the time to market for new applications. in order to take advantage of these features, a designer must know how the device works and how it fits into a system. the following sections disc uss the basic placement of the device within a system, its major func- tional blocks, and the movement of data through it. t he chapters following this over view explore all of these issues in detail. 1.4 np2g-based systems the np2g is designed for medium- to low-end systems, or ?desktop routers, ? with an uplink to a larger switch. for high-end systems, the ibm powernp np4gs3 network processor is required. systems developed with the np2g use a distributed so ftware model, which relie s on a control point to execute software instructions. the control point can be an external microprocessor connected through an ethernet link or the pci interface. the np2g?s embedded powerpc processor can also perform control point functions. in this model, functions are divide d between the contro l point and the network proc essor, as illustrated in figure 1-1 . the control point supports layer 2 and layer 3 routing protocols, layer 4 and layer 5 network applications, box maintenance, management information base (mib) collection (that is, the control point func- tions as an snmp agent), and other systems management functions. other functions, such as forwarding, filtering, and classification of the tables generated by the routing protocols, are performed by the dyadic protocol processor units (dppus) in each network processor in the system. the core language processors (clps) in each dppu execute the epc?s core software instruction set, which includes conditional execution, conditional branching, signed and unsigned operations, counts of leading zeros, and more. ibm powernp np2g network processor preliminary general information page 30 of 539 np2_ds_sec01_over.fm.01 february 12, 2003 figure 1-1. function placement in an np2g-based system ibm powernp cp control point ibm powernp np2g control store l2 support (spanning tree...) box services l2 forwarding filtering learning l3 forwarding filtering l4 flow classification priority shaping network management l3 support (ospf...) frame repository queueing flow control frame alteration multicast handling data store l4 and l5 network applications networking management agent (rmon...) counters np2g ibm powernp np2g preliminary network processor np2_ds_sec01_over.fm.01 february 12, 2003 general information page 31 of 539 1.5 structure the ibm powernp np2g network processor has seve n major functional blocks, as illustrated in figure 1-2 on page 32: epc provides all processing functions for the device. embedded powerpc? subsystem can act as a control point for the device; the control store interface provides up to 128 mb of program space for the embedded ibm powerpc subsystem. ingress enqueuer / dequeuer / scheduler (ingress eds) provides logic for frames traveling in from the physical layer devices. egress enqueuer / dequeuer / scheduler (egress eds) provides logic for frames traveling out to the physical layer devices. ingress-to-egress wrap (iew) transfers frames from the ingress side of the np2g to the egress side of the np2g. ingress physical mac multiplexer (ingress pmm) receives frames from physical layer devices. egress physical mac multiplexer (egress pmm) transmits frames to physical layer devices. ibm powernp np2g network processor preliminary general information page 32 of 539 np2_ds_sec01_over.fm.01 february 12, 2003 1.5.1 epc structure the epc contains six dyadic protocol processor unit s (dppus). each dppu contains two core language processors (clps) that share 10 coprocessors, one coprocessor command bus, and a memory pool. the six dppus share 24 threads, four of which are enhanced, and three hardware accelerators. together, the six dppus are capable of operating on up to 24 frames in parallel. they share 32 k words of internal picocode instruction store, providing 1596 million instructions per second (mips) of processing power. in addition, the epc contains a hardware classifier to parse frames on the fly, preparing them for processing by the picocode. figure 1-2. np2g major functional blocks embedded processor complex ingress eds egress eds enqueuer dequeuer scheduler enqueuer dequeuer data store ingress-to-egress wrap (iew) ddrsdram(10to13) zbt sram (2) internal srams data store ddr ingress pmm multiplexed macs egress pmm multiplexed macs a c d e physical layer devices scheduler dmu bus dmu bus embedded 405 power pc spm interface sdram (4) ibm powernp np2g preliminary network processor np2_ds_sec01_over.fm.01 february 12, 2003 general information page 33 of 539 1.5.1.1 coprocessors each dppu contains two picocode processors, the clps , that execute the epc?s core instruction set and control thread swapping and instruction fetching. the two clps share eight dedicated coprocessors that can run in parallel with the clps: 1.5.1.2 enhanced threads each clp can run two threads, making four threads per dp pu, or 24 total. twenty of the threads are general data handlers (gdhs), used for forwarding frames, and four of the 24 threads are enhanced: checksum calculates and verifies frame header checksums. cab interface controls thread access to the cont rol access bus (cab) th rough the cab arbiter; the cab control, cab arbiter, and cab interface enable debug access to np2g data structures. coprocessor response bus the coprocessor response bus (crb) is a bus interface and an internal copro- cessor that enables the attachment of an external coprocessor with results returned to an internal register. picocode determines the processing status (busy/ not busy) via the busy bit managed by the crb coprocessor. counter updates counters for the picocode engines. data store interfaces frame buffer memory (ingress and egress directions), providing a 320-byte working area. provides access to the ingress and egress data stores. enqueue manages control blocks containing key frame parameters; works with the comple- tion unit hardware accelerator to enqueue frames to the iew and target port output queues. policy determines if the incoming data stream complies with configured profiles. string copy accelerates data movement between coprocessors within the shared memory pool. tree search engine performs pattern analysis through tree searches (based on algorithms provided by the picocode) and read and write accesses, all protected by memory range checking; accesses control store memory independently. semaphore manager assists in contro lling access to shared resources, su ch as tables an d control struc- tures, through the use of semaphores; grants semaphores either in dispatch order (ordered semaphores) or in request order (unordered semaphores). guided frame handler (gfh) handles guided frames, the in-band control mechanism between the epc and all devices in the system, including the control point. general table handler (gth) builds table data in control memory ibm powernp np2g network processor preliminary general information page 34 of 539 np2_ds_sec01_over.fm.01 february 12, 2003 1.5.1.3 hardware accelerators the dppus share three hardware accelerators: 1.5.2 np2g memory storage for the np2g is provided by both internal and external memories (see figure 1-2 on page 32). the control store contains all tables, counters, and any other data needed by the picocode. the data stores contain the frame data to be forwarded and can be used by the picocode (via the data store coprocessor) to create guided traffic. the np2g has the following stores: a common instruction memory that holds 32 k instruction words for normal processing and control func- tions 128 kb internal sram for input frame buffering 113 kb internal sram control store high capacity external ddr sdram for egress frame buffering and large forwarding tables; the amount of memory can vary depending on the configuration. external zbt sram for fast table access - up to 512 kb 36 in the z0 interface - up to 123 kb 18 in the z1 interface (for use by the scheduler) general powerpc handler request (gph-req) processes frames bound to the embedded powerpc. general powerpc handler response (gph-resp) processes responses from the embedded powerpc. completion unit assures frame order as data exits the threads. dispatch unit fetches data and parses the work out among the dppus. control store arbiter enables the processors to share access to the control store. ibm powernp np2g preliminary network processor np2_ds_sec01_over.fm.01 february 12, 2003 general information page 35 of 539 1.6 data flow 1.6.1 basic data flow too many data flow routes and possibilities exist to fu lly document in this overview. however, data generally moves through the np2g in the following manner (see figure 1-3 ): 1. the ingress pmm receives a frame from a physical layer device and forwards it to the ingress eds. 2. the ingress eds identifies the frame and enqueues it to the epc. 3. the epc processes the frame data (see section 1.6.2 ). the epc may discard the frame or modify the frame data directly and then return the updated data to the ingress eds?s data store. 4. the frame is enqueued to the ingress eds, and the ingress eds scheduler selects the frame for trans- mission and moves the data to the iew. 5. the iew transfers frames from the ingress eds to the egress eds. 6. the egress eds reassembles the frame and enqueues it to the epc once it is fully reassembled. 7. the epc processes it (see section 1.6.2 ). the epc may discard the frame or modify it using one of the frame alteration hardware assists. if exten- sive modification is required, the epc may append to or rewrite the frame in data store. figure 1-3. data flow overview embedded processor complex ingress eds ingress pmm egress pmm physical layer devices 1 2 3 4 6 7 8 9 egress eds ingress-to-egress wrap (iew) 5 ibm powernp np2g network processor preliminary general information page 36 of 539 np2_ds_sec01_over.fm.01 february 12, 2003 8. the frame is enqueued to the egress eds, and the egress eds scheduler, if enabled, selects the frame for transmission and moves the data to the egress pmm. if the scheduler is not enabled, the epc may forward the frame to a target port queue, to a wrap port, or to the gfh or gph. 9. the egress pmm sends the frame to a physical layer device. 1.6.2 data flow in the epc the epc is the functional center of the device, and it pl ays a pivotal role in data flow. this section presents a basic overview of data flow in the epc. figure 1-4. basic data flow in the epc hardware classifier control store ingress eds queue ingress data egress data store store interface data store coprocessor enqueue coprocessor tree search engine completion unit dispatch unit instruction memory 1st available dppu arbiter egress eds queue interface (external) to egress pmm to iew ingress eds egress eds epc 2 9 8 7 5 4 3 11 12 14 15 16 17 18 1 6 10 13 ibm powernp np2g preliminary network processor np2_ds_sec01_over.fm.01 february 12, 2003 general information page 37 of 539 ingress side 1. the ingress eds enqueues a data frame to the epc. 2. the dispatch unit fetches a portion of a frame and sends it to the next available thread. 3. simultaneously, the hardware classifier (hc) determines the starting common instruction address (cia), parses different frame formats (for example: bridged, ip, and ipx), and forwards the results on to the thread. 4. the picocode examines the information from the hc and may examine the data further; it assembles search keys and launches the tree search engine (tse). 5. the tse performs table searches, using search algorithms based on the format of the downloaded tables. 6. the control store arbiter allocates control store memory bandwidth among the protocol processors. 7. frame data moves into the data store coprocessor?s memory buffer. forwarding and frame alteration information is identified by the results of the search. the ingress eds can insert or overlay vlan tags on the frame (hardware-assisted frame alteration) or the picocode can allocate or remove buffers to allow alteration of the frame (flexible frame alter- ation). 8. the enqueue coprocessor builds the necessary information to enqueue the frame to the iew and pro- vides it to the completion unit (cu), which guarantees the frame order as the data moves from the 24 threads of the dppu to the ingress eds queues. 9. the frame is enqueued to the ingress eds. the ingress eds forwards the frame to the ingress scheduler. the scheduler selects the frame for transmission to the iew. note: the entire frame is not sent at once. the scheduler sends it a cell at a time. with the help of the ingress eds, the iew segments the frames into 64-byte cells and inserts cell header and frame header bytes so that they can be stored and reassembled on the egress side. thus, it is not necessary to use the smaller ingress data store to store frames while waiting for their ends to arrive. egress side 10. the egress eds enqueues a data frame to the epc. 11. the dispatch unit fetches a portion of a frame and sends it to the next available thread. 12. simultaneously, the hc determines the starting cia, parses different frame formats (for example: bridged, ip, and ipx), and forwards the results to the thread. 13. the picocode examines the information from the hc and may examine the data further; it assembles search keys and launches the tse. 14. the tse performs table searches, using search algorithms based on the format of the downloaded tables. 15. the control store arbiter allocates control store memory bandwidth among the protocol processors. 16. frame information, including alteration instructions , moves into queues in the egress eds; if flexible frame alteration is used, the data store coprocessor moves additional frame data to the data store. forwarding and frame alteration information is identified by the results of the search. the np2g provides two frame alteration techniques: hardware-assisted frame alteration and flexible frame alteration: ibm powernp np2g network processor preliminary general information page 38 of 539 np2_ds_sec01_over.fm.01 february 12, 2003 in hardware-assisted frame alteration, commands are passed to the egress eds hardware during enqueueing. these commands can, for example, up date the ttl field in an ip header, generate frame crc, or overlay an existing layer 2 wrapper with a new one. in flexible frame alteration, the picocode allocates additional buffers and the data store coprocessor places data into these buffers. the additional buffers allow prepending of data to a received frame and bypassing part of the received data when transmitting. this is useful for frame fragmentation when a when an ip header and mac header must be prepended to received data in order to form a frame fragment of the correct size. 17. the enqueue coprocessor builds the necessary information to enqueue the frame to the egress eds and provides it to the cu, which guarantees the frame order as the data moves from the 24 threads of the dppu to the egress eds queues. 18. the frame is enqueued to the egress eds. the frame is enqueued to the egress eds, which forwards it to the egress scheduler (if enabled). the scheduler selects the frame for transmission to a target port queue. if the scheduler is not enabled, the eds will forward the frame directly to a target queue. the egress eds selects frames for transmission from the target port queue and moves their data to the egress pmm. ibm powernp np2g preliminary network processor np2_ds_sec02_phys.fm.01 february 12, 2003 physical description page 39 of 539 2. physical description figure 2-1. device interfaces data stores sdram sram clk, test, reset, etc. eeprom interface eeprom ibm powernp a gmll tbi pos c smll gmll tbi d pci interface note: the memory array consists of the following ddr sdrams: drams 0 and 4 2 devices each drams 2 and 3 1 device each dram 6 6 devices ddr sdram ddr control store control store ddr sdram for d0/2/3 interface control store ddr sdram for d4 interface control store ddr sdram for d6 interface pos pos smll gmll tbi np2g ibm powernp np2g network processor preliminary physical description page 40 of 539 np2_ds_sec02_phys.fm.01 february 12, 2003 2.1 pin information this section describes the many interfaces and asso ciated pins of the np2g network processor. for a summary of all the device?s interfaces and how many pins each contains, see table 2-1 . for information on signal pin locations, see table 2-38: complete signal pin listing by signal name on page 88 and table 2-39: complete signal pin listing by grid position on page 98. the following table groups the interfaces and pins by function, briefly describes them, and points to the loca- tion of specific info rmation in the chapter. table 2-1. signal pin functions (page 1 of 2) pin type function resources flow control table 2-3: flow control pins on page 41 z0 and z1 zbt sram interface interface with the z0 and z1 zbt sram for lookups table 2-4: z0 zbt sram interface pins on page 42 table 2-5: z1 zbt sram interface pins on page 42 figure 2-2: zbt sram timing diagram on page 43 d3, d2, and d0 memory interface with the ddr sdram used to implement the d3, d2, and d0 memories table 2-10: d3 and d2 interface pins on page 51 table 2-11: d0 memory pins on page 52 figure 2-3: ddr control timing diagram on page 45 figure 2-4: ddr read timing diagram on page 46 figure 2-5: ddr write output timing diagram on page 47 d4_0 and d4_1 memory interface with the ddr dram used to implement the d4 memories table 2-12: d4_0 and d4_1 interface pins on page 53 figure 2-3: ddr control timing diagram on page 45 figure 2-4: ddr read timing diagram on page 46 figure 2-5: ddr write output timing diagram on page 47 d6_5, d6_4, d6_3, d6_2, d6_1, and d6_0 memory interface with the ddr sdram used to implement the powerpc store table 2-13: d6_5, d6_4, d6_3, d6_2, d6_1, and d6_0 memory pins on page 54 figure 2-3: ddr control timing diagram on page 45 figure 2-4: ddr read timing diagram on page 46 figure 2-5: ddr write output timing diagram on page 47 ds1 and ds0 memory interface with the ddr dram used to implement the ds1 and ds0 memories table 2-14: ds1 and ds0 interface pins on page 55 figure 2-3: ddr control timing diagram on page 45 figure 2-4: ddr read timing diagram on page 46 figure 2-5: ddr write output timing diagram on page 47 pmm interface interface with the physical layer devices through the following buses: table 2-15: pmm interface pins on page 56 table 2-16: pmm interface pin multiplexing on page 57 figure 2-6: np2g dmu bus clock connections on page 58 tbi table 2-18: parallel data bit to 8b /10b position mapping (tbi interface) on page 59 table 2-19: pmm interface pins: tbi mode on page 59 figure 2-8: tbi timing diagram on page 61 gmii table 2-21: pmm interface pins: gmii mode on page 63 figure 2-9: gmii timing diagram on page 64 smii table 2-23: pmm interface pins: smii mode on page 65 figure 2-10: smii timing diagram on page 66 pos figure 2-7: np2g dmu bus cloc k connections (pos overview) on page 59 table 2-25: pos signals on page 67 figure 2-11: pos transmit timing diagram on page 68 figure 2-12: pos receive timing diagram on page 69 ibm powernp np2g preliminary network processor np2_ds_sec02_phys.fm.01 february 12, 2003 physical description page 41 of 539 2.1.1 ingress-to-egress wrap (iew) pins 2.1.2 flow control interface pins pci interface interface to the pci bus table 2-27: pci pins on page 71 figure 2-13: pci timing diagram on page 72 management bus translated into various ?host? buses by an external fpga (spm) table 2-29: management bus pins on page 73 figure 2-14: spm bus timing diagram on page 74 miscellaneous va rious interfaces table 2-31: miscellaneous pins on page 75 table 2-32: signals requiring pull-up or pull-down on page 77 table 2-2. ingress-to-egress wrap (iew) pins signal (clock domain) description type master_grant_a(1:0) master_grant_b(1:0) (iew clk * 2) these i/o signals are used to receive status in formation from the egress side. both ?a? bits should be connected to the send_grant_a pin and both ?b? bits should be connected to the send_grant_b pin. input 5.0 v-tolerant 3.3 v lvttl send_grant_a send_grant_b (iew clk * 2) send grants a and b indicate whether the iew is able to receive cells from the ingress side. 0 unable 1able the np2g changes the state of these signal s for use on the corresponding master_grant inputs. output 5.0 v-tolerant 3.3 v lvttl table 2-3. flow control pins signal description type i_freeq_th ingress free queue threshold 0 threshold not exceeded 1 threshold exceeded output 5.0 v-tolerant 3.3 v lvttl res_sync remote egress status synchronization (sync) may be driven by the network processor to indicate the start of time division multiple x cycle for passing egress status information to the ingress side. input/output 5.0 v-tolerant 3.3 v lvttl res_data remote egress status data is driven by the network processor to indicate its congestion status to the ingress side during a designated time slot. 0 not exceeded 1 network processor?s exponentially wei ghted moving average (ewma) of the egress offered rate exceeds the configured threshold. input/output 5.0 v-tolerant 3.3 v lvttl table 2-1. signal pin functions (page 2 of 2) pin type function resources ibm powernp np2g network processor preliminary physical description page 42 of 539 np2_ds_sec02_phys.fm.01 february 12, 2003 2.1.3 zbt interface pins these pins interface with z0 and z1 zbt sram for lookups as described in table 2-4 and table 2-5 . table 2-4. z0 zbt sram interface pins signal description type lu_clk look-up clock. 7.5 ns period (133 mhz). output cmos 2.5 v lu_addr(19:0) look-up address signals are sampled by the rising edge of lu_clk. output cmos 2.5 v lu_data(35:0) look-up data. when used as sram inputs, the rising edge of lu_clk samples these sig- nals. input/output cmos 2.5 v lu_r_wrt look-up read/write control signal is sa mpled by the rising edge of lu_clk. 0write 1 read output cmos 2.5 v cam_cp_response(13:0) coprocessor response bus (crb). results from an external coprocessor are sent to a specified thread's crb coprocessor and stored into the crb results register. input/output cmos 2.5 v table 2-5. z1 zbt sram interface pins signal description type sch_clk sram clock input. 7.5 ns period (133 mhz). output cmos 2.5 v sch_addr(18:0) sram address signals are sampled by the rising edge of lu_clk. output cmos 2.5 v sch_data(17:0) data bus. when used as sram inpu t, the rising edge of sch_clk samples these signals. input/output cmos 2.5 v sch_r_wrt read/write control signal is sampled by the rising edge of sch_clk. 0write 1 read output cmos 2.5 v ibm powernp np2g preliminary network processor np2_ds_sec02_phys.fm.01 february 12, 2003 physical description page 43 of 539 figure 2-2. zbt sram timing diagram 30 pf ts +v dd /2 50 ? t ck t ch t cl t da (max) t da (min) t dwe (min) t dwe (max) t dckon t dckoff t dh t ds t dd (min) outputs inputs xx_clk xx_addr xx_r_wrt xx_data t dd (max) notes: 1) xx = lu or sch 2) data invalid 3) v dd = 2.5 v 4) output load 50 ohms and 30 pf ibm powernp np2g network processor preliminary physical description page 44 of 539 np2_ds_sec02_phys.fm.01 february 12, 2003 table 2-6. zbt sram timing diagram legend (for figure 2-2) symbol symbol description minimum (ns) maximum (ns) t ck zbt cycle time 7.5 t ch clock pulse width high 3.5 3.7 t cl clock pulse width low 3.8 4.0 t da address output delay 1.0 3.0 t dwe read/write output delay 1.1 2.6 t dd data output delay 1.1 2.7 t dckon data output turn on 1.3 4.1 t dckoff data output turn off 0.8 3.0 t ds input data setup time 1.0 t dh input data hold time 0 note: all delays are measured with 1 ns slew time measured from 10 - 90% of input voltage. ibm powernp np2g preliminary network processor np2_ds_sec02_phys.fm.01 february 12, 2003 physical description page 45 of 539 2.1.4 ddr dram interface pins the pins described here interface with ddr dram to implement data store, control store, and the powerpc store. the control, read, and write timing diagrams ( figure 2-3 , figure 2-4 , and figure 2-5 ) apply to all pin tables in this section. figure 2-3. ddr control timing diagram t da (max) t da (min) dx_addr t ch t cl dy_clk dy_nclk t dw (max) t dw (min) dx_we t dcs (max) t dcs (min) dx_cs t dba (max) t dba (min) dy_ba t dras (max) t dras (min) dy_ras t dcas (max) t dcas (min) dy_cas 30 pf ts +v dd /2 50 ? notes: 3) data invalid 4) v dd = 2.5 v 1) dx = d0, d2, d3, d4, d6, ds0, ds1 2) dy = da, db, dc, dd, de 5) output load 50 ohms and 30 pf ibm powernp np2g network processor preliminary physical description page 46 of 539 np2_ds_sec02_phys.fm.01 february 12, 2003 figure 2-4. ddr read timing diagram dx_dq t dqsq (max) t dqsq (max) t ck t ch t cl dy_clk dy_nclk dx_dqs t css notes: 3) data invalid 4) v dd = 2.5 v 1) dx = d0, d2, d3, d4, d6, ds0, ds1 2) dy = da, db, dc, dd, de 5) ouput load 50 ohms and 30 pf 30 pf ts +v dd /2 50 ? t dqsq (min) t dqsq (min) ibm powernp np2g preliminary network processor np2_ds_sec02_phys.fm.01 february 12, 2003 physical description page 47 of 539 figure 2-5. ddr write outp ut timing diagram t ck t ch t cl dy_clk t csd t ds t dh dy_nclk dx_dqs dx_dq t dh t ds notes: 3) data invalid 4) v dd = 2.5 v 1) dx = d0, d2, d3, d4, d6, ds0, ds1 2) dy = da, db, dc, dd, de 5) ouput load 50 ohms and 30 pf 6) byte enablement is for d6 only. 30 pf ts +v dd /2 50 ? t bs t bh d6_byteen t bh t bs ibm powernp np2g network processor preliminary physical description page 48 of 539 np2_ds_sec02_phys.fm.01 february 12, 2003 table 2-7. ddr timing diagram legend (for figure 2-3, figure 2-4, and figure 2-5) values are for d0, d2, d3, d4, ds0, and ds1 symbol symbol description minimum (ns) maximum (ns) t ck ddr clock cycle time 7.5 t ch clock pulse width high 0.45 * t ck 0.55 * t ck t cl clock pulse width low 0.45 * t ck 0.55 * t ck t da address output delay 1.7 4.8 t dw write enable output delay 2.0 5.2 t dcs chip select output delay 1.9 5.2 t ba bank address output delay 1.9 5.2 t dras ras output delay 1.9 5.4 t dcas cas output delay 1.9 5.4 t csd dy_clk to dx_dqs strobe output delay 0.5 1.4 t ds data to strobe output setup time 1.0 t dh data to strobe output hold time 1.2 t css clock to strobe input skew -2.0 2.5 t dqsq data to dqs input skew 1.0 1.1 note: all delays are measured with 1 ns skew time measured from 10-90% of input voltage. all measurements made with test load of 50 ohms and 30 pf. the dx_dqs pin descriptions for the ds0, ds1, and d4 interfaces ( section 2.1.4.2 on page 53 and section 2.1.4.4 on page 55) describe the association of data strobe to data. this association is dependent on the setting of strobe_cntl in the dram configuration r egister is described in section 13.1.2 on page 434. ibm powernp np2g preliminary network processor np2_ds_sec02_phys.fm.01 february 12, 2003 physical description page 49 of 539 table 2-8. ddr timing diagram legend (for figure 2-3, figure 2-4, and figure 2-5) values are for d6 in 4-bit interface mode. symbol symbol description minimum (ns) maximum (ns) t ck ddr clock cycle time 7.5 t ch clock pulse width high 0.45 * t ck 0.55 * t ck t cl clock pulse width low 0.45 * t ck 0.55 * t ck t da address output delay 2.4 6.0 t dw write enable output delay 2.4 5.6 t dcs chip select output delay 2.5 5.9 t ba bank address output delay 2.3 5.7 t dras ras output delay 2.4 5.7 t dcas cas output delay 2.5 5.7 t csd dy_clk to dx_dqs strobe output delay 0.7 1.6 t ds data to strobe output setup time 1.5 t dh data to strobe output hold time 1.0 t bs byte enable to strobe setup time 1.1 t bh byte enable to strobe hold time 1.3 t css clock to strobe input skew -2.0 3.0 t dqsq data to dqs input skew for d6_data_00-03 1.0 1.3 data to dqs input skew for d6_data_04-07 0.9 1.3 data to dqs input skew for d6_data_08-11 1.0 1.4 data to dqs input skew for d6_data_12-15 1.0 1.3 data to dqs input skew for d6_parity_00 1.7 1.1 data to dqs input skew for d6_parity_01 1.7 1.1 note: all delays are measured with 1 ns slew time measured from 10-90% of input voltage. all measurements made with test load of 50 ohms and 30 pf. ibm powernp np2g network processor preliminary physical description page 50 of 539 np2_ds_sec02_phys.fm.01 february 12, 2003 table 2-9. ddr timing diagram legend (for figure 2-3, figure 2-4, and figure 2-5) values are for d6 in 16-bit interface mode. symbol symbol description minimum (ns) maximum (ns) t ck ddr clock cycle time 7.5 t ch clock pulse width high 0.45 * t ck 0.55 * t ck t cl clock pulse width low 0.45 * t ck 0.55 * t ck t da address output delay 2.4 6.0 t dw write enable output delay 2.4 5.6 t dcs chip select output delay 2.5 5.9 t ba bank address output delay 2.3 5.7 t dras ras output delay 2.4 5.7 t dcas cas output delay 2.5 5.7 t csd dy_clk to dx_dqs strobe output delay 0.8 1.6 t ds data to strobe output setup time 1.5 t dh data to strobe output hold time 1.0 t bs byte enable to strobe setup time 1.1 t bh byte enable to strobe hold time 1.3 t css clock to strobe input skew -2.1 2.9 t dqsq data to dqs input skew for d6_data_00-07 0.8 1.3 data to dqs input skew for d6_data_08-15 0.9 1.4 data to dqs input skew for d6_parity_00 1.7 1.1 data to dqs input skew for d6_parity_01 1.7 1.1 note: all delays are measured with 1 ns slew time measured from 10-90% of input voltage. all measurements made with test load of 50 ohms and 30 pf. ibm powernp np2g preliminary network processor np2_ds_sec02_phys.fm.01 february 12, 2003 physical description page 51 of 539 2.1.4.1 d3, d2, and d0 interface pins these pins interface with the ddr sdram used to implement the d3, d2, and d0 control stores. table 2-10. d3 and d2 interface pins signal description type shared signals db_clk the positive pin of an output differential pair. 133 mhz. common to the d3 and d2 memory devices. output sstl2 2.5 v db_clk the negative pin of an output differential pair. 133 mhz. common to the d3 and d2 memory devices. output sstl2 2.5 v db_ras common row address strobe (common to d3 and d2). output sstl2 2.5 v db_cas common column address strobe (common to d3 and d2). output sstl2 2.5 v db_ba(1:0) common bank address (common to d3 and d2). output sstl2 2.5 v d3 signals d3_addr(12:0) d3 address output cmos 2.5 v d3_dqs(1:0) d3 data strobes input/output sstl2 2.5 v d3_data(15:0) d3 data bus input/output sstl2 2.5 v d3_we d3 write enable output cmos 2.5 v d3_cs d3 chip select output cmos 2.5 v d2 signals d2_addr(12:0) d2 address output cmos 2.5 v d2_dqs(1:0) d2 data strobes input/output sstl2 2.5 v d2_data(15:0) d2 data bus input/output sstl2 2.5 v d2_we d2 write enable output cmos 2.5 v d2_cs d2 chip select output cmos 2.5 v ibm powernp np2g network processor preliminary physical description page 52 of 539 np2_ds_sec02_phys.fm.01 february 12, 2003 table 2-11. d0 memory pins signal description type d0_0 and d0_1 shared signals de_clk the positive pin of an output differential pa ir. 133 mhz. common to the d0_0/1 memory devices. output sstl2 2.5 v de_clk the negative pin of an output differential pair. 133 mhz. common to the d0_0/1 devices. output sstl2 2.5 v de_ras common row address strobe output cmos 2.5 v de_cas common column address strobe output cmos 2.5 v de_ba(1:0) common bank address output cmos 2.5 v d0_addr(12:0) d0 address output cmos 2.5 v d0_dqs(3:0) d0 data strobes input/output sstl2 2.5 v d0_data(31:0) d0 data bus input/output sstl2 2.5 v d0_we d0 write enable output cmos 2.5 v d0_cs d0 chip select output cmos 2.5 v ibm powernp np2g preliminary network processor np2_ds_sec02_phys.fm.01 february 12, 2003 physical description page 53 of 539 2.1.4.2 d4_0 and d4_1 interface pins these pins interface with the ddr dram used to implement the d4 control store. table 2-12. d4_0 and d4_1 interface pins signal description type dd_clk the positive pin of an output differential pa ir. 133 mhz. common to the d4_0/1 memory devices. output sstl2 2.5 v dd_clk the negative pin of an output differential pair. 133 mhz. common to the d4_0/1 memory devices. output sstl2 2.5 v dd_ras common row address strobe output cmos 2.5 v dd_cas common column address strobe output cmos 2.5 v dd_ba(1:0) common bank address output cmos 2.5 v d4_addr(12:0) d4 address output cmos 2.5 v d4_dqs(3:0) d4 data strobes. data bits are associ ated with strobe bits as follows: strobe_cntl = ?01? strobe_cntl = ?00? 3 ? 31:24 2 ? 23:16 1 ? 15:8 0 31:0 7:0 input/output sstl2 2.5 v d4_data(31:0) d4 data bus input/output sstl2 2.5 v d4_we d4 write enable output cmos 2.5 v d4_cs d4 chip select output cmos 2.5 v ibm powernp np2g network processor preliminary physical description page 54 of 539 np2_ds_sec02_phys.fm.01 february 12, 2003 2.1.4.3 d6_ x interface pins these pins interface with the ddr sdram used to implement the powerpc store. table 2-13. d6_5, d6_4, d6_3, d6_2, d6_1, and d6_0 memory pins signal description type da_clk the positive pin of an output differential pa ir. 133 mhz. common to the d6 memory devices. output sstl2 2.5 v da_clk the negative pin of an output differential pair. 133 mhz. common to the d6 memory devices. output sstl2 2.5 v da_ras common row address strobe (common to d6). output sstl2 2.5 v da_cas common column address strobe (common to d6). output sstl2 2.5 v da_ba(1:0) common bank address (common to d6). output sstl2 2.5 v d6_we common write enable (common to d6). output sstl2 2.5 v d6_addr(12:0) d6 address output sstl2 2.5 v d6_cs d6 chip select output sstl2 2.5 v d6_dqs(3:0) d6 data strobes. data bits are asso ciated with strobe bits as follows: d6_dram_size = ?0xx? d6_dram_size = ?1xx? 3? 15:12 2 15:8 11:8 1? 7:4 07:0 3:0 input/output sstl2 2.5 v d6_data(15:0) d6 data bus input/output sstl2 2.5 v d6_byteen (1:0) d6 byte enables byte masking write to d6 . data is masked when d6_byteen is high. data bits are associated with byte enable as follows: 1 15:8 07:0 input/output sstl2 2.5 v d6_parity(1:0) d6 parity signals, one per byte. must go to separ ate chips to allow for byte write capability. data bits are associated wi th parity bits as follows: 1 15:8 07:0 input/output sstl2 2.5 v d6_dqs_par(1:0) d6 data strobe for the parity signals input/output sstl2 2.5 v ibm powernp np2g preliminary network processor np2_ds_sec02_phys.fm.01 february 12, 2003 physical description page 55 of 539 2.1.4.4 ds1 and ds0 interface pins these pins interface with the ddr dram used to implement the ds1 and dso data stores. table 2-14. ds1 and ds0 interface pins (page 1 of 2) signal description type shared signals dc_clk the positive pin of an output differential pair. 133 mhz. common to the ds1 and ds0 memory devices. output sstl2 2.5 v dc_clk the negative pin of an output differential pair. 133 mhz. common to the ds1 and ds0 memory devices. output sstl2 2.5 v dc_ras common row address strobe (common to ds1 and ds0). output sstl2 2.5 v dc_cas common column address str obe (common to ds1 and ds0). output sstl2 2.5 v dc_ba(1:0) common bank address (common to ds1 and ds0). output sstl2 2.5 v ds1 signals ds1_addr(12:0) ds1 address output cmos 2.5 v ds1_dqs(3:0) ds1 data strobes. data bits are asso ciated with strobe bits as follows: strobe_cntl = ?01? strobe_cntl = ?00? 3 ? 31:24 2 ? 23:16 1 ? 15:8 0 31:0 7:0 input/output sstl2 2.5 v ds1_data(31:0) ds1 data bus input/output sstl2 2.5 v ds1_we ds1 write enable output cmos 2.5 v ds1_cs ds1 chip select output cmos 2.5 v ds0 signals ds0_addr(12:0) ds0 address output cmos 2.5 v ds0_dqs(3:0) ds0 data strobes. data bits are asso ciated with strobe bits as follows: strobe_cntl = ?01? strobe_cntl = ?00? 3 ? 31:24 2 ? 23:16 1 ? 15:8 0 31:0 7:0 input/output sstl2 2.5 v ibm powernp np2g network processor preliminary physical description page 56 of 539 np2_ds_sec02_phys.fm.01 february 12, 2003 2.1.5 pmm interface pins these pins allow the physical mac mu ltiplexer (pmm) to interface with the physical layer devices. the np2g has different sets of pins for the ten-bit (tbi), gigabit media-independent (gmii), serial media-independent (smii), and packet over sonet (pos) interfaces. ds0_data(31:0) ds0 data bus input/output sstl2 2.5 v ds0_we ds0 write enable output cmos 2.5 v ds0_cs ds0 chip select output cmos 2.5 v table 2-15. pmm interface pins signal description type dmu_a(30:0) define the first of the four pmm interfaces and can be configured for tbi, smii, gmii, or pos. see table 2-16: pmm interface pin multiplexing on page 57 for pin directions and definitions. 5.0 v-tolerant 3.3 v lvttl dmu_c(30:0) define the third of the four pmm interfaces and can be configured for tbi, smii, gmii, or pos. see table 2-16: pmm interface pin multiplexing on page 57 for pin directions and definitions. 5.0 v-tolerant 3.3 v lvttl dmu_d(30:0) define the fourth of the four pmm interfaces and can be configured for tbi, smii, gmii, debug, or pos. see table 2-16: pmm interface pin multiplexing on page 57 for pin directions and definitions. 5.0 v-tolerant 3.3 v lvttl table 2-14. ds1 and ds0 interface pins (page 2 of 2) signal description type ibm powernp np2g preliminary network processor np2_ds_sec02_phys.fm.01 february 12, 2003 physical description page 57 of 539 table 2-16. pmm interface pin multiplexing pin(s) pin mode interface type dmu_a, dmu_c dmu_d gmii tbi smii debug (dmu_d only) 8-bit pos 30 o o rxaddr(1) o 29 o o rxaddr(0) o 28 o o txaddr(1) o 27 o o txaddr(0) o 26 o o txsof o 25 o o tx_valid_byte o txeof o (24:17) o o tx_data(7:0) o tx_data(0:7) o tx_data(9:2) o debug(23:16) o txdata(7:0) o (16:9) i o rx_data(7:0) i rx_data(0:7) i rx_data(9:2) i debug(15:8) o rxdata(7:0) i 8oo tx_clk 8 ns tx_clk 8 ns ??? 7oo tx_en o tx_data(8) o tx_data(1) o debug(7) o txen o 6 i/o i/o tx_er o tx_data(9) o tx_data(0) o debug(6) o txpfa i 5 i i/o rx_valid_byte i rx_data(8) i rx_data(1) i debug(5) o rxpfa i 4 i i/o tx_byte_credit i rx_data(9) i rx_data(0) i debug(4) o rxval i 3 i i/o rx_clk i 8 ns rx_clk1 i 16 ns clk i 8 ns debug(3) o clk i 10 ns 2 i/o i/o rx_dv i rx_clk0 i 16 ns sync o debug(2) o rxeof i 1 i/o i/o rx_er i sig_det i sync2 o debug(1) o rxerr i 0 i/o i/o cpdetect (0 = cpf) - input cpdetect (0 = cpf) - input activity - output cpdetect (0 = cpf) - input debug(0) o rxenb o ibm powernp np2g network processor preliminary physical description page 58 of 539 np2_ds_sec02_phys.fm.01 february 12, 2003 figure 2-6. np2g dmu bus clock connections gmii phy dmu_*(8) dmu_*(3) clock125 tx_clk rx_clk dmu_*(8) dmu_*(3) (1 port) note: trace lengths to all inputs will be matched on the card. nc ibm powernp np2g tbi phy (10 ports) dmu_*(8) dmu_*(3) dmu_*(2) tx_clk rx_clk1 rx_clk0 clock125 53.3 mhz oscillator pll 266 mhz 62.5 mhz 62.5 mhz clock_core 125 mhz oscillator x5 notes : each figure above illustrates a single dmu bus and applies to any of the three dmu busses. the ?dmu_*? labels represent any of the th ree dmu busses (dmu_a, dmu_c, or dmu_d). smii phy (6 ports) smii phy (4 ports) gmii interface smii interface tbi interface 125 mhz oscillator 125 mhz oscillator asynchronous interface ibm powernp np2g ibm powernp np2g ibm powernp np2g preliminary network processor np2_ds_sec02_phys.fm.01 february 12, 2003 physical description page 59 of 539 2.1.5.1 tbi bus pins figure 2-7. np2g dmu bus clock connections (pos overview) table 2-17. pmm interface pins: debug (dmu_d only) signal description type debug (23:0) when dmu_d is configured as the debug bus, signal s internal to the np2g are available to be observed externally. this m ode is supported only when its us e is directed by an ibm net- work processor appl ication engineer. it is recommended that board designs provi de for the attachment of scope probes to observe this interface which runs at 133 mhz. output 5.0 v-tolerant 3.3 v lvttl table 2-18. parallel data bit to 8b/10b position mapping (tbi interface) parallel data bit 0123456789 8b/10b bit position abcde f gh i j table 2-19. pmm interface pins: tbi mode (page 1 of 2) signal description type tx_data(9:0) transmit data. data bus to the phy, synchronous to tx_clk. output 5.0 v-tolerant 3.3 v lvttl rx_data(9:0) receive data. data bus from the phy, synchronous to rx_clk1 and rx_clk0. (data switches at double the frequency of rx_clk1 or rx_clk0.) input 5.0 v-tolerant 3.3 v lvttl rx_clk1 receive clock, 62.5 mhz. rx_data is valid on the rising edge of this clock. input 5.0 v-tolerant 3.3 v lvttl rx_clk0 receive clock, 62.5 mhz. this signal is 18 0 degrees out of phase with rx_clk1. rx_data is valid on the rising edge of this clock. input 5.0 v-tolerant 3.3 v lvttl note: see table 2-16: pmm interface pin multiplexing on page 57 for pin directions (i/o) and definitions. atm framer dmu_*(8) dmu_*(3) note: trace lengths to all inputs will be matched on the card. 100 mhz oscillator rxclk txclk nc single dmu bus (applies to dmu a?d) ibm powernp np2g ibm powernp np2g network processor preliminary physical description page 60 of 539 np2_ds_sec02_phys.fm.01 february 12, 2003 sig_det signal detect. signal asserted by the phy to indicate that the physical media are valid. input 5.0 v-tolerant 3.3 v lvttl cpdetect this pin must be pulled low to indicate when a control point is active on this dmu inter- face. otherwise, this signal s hould be pulled high (inactive). the state of the signal is captured in the da ta mover unit (dmu) configuration (page 485) when the reset signal is deasserted. after dmu configuration, this signal is driven by t he network processor to indicate the sta- tus of the tbi interface. 0 tbi interface is not in the data pass state (link down) 1 tbi interface is in the data pass state (occurs when auto-negotiation is complete, or when idles are detected (if an is disabled)) pulse tbi interface is in a data pass state and is either receiving or transmitting. the line pulses once per frame trans mitted or received at a maximum rate of 8hz. input/output 5.0 v-tolerant 3.3 v lvttl tx_clk 125 mhz clock transmit clock to the phy. duri ng operation, the network processor drives this signal to indicate that a transmit or receive is in progress for this interface. output 5.0 v-tolerant 3.3 v lvttl table 2-19. pmm interface pins: tbi mode (page 2 of 2) signal description type note: see table 2-16: pmm interface pin multiplexing on page 57 for pin directions (i/o) and definitions. ibm powernp np2g preliminary network processor np2_ds_sec02_phys.fm.01 february 12, 2003 physical description page 61 of 539 figure 2-8. tbi timing diagram 30 pf ts +v dd /2 50 w t xck t xch t xcl t rck t rch t rcl t rcl t rch tx_clk tx_data rx_clk0 rx_clk1 rx_data transmit timings receive timings t dd (max) t dd (min) t rdh t rds t rdh t rds t rsh t rss rx_data t rck notes: 1) v dd = 3.3 v 2) data invalid 3) output load 50 ohms and 30 pf ibm powernp np2g network processor preliminary physical description page 62 of 539 np2_ds_sec02_phys.fm.01 february 12, 2003 table 2-20. tbi timing diagram legend (for figure 2-8) symbol symbol description minimum (ns) maximum (ns) t xck tx_clk transmit cycle time 8 t xch tx_clk pulse width high 3.5 4.0 t xcl tx_clk pulse width low 4.0 4.5 t dd tx_data_(7:0) output delay 3.2 4.7 t rck rx_clk0/rx_clk1 receive cycle time 16 t rch rx_clk0/rx_clk1 pulse width high 7 t rcl rx_clk0/rx_clk1 pulse width low 7 t rds rx_data_(9:0) setup time clk0 0.7 t rdh rx_data_(9:0) hold time clk0 1.2 t rds rx_data_(9:0) setup time clk1 0.7 t rdh rx_data_(9:0) hold time clk1 1.2 note: all delays are measured with 1 ns slew time measured from 10-90% of input voltage. ibm powernp np2g preliminary network processor np2_ds_sec02_phys.fm.01 february 12, 2003 physical description page 63 of 539 2.1.5.2 gmii bus pins table 2-21. pmm interface pins: gmii mode signal description type tx_data(7:0) transmit data. data bus to the phy, synchronous to tx_clk. output 5.0 v-tolerant 3.3 v lvttl rx_data(7:0) received data. data bus fr om the phy, synchronous to rx_clk. input 5.0 v-tolerant 3.3 v lvttl tx_en transmit data enabled to the phy, synchronous to tx_clk. 0 end of frame transmission 1 active frame transmission output 5.0 v-tolerant 3.3 v lvttl tx_er transmit error, synchronous to the tx_clk. 0 no error detected 1 informs the phy that mac detected an error output 5.0 v-tolerant 3.3 v lvttl rx_valid_byte receive valid data, sync hronous to the rx_clk. 0 data invalid 1 byte of data (from the phy) on rx_data is valid. for a standard gmii connection, this signal can be tied to ?1? on the card. input 5.0 v-tolerant 3.3 v lvttl tx_byte_credit transmit next data value, asynchronous. 0 do not send next data byte 1 asserted. phy indicates that the next tx_data value may be sent. for a standard gmii connection, this signal can be tied to ?1? on the card. input 5.0 v-tolerant 3.3 v lvttl tx_valid_byte transmit valid data, synchronous to tx_clock 0 data invalid 1 byte of data (from the network processor) on tx_data is valid. output 5.0 v-tolerant 3.3 v lvttl rx_clk 125 mhz receive medium clock generated by the phy. input 5.0 v-tolerant 3.3 v lvttl rx_dv receive data valid (from the phy), synchronous to rx_clk. 0 end of frame transmission. 1 active frame transmission. input 5.0 v-tolerant 3.3 v lvttl rx_er receive error, synchronous to rx_clk. 0 no error detected 1 informs the mac that phy detected an error input 5.0 v-tolerant 3.3 v lvttl tx_clk 125 mhz transmit clock to the ph y. during operation, the network processor driv es this sig- nal to indicate that a transmit is in progress for this interface. output 5.0 v-tolerant 3.3 v lvttl cpdetect this pin must be pulled low to indicate when a c ontrol point is active on this dmu interface. otherwise, this signal shoul d be pulled high (inactive). the state of the signal is captured in the da ta mover unit (dmu) configuration (page 485) when the reset signal is deasserted. input 5.0 v-tolerant 3.3 v lvttl note: the np2g supports gmii in full-duplex mode only. see table 2-16: pmm interface pin multiplexing on page 57 for pin directi ons (i/o) and definitions. ibm powernp np2g network processor preliminary physical description page 64 of 539 np2_ds_sec02_phys.fm.01 february 12, 2003 figure 2-9. gmii timing diagram 30 pf ts 50 ? t ck t xch t xcl t dd (min) t dd (max) t den (min) t den (max) t der (min) t der (max) t dbv (min) t dvb (max) t rch t rcl t rdh t rds t rvh t rvs t reh t res t rdvh t rdvs tx_clk tx_data tx_en tx_er tx_valid_byte rx_clk rx_data rx_valid_byte rx_er rx_dv transmit timings receive timings notes: 1) v dd = 3.3 v 2) data invalid 3) output load 50 ohms and 30 pf ibm powernp np2g preliminary network processor np2_ds_sec02_phys.fm.01 february 12, 2003 physical description page 65 of 539 2.1.5.3 smii bus pins table 2-22. gmii timing diagram legend (for figure 2-9) symbol symbol description minimum (ns) maximum (ns) t ck tx_clk cycle time 8 t xch transmit clock pulse width high 3.5 3.9 t xcl transmit clock pulse width low 4.1 4.5 t rch receive clock pulse width high 2.5 t rcl receive clock pulse width low 2.5 t dd tx_data output delay 3.7 4.6 t der tx_er output delay 3.7 4.6 t dvb tx_valid_byte output delay 3.7 4.5 t den tx_en output delay 3.2 4.7 t rds rx_data setup time 1.9 t rdh rx_data hold time 0 t rvs rx_valid_byte setup time 1.9 t rvh rx_valid_byte hold time 0 t res rx_er setup time 1.8 t reh rx_er hold time 0 t rdvs rx_dv setup time 1.9 t rdvh rx_dv hold time 0 1. all delays are measured with 1 ns slew time measured from 10-90% of input voltage. table 2-23. pmm interface pins: smii mode signal description type tx_data(9:0) transmit data. data bus to the phy - contains ten streams of serial transmit data. each serial stream is connected to a unique port. synchronous to the common clock (clk). output 5.0 v-tolerant 3.3 v lvttl rx_data(9:0) received data. data bus from the phy - contai ns ten streams of serial receive data. each serial stream is connected to a unique port. synchronous to the common clock (clk). input 5.0 v-tolerant 3.3 v lvttl sync asserted for one tx_clk cycle once every ten tx _clk cycles. assertion indicates the begin- ning of a 10-bit segment on both tx_data and rx_data. output 5.0 v-tolerant 3.3 v lvttl sync2 logically identical to sync and provided for fanout purposes. output 5.0 v-tolerant 3.3 v lvttl cpdetect this pin must be pulled low to indicate when a control point is active on this dmu inter- face. otherwise, this signal s hould be pulled high (inactive). the state of the signal is captured in the data mover unit (dmu) configuration (see 13.24 data mover unit (dmu) configuration registers on page 485) when the reset signal is deasserted. input 5.0 v-tolerant 3.3 v lvttl ibm powernp np2g network processor preliminary physical description page 66 of 539 np2_ds_sec02_phys.fm.01 february 12, 2003 figure 2-10. smii timing diagram table 2-24. smii timing diagram legend (for figure 2-10) symbol symbol description minimum (ns) maximum (ns) t ck clk cycle time 8 t ch clk pulse width high 4 t cl clk pulse width low 4 t dd tx_data_(9:0) output delay 1.9 4.7 tds sync output delay 2.2 4.5 tds2 sync2 output delay 2.3 4.5 trs rx_data_(9:0) setup time 0.8 trh rx_data_(9:0) hold time 0.2 1. all delays are measured with 1 ns slew time measured from 10-90% of input voltage. 30 pf ts +v dd /2 50 ? t ck t ch t cl t dd (min) t dd (max) t ds (min) t ds (max) t ds2 (min) t ds2 (max) t rh t rs clk tx_data sync sync2 rx_data transmit timings receive timings notes: 1) v dd = 3.3 v 2) data invalid 3) output load 50 ohms and 30 pf ibm powernp np2g preliminary network processor np2_ds_sec02_phys.fm.01 february 12, 2003 physical description page 67 of 539 table 2-25. pos signals signal description type rxaddr(1:0) receive address bus selects a particular port in the framer for a data transfer. valid on the rising edge of clk. 5.0 v-tolerant 3.3 v lvttl rxdata(7:0) 8-bit mode receive pos data bus carries the frame word t hat is read from the fr amer?s fifo. rxdata transports the frame data in an 8-bit format. rxdata[7:0] is updated on the rising edge of clk. 5.0 v-tolerant 3.3 v lvttl clk pos clock provides timing for the pos framer interfac e. clk must cycle at a 100 mhz or lower instantaneous rate. 5.0 v-tolerant 3.3 v lvttl rxenb receive read enable controls read access fr om the framer?s receive interface. the framer?s addressed fifo is selected on the fa lling edge of rxenb. generated on the rising edge of clk. 5.0 v-tolerant 3.3 v lvttl rxeof receive end-of-frame marks the last word of a frame in rxdata. updated on the rising edge of clk. 5.0 v-tolerant 3.3 v lvttl rxerr receive packet error indicates that the rece ived packet contains an error and must be dis- carded. only asserted on the last word of a packet (when rxeof is also asserted). updated on the rising edge of clk. 5.0 v-tolerant 3.3 v lvttl rxval receive valid data output indicates the rece ive signals rxdata, rxeof, and rxerr are valid from the framer. updated on the rising edge of clk. 5.0 v-tolerant 3.3 v lvttl rxpfa receive polled frame-available input indicates that the fram ers polled receive fifo con- tains data. updated on the rising edge of clk. 5.0 v-tolerant 3.3 v lvttl txdata (7:0) 8-bit mode (31:0) 32-bit mode transmit utopia data bus carries the frame word that is wri tten to the framer?s transmit fifo. considered valid and written to a fram er?s transmit fifo on ly when the transmit interface is selected by using txenb . sampled on the rising edge of clk. 5.0 v-tolerant 3.3 v lvttl txen transmit write enable controls write access to the transmit interface. a framer port is selected on the falling edge of txenb . sampled on the rising edge of clk. 5.0 v-tolerant 3.3 v lvttl txaddr(1:0) transmit address bus uses txenb to select a particular fifo within the framer for a data transfer. sampled on the rising edge of clk. 5.0 v-tolerant 3.3 v lvttl txsof transmit start-of-frame marks the first word of a frame in txdata. sampled on the rising edge of clk. 5.0 v-tolerant 3.3 v lvttl txeof transmit end-of-frame marks the last word of a frame in txdata. sampled on the rising edge of clk. 5.0 v-tolerant 3.3 v lvttl txpadl (1:0) transmit padding length indicates the number of padding bytes included in the last word of the packet transferred in txdata. sampled on the rising edge of clk. when configured in 32-bit mode the last word may contain zero, one, two or three padding bytes and only txpadl[1:0] is used. txpadl[1:0] (32-bit mode) 00 packet ends on txdata[7:0] (txdata = dddd) 01 packet ends on txdata[15:8] (txdata = dddp) 10 packet ends on txdata[23:16] (txdata = ddpp) 11 packet ends on txdata[31:24] (txdata = dppp) 5.0 v-tolerant 3.3 v lvttl txpfa transmit polled frame-available output indicates that the poll ed framer?s transmit fifo has free available space and the np 2g can write data into the framer?s fifo. updated on the rising edge of clk. 5.0 v-tolerant 3.3 v lvttl ibm powernp np2g network processor preliminary physical description page 68 of 539 np2_ds_sec02_phys.fm.01 february 12, 2003 figure 2-11. pos transmit timing diagram 30 pf ts +v dd /2 50 ? t ck t ch t cl t dd (min) t dd (max) t dxa (min) t dxa (max) t dra (min) t dra (max) t dsof (min) t dsof (max) clk txdata txaddr rxaddr txsof t deof (min) t deof (max) t den (min) t den (max) t dpadl (min) t dpadl (max) t dren (min) t dren (max) txeof txen txpadl rxenb notes: 1) v dd = 3.3 v 2) data invalid 3) output load 50 ohms and 30 pf ibm powernp np2g preliminary network processor np2_ds_sec02_phys.fm.01 february 12, 2003 physical description page 69 of 539 figure 2-12. pos receive timing diagram 30 pf ts +v dd /2 50 ? notes: 1) v dd = 3.3 v 2) data invalid 3) output load 50 ohms and 30 pf t ck t ch t cl t rxh t rxs t rpfh t rpfs t tpfh t tpfs t rvh t rvs t reofh t reofs clk rxdata rxpfa rxerr rxval rxeof t tpfh t tpfs txpfa t rpadh rxpadl t rpads ibm powernp np2g network processor preliminary physical description page 70 of 539 np2_ds_sec02_phys.fm.01 february 12, 2003 table 2-26. pos timing diagram legend (for figure 2-11 and figure 2-12) symbol symbol description minimum (ns) maximum (ns) t ck clk cycle time 10 t ch clk clock width high 2.1 t cl clk clock width low 2.1 t dd tx_data_(31:0) output delay 2.2 4.6 t dxa tx_addr_(1:0) output delay 2.2 4.6 t dra rx_addr_(1:0) output delay 2.1 4.3 t dsof txsof output delay 2.3 4.6 t deof txeof output delay 2.2 4.5 t den txen output delay 1.9 4.7 t dpadl txpadl_(1:0) output delay 2.2 4.6 t dren rxenb output delay 1.5 4.3 t rxs rx_data_(31:0) setup time 1.9 t rxh rx_data_(31:0) hold time 0 t rvs rxval setup time 1.9 t rvh rxval hold time 0 t rers rxerr setup time 1.8 t rerh rxerr hold time 0 t reofs rxeof setup time 1.9 t reofh rxeof hold time 0 t rpfs rxpfa setup time 1.9 t rpfh rxpfa hold time 0 t tpfs txpfa setup time 1.6 t tpfh txpfa hold time 0 t rpads rxpadl setup time 1.8 t rpadh rxpadl hold time 0 1. all delays are measured with 1 ns slew time measured from 10-90% of input voltage. ibm powernp np2g preliminary network processor np2_ds_sec02_phys.fm.01 february 12, 2003 physical description page 71 of 539 2.1.6 pci pins these pins interface with the pci bus. table 2-27. pci pins (page 1 of 2) signal description type pci_clk pci clock signal (see pci_speed field below) input pci (in)/ 3.3 v pci_ad(31:0) pci multiplexed address and data signals input/output pci (t/s) 3.3 v pci_cbe (3:0) pci command/byte enable signals input/output pci (t/s) 3.3 v pci_frame pci frame signal input/output pci (s/t/s) 3.3 v pci_irdy pci initiator (master) ready signal input/output pci (s/t/s) 3.3 v pci_trdy pci target (slave) ready signal input/output pci (s/t/s) 3.3 v pci_devsel pci device select signal input/output pci (s/t/s) 3.3 v pci_stop pci stop signal input/output pci (s/t/s) 3.3 v pci_request pci bus request signal output pci (t/s) 3.3 v pci_grant pci bus grant signal input pci (t/s) 3.3 v pci_idsel pci initialization device select signal input pci (in) 3.3 v pci_perr pci parity error signal input/output pci (s/t/s) 3.3 v pci_serr pci system error signal input/output pci (o/d) 3.3 v pci_inta pci level sensitive interrupt output pci (o/d) 3.3 v pci_par pci parity signal. covers all t he data/address and the four command/be signals. input/output pci (t/s) 3.3 v note: pci i/os are all configured for multi-point operation. ibm powernp np2g network processor preliminary physical description page 72 of 539 np2_ds_sec02_phys.fm.01 february 12, 2003 pci_speed pci speed. controls acceptable pci frequenc y asynchronous range by setting the plb/pci clock ratio. 0 plb:pci mode 2:1. acceptable pci frequency as ynchronous range is 34.5 mhz to 66.6 mhz 1 plb:pci mode 3:1. acceptable pci frequency as ynchronous range is 23.5 mhz to 44.5 mhz input 3.3 v-tolerant 2.5 v pci_bus_nm_int external non-maskable interrupt - the active pola rity of the interrupt is programmable by the powerpc. input pci 3.3 v pci_bus_m_int external maskable interrupt - the active pol arity of the interrupt is programmable by the powerpc. input pci 3.3 v figure 2-13. pci timing diagram table 2-27. pci pins (page 2 of 2) signal description type note: pci i/os are all configured for multi-point operation. 30 pf ts 50 ? v dd /2 t ck t ch t cl t val t on t off outputs pci_clk t dh t ds inputs notes: 1) v dd = 3.3 v 2) data invalid 3) output load 50 ohms and 30 pf ibm powernp np2g preliminary network processor np2_ds_sec02_phys.fm.01 february 12, 2003 physical description page 73 of 539 2.1.7 management bus interface pins the signals from these pins are translated into variou s ?host? buses by an external field-programmable gate array (fpga) serial/parallel manager (spm). table 2-28. pci timing diagram legend (for figure 2-13) symbol symbol description minimum (ns) maximum (ns) t ck pci cycle time 15 t ch clk clock width high 7.5 t cl clk clock width low 7.5 t val worst case output delay 2.0 4.8 t on pci bus turn on output delay 2 t off pci bus turn off output delay 14 t ds input setup time 2.4 t dh input hold time 0 note: all delays are measured with 1 ns slew time measured from 10-90% of input voltage. table 2-29. management bus pins signal description type mg_data serial data. supports a ddress/control/data protocol. input/output 3.3 v-tolerant 2.5 v mg_clk 33.33 mhz clock output 3.3 v-tolerant 2.5 v mg_nintr rising-edge sens itive interrupt input input 3.3 v-tolerant 2.5 v ibm powernp np2g network processor preliminary physical description page 74 of 539 np2_ds_sec02_phys.fm.01 february 12, 2003 figure 2-14. spm bus timing diagram table 2-30. spm bus timing diagram legend (for figure 2-14) symbol symbol description minimum (ns) maximum (ns) t ck spm cycle time 30 t ch clock pulse width high 14.4 15.6 t cl clock pulse width low 14.4 15.6 t dd data output delay 6.9 7.9 t ds data setup time 5.1 t dh data hold time 0 note: mg_nintr is an asynchronous input and is not timed. all delays are measured with 1 ns slew time measured from 10-90% of input voltage. 30 pf ts 50 ? v dd /2 t ck t ch t cl t dd (max) outputs mg_clk t dh t ds inputs t dd (min) mg_data mg_data notes: 1) v dd = 3.3 v 2) data invalid 3) output load 50 ohms and 30 pf ibm powernp np2g preliminary network processor np2_ds_sec02_phys.fm.01 february 12, 2003 physical description page 75 of 539 2.1.8 miscellaneous pins table 2-31. miscellaneous pins (page 1 of 2) signal description type iew_clock_a the positive pin of an input differential pai r. 50.6875 to 62.5 mhz. generates iew clock domains. required to hav e cycle-to-cycle jitter 150 ps. duty cycle tolerance must be 10%. an on-chip differential terminator of 100 ohms is present between this pin and its complement pin. iew lvds (see page 526) iew_clock_a the negative pin of an input diffe rential pair. 50.6875 to 62.5 mhz. input lvds (see page 526) iew_clock_b the positive pin of an input differential pai r. 50.6875 to 62.5 mhz. generates iew clock domains. required to hav e cycle-to-cycle jitter 150 ps. duty cycle tolerance must be 10%. an on-chip differential terminator of 100 ohms is present between this pin and its complement pin. iew lvds (see page 526) iew_clock_b the negative pin of an input diffe rential pair. 50.6875 to 62.5 mhz. input lvds (see page 526) core_clock 53.33 mhz oscillator - generates 266 /133 cloc k domains. required to have cycle-to-cycle jitter 150 ps. duty cycle tolerance must be 10%. input 5.0 v-tolerant 3.3 v lvttl clock125 125 mhz oscillator. required to have cycle-to-cycle jitter 60 ps. duty cycle tolerance must be 5%. this clock is required only w hen supporting tbi and gmii dmu bus modes. input 5.0 v-tolerant 3.3 v lvttl reset reset np2g - signal must be driv en active low for a minimum of 1 s to ensure a proper reset of the np2g. all input clocks (iew_clock_a, iew_clock_a , iew_clock_b, iew_clock_b , core_clock, clock125 if in use, and pci_clk) must be running prior to the activation of this signal. input 5.0 v-tolerant 3.3 v lvttl operational np2g operational - pin is driven active lo w when both the np2g ingress and egress macros have completed their initialization. it remains active until a subsequent reset is issued. output (o/d) 5.0 v-tolerant 3.3 v lvttl testmode(1:0) 00 functional mode, including c oncurrent use of the jtag interface for riscwatch or cabwatch operations. 01 debug mode - debug mode must be indicated by the testmode i/o for debug bus (dmu_d) output to be gated from the probe. 10 jtag test mode 11 lssd test mode input cmos 1.8 v jtag_trst jtag test reset. for normal functional operation, this pin must be connected to the same card source that is connected to the reset input. when the jtag interface is used for jtag test functions, this pin is controlled by the jtag interface logic on the card. input 5.0 v-tolerant 3.3 v lvttl jtag_tms jtag test mode select. for normal functional o peration, this pin should be tied either low or high. input 5.0 v-tolerant 3.3 v lvttl jtag_tdo jtag test data out. for normal functional operat ion, this pin should be tied either low or high. output 5.0 v-tolerant 3.3 v lvttl jtag_tdi jtag test data in. for normal functional oper ation, this pin should be tied either low or high. input 5.0 v-tolerant 3.3 v lvttl jtag_tck jtag test clock. for normal functional oper ation, this pin should be tied either low or high. input 5.0 v-tolerant 3.3 v lvttl ibm powernp np2g network processor preliminary physical description page 76 of 539 np2_ds_sec02_phys.fm.01 february 12, 2003 the termination network details for the signals are th e same as those for the np4gs3. see the guidelines contained in the ibm powernp np4gs3 pc card layout guidelines . plla_v dd pllb_v dd pllc_v dd these pins serve as the +1.8 volt supply fo r a critical noise-sensit ive portion of the phase- locked loop (pll) circuits. o ne pin serves as the analog v dd for each pll circuit. to prevent noise on these pins from introducing phase jitter in the pll outputs, place filters at the board level to isolate these pins from the noisy digital v dd pins. place separat e filters on each ana- log v dd pin to prevent noise from one pll being introduced into another. see section 2.1.9 pll filter circuit on page 80 for filter circuit details. input pll_v dd 1.8 v plla_gnd pllb_gnd pllc_gnd these pins serve as the ground connection for t he critical noise porti on of the phase lock loop (pll). one pin serves as the analog g nd for each pll circuit. each should be con- nected to the digital ground plane at the v dda node of the pll filter capacitor shown in fig- ure 2-16: pll filter circuit diagram on page 80. input pll_gnd 0.0 v thermal_in input pad of the thermal monitor (resistor). see 2.1.10 thermal i/o usage on page 80 for details on thermal monitor usage thermal thermal_out output pad of the thermal monitor (resistor) thermal vref1(2), vref2(8,7,6) voltage reference for sstl2 i/os for d2 and d3 (approximately four pins per side of the device that contains sstl2 i/o) input vref 1.25 v vref1(1), vref2(5,4,3) voltage reference for sstl2 i/os for d4 and d6 (approximately four pins per side of the device that contains sstl2 i/o) input vref 1.25 v vref1(0), vref2(2,1,0) voltage reference for sstl2 i/os for ds0 and ds 1 (approximately four pins per side of the device that contains sstl2 i/o) input vref 1.25 v boot_picocode determines location of network processor picocode load location. 0 load from spm 1 load from external source (typically power pc or pci bus) input 3.3 v-tolerant 2.5 v boot_ppc determines location of power pc code start location. 0 start from d6 1 start from pci input 3.3 v-tolerant 2.5 v spare_tst_rcvr(9:0) unused signals needed for manufacturing test. spare_tst_rcvr (9:5,1) should be tied to 0 on the card. spare_tst_rcvr (4:2,0) should be tied to 1 on the card. input cmos 1.8 v c405_debug_halt this signal, when asserted low, forces the embedded powerpc 405 processor to stop pro- cessing all instructions. for normal functional oper ation, this signal shou ld be tied inactive high. input 5.0 v-tolerant 3.3 v lvttl pio(2:0) programmable i/o input/output cmos 2.5 v pgm_gnd pgm_vdd these io are used for chip manufacturing and test purposes and should be left unconnected on the card. - table 2-31. miscellaneous pins (page 2 of 2) signal description type ibm powernp np2g preliminary network processor np2_ds_sec02_phys.fm.01 february 12, 2003 physical description page 77 of 539 table 2-32. signals requirin g pull-up or pull-down signal name function value signals requiring a dc connection that is the same value for all applications testmode(1:0) pull-down jtag_tdi pull-up jtag_tms pull-up jtag_tck pull-up c405_debug_halt pull-up spare_tst_rcvr (9:5, 1) pull-down spare_tst_rcvr (4:2, 0) pull-up reserved_io (17:18) pull down to gnd reserved_io (19:21, 22, 23:26, 28:49, 54, 55, 56) pull down to gnd 1 reserved_io (50:53) pull-up to 3.3 v 1 res_data pull-down and do not connect with other signals res_sync pull-down and do not connect with other signals signals requiring a dc connection that varies across different applications pci_speed choose up or down based on system pci bus speed mg_nintr pull-down if no syst em device drives this signal mg_data pull-down when external spm module is attached boot_picocode choose up or down based on picocode load location boot_ppc choose up or down based on ppc code load location lu_r_wrt , sch_r_wrt pull up when system diagnostics uses zbt sram to hold information through a software controlled reset (see software controlled reset register (soft_reset) on page 455). signals that have an ac connection, but also require pull-up or pull-down operational pull-up dmu_a(0), dmu_c(0), dmu_d(0) cpdetect if control point then pull-down, otherwise pull-up dmu_a(30:29), dmu_c( 30:29), dmu_d(30:29) dmu in 8-bit pos mode. rxaddr (1:0) pull-down dmu_a(4), dmu_c(4), dmu_d(4) dmu in any pos mode. rxval pull-down d3_dqs(1:0), d2_dqs(1:0) pull-down d0_dqs(3:0), d4_dqs(3:0), d6_dqs(3:0) pull-down ds0_dqs(3:0), ds1_dqs(3:0) pull-down 1. up to eight i/os that are pulled to the same voltage can be c onnected to a single resistor if its value is close to 300 ohms. if individ- ual resistors are used, they may be up to 1000 ohms. note: in addition to the signals in this table, any interface signals not used for a particu lar application should be pulled to their inactive state for control signals or either state for data signals. this prevents extraneous switching of the circuitry, which can caus e current surges and affect other signals. ibm powernp np2g network processor preliminary physical description page 78 of 539 np2_ds_sec02_phys.fm.01 february 12, 2003 table 2-33. pins requiring connections to other pins first grid location second grid location third grid location notes ak01 y01 1 aj02 w02 1 af01 w03 1 ae02 aa01 1 ah01 ab01 1 ah03 aa02 1 ae01 ac06 1 ae03 ac05 1 ad03 ac07 1 ad01 ad05 1 ac02 ae04 1 ac03 ae05 1 ab03 af03 1 aa04 af05 1 aa03 ag04 1 y03 ag02 1 e02 r02 d01 p01 j02 n01 h01 r03 f03 n02 f01 m01 g02 p03 g04 n03 j03 l05 j01 l06 k01 k05 k03 l07 l03 j05 l02 j04 n04 h05 m03 h03 v19 u19 w20 ag27 ae25 t19 note : all pins in the same row shoul d be connected together on the board. 1. if wiring congestion occurs, the pins in these rows can be rewired as shown in table 2-34 and figure 2-15 . ibm powernp np2g preliminary network processor np2_ds_sec02_phys.fm.01 february 12, 2003 physical description page 79 of 539 the alternate wiring scheme illustrated in table 2-34 and figure 2-15 can be used if wiring congestion occurs. note: this scheme applies only to a subset of the pins requiring connections to other pins (see table 2-33 ). table 2-34. alternate wiring for pins requiring connections to other pins first grid location second grid location ak01 ac07 aj02 ag02 af01 af03 ae02 ad05 ah01 ag04 ah03 af05 ae01 ae04 ae03 ae05 ad03 ac06 ad01 aa01 ac02 ab01 ac03 ac05 ab03 w03 aa04 aa02 aa03 y01 y03 w02 figure 2-15. alternate wiring for pins requiring connection to other pins ak01 ajo2 ah01 ah03 ag02 ag04 af01 af03 af05 ae01 ae02 ae03 ae04 ae05 ad01 ad03 ad05 ac02 ac03 ac05 ac06 ac07 ab01 ab03 aa01 aa02 aa03 aa04 y01 y03 w02 w03 ibm powernp np2g network processor preliminary physical description page 80 of 539 np2_ds_sec02_phys.fm.01 february 12, 2003 2.1.9 pll filter circuit v dda is the voltage supply pin to the analog circuits in the pll. noise on v dda causes phase jitter at the output of the pll. v dda is brought to a package pin to isolate it from the noisy internal digital v dd signal. if little noise is expected at the board level, then v dda can be connected directly to the digital v dd plane. in most circumstances, however, it is prudent to place a filter circuit on the v dda as shown below. note: all wire lengths should be kept as short as poss ible to minimize coupling from other signals. the impedance of the ferrite bead should be much greater than that of the capacitor at frequencies where noise is expected. many applications have found that a resistor does a better job of reducing jitter than a ferrite bead does. the resistor should be kept to a value lower than 2 ? . experimentation is the best way to determine the optimal filter de sign for a specific application. note: one filter circuit may be used for plla and pllb, and a second filter circuit should be used for pllc. 2.1.10 thermal i/o usage the thermal monitor consists of a resistor connected between pins pada and padb. at 2 5 c this resistance is estimated at 1500 + 350 ohms. the published temperat ure coefficient of the resistance for this technology is 0.33% per c. to determine the actual temperature coefficient, see measurement calibration on page 81. note: there is an electrostatic discharge (esd) diode at pada and padb. figure 2-16. pll filter circuit diagram figure 2-17. thermal monitor gnd digital vdd (via at board) vdda (to pll) ferrite bead c = 0.1 f thermal pada padb ibm powernp np2g preliminary network processor np2_ds_sec02_phys.fm.01 february 12, 2003 physical description page 81 of 539 2.1.10.1 temperature calculation the chip temperature can be calculated from where: r measured = resistance measured between pada and padb at test temperature. r calibrated = resistance measured between pada and padb (v r /i dc) at known temperature. t calibrated = known temperature used to measure r calibrated. 2.1.10.2 measurement calibration to use this thermal monitor accurately, it must first be calibrated. to calibrate, measure the voltage drop at two different known temperatures at the package while the device is dissipating little (less than 100 mw) or no power. apply i dc and wait for a fixed time t m , where t m = approximately 1 ms. keep t m short to minimize heating effects on the thermal monitor resistance. then measure v r . next, turn off i dc and change the package temperature. reapply i dc , wait t m again and measure v r . the temperature coefficient is, , where: t = temperature change, c v r = voltage drop, v i dc = applied current, a t c (r measured - r calibrated ) t chip = 1 + t calibrated c tc ? vr idc ? t --------------------- - ? c ------ = padb pada v r measure voltage drop v supply = v dd maximum i dc = 200 a maximum thermal ibm powernp np2g network processor preliminary physical description page 82 of 539 np2_ds_sec02_phys.fm.01 february 12, 2003 2.2 clocking domains see np2g dmu bus clock connections on page 58 and np2g dmu bus clock connections (pos over- view) on page 59 for related clock information. figure 2-18. clock generation and distribution pll 4.54-5 ns iew clock domain 9.09 ns x8 /4 /4 x16 /8 iew clock generator oscillator iew_clk_a (55 mhz) iew_clk_b (55 mhz) pll 4.54-5 ns iew clock domain 9.09 ns x8 53.3 mhz 125 mhz 2 2 divide by 2 7.5 ns ibm np2g /4 /4 tx_clk rx_clk phy and pos devices 3.75 ns 8 ns core, ddr, zbt clock_core clock domain smii, tbi, and gmii x16 /8 pll x8 /4 /3 x15 /8 clock domain divide by 4 36.3 ns divide by 4 36.3 ns 10 ns clock125 - tbi, gmii dmu_*(03) - smii note: iew_clk_a and b frequencies are shown for illustration purposes. these clocks can range from 50.6875 to 62.5 mhz. ibm powernp np2g preliminary network processor np2_ds_sec02_phys.fm.01 february 12, 2003 physical description page 83 of 539 figure 2-19. pins diagram wv u t r p nml kj h gf e d c b a 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 ad ac ab aa y 20 21 22 23 24 25 corner ae af ag ah aj ak al am an signal = 815 test i/o ground = 137 v dd = 72 v dd2 (3.3 v) = 16 1 2 v dd3 (2.5 v) = 16 v dd4 (2.5 v) = 16 3 4 v dd5 (2.5 v) = 16 5 dc test i/o 1 4 1 4 1 4 1 4 1 4 1 1 3 4 1 4 1 4 5 4 1 4 1 1 5 4 1 1 1 4 3 1 5 1 1 4 4 1 1 3 1 4 1 5 4 3 1 3 1 1 5 1 1 5 1 3 1 3 5 1 5 1 1 1 3 1 1 1 1 2 1 2 1 2 1 2 1 2 1 2 5 1 1 2 1 2 1 1 1 2 1 2 3 1 1 2 5 2 1 1 3 1 5 2 1 1 2 3 1 5 2 5 1 2 1 3 1 1 1 1 5 1 5 1 3 3 1 1 1 1 5 1 3 1 3 1 26 27 28 29 30 31 32 33 note: for illustrative purposes only. viewed through top of package a01 ibm powernp np2g network processor preliminary physical description page 84 of 539 np2_ds_sec02_phys.fm.01 february 12, 2003 2.3 mechanical specifications figure 2-20. mechanical diagram notes: 1. refer to table 2-35 on page 85 for mechanical dimensions. 2. mechanical drawing is not to scale. see yo ur ibm representative for more information. 3. ibm square outline conforms to jedec mo-158. a a1 dla lidless dla chip aaa d e e1 d1 e ccc ccc b note: no i/o at a01 location yddd m yeee m z z xy a a1 aaa z y x terminal a01 identifier top view bottom view z ibm powernp np2g preliminary network processor np2_ds_sec02_phys.fm.01 february 12, 2003 physical description page 85 of 539 table 2-35. mechanical specifications mechanical dimensions value 1 a (dla) min 2 6.23 max 3 6.83 a (lidless) min 2 4.23 max 3 4.83 a1 nom 2.21 b min 0.48 max 0.52 e basic 1.27 aaa 0.15 ccc 0.20 ddd 0.30 eee 0.10 d 42.50 d1 40.64 e 42.50 e1 40.64 m 4 33 x 33 n 5 1088 5 weight (g) tbd 1. all dimensions are in mill imeters, except where noted. 2. minimum package thickness is calculated using the nominal thic kness of all parts. the nominal thickness of an 8-layer package was used for the package thickness. 3. maximum package thickness is calculated usi ng the nominal thickness of all parts. the nominal thickness of a 12-layer package was used for the package thickness. 4. m = the i/o matrix size. 5. n = the maximum number of i/os. the number of i/os shown in the table is the amount after depopulation. product with 1.27 mm pitch is depopulated by one i/o at the a01 corner of the array. ibm powernp np2g network processor preliminary physical description page 86 of 539 np2_ds_sec02_phys.fm.01 february 12, 2003 2.4 ieee 1149 (jtag) compliance 2.4.1 statement of jtag compliance the np2g is compliant wit h ieee standard 1149.1a. 2.4.2 jtag compliance mode compliance with ieee 1149.1a is enab led by applying a compliance-enable pattern to the compliance-enable inputs as shown in table 2-36 . 2.4.3 jtag implementation specifics all mandatory jtag public instructions are implemented in the np2g?s design. table 2-37 documents all implemented public instructions. table 2-36. jtag compliance-enable inputs compliance-enable inputs compliance-enable pattern testmode(1:0) ?10? spare_tst_rcvr(9) 1 spare_tst_rcvr(4) 1 spare_tst_rcvr(3) 1 spare_tst_rcvr(2) 1 note: to achieve reset of the jtag test logic, the jtag_trst input must be driven low wh en the compliance-enable pattern is applied. table 2-37. implemented jtag public instructions instruction name binary code 1 serial data reg connected to tdi/tdo i/o control source (driver data and driver enable) bypass 111 1111 bypass system, functional values clamp 111 1101 bypass jtag extest 111 1000 boundaryscan jtag highz 111 1010 bypass jtag, all drivers disabled sample/preload 111 1001 boundaryscan system, functional values 1. device tdo output driver is only enabled during tap controller states shift_ir and shift_dr. ibm powernp np2g preliminary network processor np2_ds_sec02_phys.fm.01 february 12, 2003 physical description page 87 of 539 2.4.4 brief overview of jtag instructions instruction description bypass connects the bypass data register between the tdi and tdo pins. the bypass data register is a single shift-register stage that provides a minimum-length serial path between the tdi and tdo pins when no test operation of the device is required. bypass does not disturb the norma l functional connection and control of the i/o pins. clamp causes all output pins to be driven from the co rresponding jtag parallel boundary scan register. the sample/preload instruction is ty pically used to load the desired values in to the parallel boundary scan register. since the clamp instruction causes the serial tdi/tdo path to be connected to the bypass data registers, scanning thr ough the device is very fast when the clamp instruction is loaded. extest allows the jtag logic to control output pin values by connecting each output data and enable signal to its corresponding parallel boundary scan register. the desired controlling values for the output data and enable signals are shifted into the scan boundary scan register during the shiftdr state. the paral- lel boundary scan register is loaded from the sc an boundary scan register during the updatedr state. the extest instruction also allows the jtag logic to sample input receiver and output enable values. the values are loaded into the scan boundary scan register during capturedr state. highz causes the jtag logic to tri-stat e all output drivers while connecting th e bypass register in the serial tdi/tdo path. sample/preload allows the jtag logic to sample input pin val ues and load the parallel boundar y scan register without disturbing the normal functional connection and control of the i/o pins. the sample phase of the instruction occurs in capturedr state, at which time the scan boundary scan register is loaded with the corresponding input receiver and output enable values. (n ote that for input pins that are connected to a common i/o, the scan boundary scan regist er only updates with a input receiver sample if the corre- sponding output driver of the common i/o is disabled; otherwise the sc an register is updated with the output data signal.) the desired controlling values for the output pins are shifted into the scan boundary scan register dur- ing the shiftdr state and loaded from the scan bounda ry scan register to the parallel boundary scan register during the updatedr state. ibm powernp np2g preliminary network processor np2_ds_sec02_phys_pinlist1.fm.01 february 12, 2003 physical description page 88 of 539 table 2-38. complete signal pin listing by signal name (continued) 2.5 signal pin lists table 2-38. complete signal pin listing by signal name signal name grid position boot_picocode k07 boot_ppc l04 c405_debug_halt ab23 cam_cp_response(00) u09 cam_cp_response(01) t11 cam_cp_response(02) p05 cam_cp_response(03) r06 cam_cp_response(04) t13 cam_cp_response(05) p07 cam_cp_response(06) t05 cam_cp_response(07) r01 cam_cp_response(08) r10 cam_cp_response(09) p09 cam_cp_response(10) r09 cam_cp_response(11) r14 cam_cp_response(12) r13 cam_cp_response(13) n07 clock125 b33 core_clock c33 d0_addr(00) al10 d0_addr(01) an10 d0_addr(02) aj09 d0_addr(03) an06 d0_addr(04) aa14 d0_addr(05) ab15 d0_addr(06) am07 d0_addr(07) al08 d0_addr(08) am11 d0_addr(09) al11 d0_addr(10) ac14 d0_addr(11) ag10 d0_addr(12) af11 d0_cs an09 d0_data(00) aa12 d0_data(01) ad09 d0_data(02) ag07 d0_data(03) ab11 d0_data(04) an02 d0_data(05) am03 d0_data(06) an01 d0_data(07) an03 d0_data(08) al04 d0_data(09) ag03 d0_data(10) ah07 d0_data(11) ae09 d0_data(12) al03 d0_data(13) ac11 d0_data(14) aj06 d0_data(15) ak05 d0_data(16) aj07 d0_data(17) an04 d0_data(18) an07 d0_data(19) al07 d0_data(20) af09 d0_data(21) ag08 d0_data(22) ae10 d0_data(23) ad11 d0_data(24) an08 d0_data(25) al09 d0_data(26) al06 d0_data(27) am05 d0_data(28) ab13 d0_data(29) ac15 d0_data(30) ak07 d0_data(31) aj08 d0_dqs(0) ag09 d0_dqs(1) ac12 d0_dqs(2) ae11 signal name grid position d0_dqs(3) ah09 d0_we am09 d2_addr(00) aj22 d2_addr(01) ah21 d2_addr(02) an21 d2_addr(03) am21 d2_addr(04) ah23 d2_addr(05) ac20 d2_addr(06) ad21 d2_addr(07) ag23 d2_addr(08) an22 d2_addr(09) al21 d2_addr(10) ak23 d2_addr(11) aj23 d2_addr(12) aa19 d2_cs al22 d2_data(00) an18 d2_data(01) aj19 d2_data(02) w18 d2_data(03) aa18 d2_data(04) aj20 d2_data(05) al20 d2_data(06) an19 d2_data(07) ae20 d2_data(08) ae17 d2_data(09) ae21 d2_data(10) ag22 d2_data(11) an20 d2_data(12) am19 d2_data(13) ak21 d2_data(14) aj21 d2_data(15) y19 d2_dqs(0) ab19 d2_dqs(1) ak25 signal name grid position ibm powernp np2g preliminary network processor np2_ds_sec02_phys_pinlist1.fm.01 february 12, 2003 physical description page 89 of 539 table 2-38. complete signal pin listing by signal name (continued) d2_we aj24 d3_addr(00) ag19 d3_addr(01) aj16 d3_addr(02) af17 d3_addr(03) aj17 d3_addr(04) ag18 d3_addr(05) ae18 d3_addr(06) aa17 d3_addr(07) ac18 d3_addr(08) ak19 d3_addr(09) al19 d3_addr(10) an17 d3_addr(11) ak17 d3_addr(12) ae19 d3_cs al18 d3_data(00) ag13 d3_data(01) aa16 d3_data(02) ag14 d3_data(03) ae15 d3_data(04) al17 d3_data(05) am17 d3_data(06) al15 d3_data(07) ak15 d3_data(08) w17 d3_data(09) ae16 d3_data(10) ag16 d3_data(11) ah17 d3_data(12) ag17 d3_data(13) ag15 d3_data(14) af15 d3_data(15) af19 d3_dqs(0) ag20 d3_dqs(1) ac17 d3_we ad19 d4_addr(00) c12 signal name grid position d4_addr(01) a11 d4_addr(02) j12 d4_addr(03) h11 d4_addr(04) g10 d4_addr(05) l13 d4_addr(06) c11 d4_addr(07) b11 d4_addr(08) d09 d4_addr(09) c08 d4_addr(10) m13 d4_addr(11) n14 d4_addr(12) b07 d4_cs e10 d4_data(00) m17 d4_data(01) l16 d4_data(02) d15 d4_data(03) c15 d4_data(04) a17 d4_data(05) d17 d4_data(06) h09 d4_data(07) g14 d4_data(08) g13 d4_data(09) k15 d4_data(10) c16 d4_data(11) a16 d4_data(12) e15 d4_data(13) f15 d4_data(14) r17 d4_data(15) n16 d4_data(16) e14 d4_data(17) c14 d4_data(18) e09 d4_data(19) a15 d4_data(20) l15 d4_data(21) j14 signal name grid position d4_data(22) g12 d4_data(23) h13 d4_data(24) a14 d4_data(25) b15 d4_data(26) d13 d4_data(27) e13 d4_data(28) p15 d4_data(29) e12 d4_data(30) f13 d4_data(31) a13 d4_dqs(0) d11 d4_dqs(1) e11 d4_dqs(2) n15 d4_dqs(3) m15 d4_we f11 d6_addr(00) al28 d6_addr(01) an26 d6_addr(02) ae24 d6_addr(03) ag26 d6_addr(04) af25 d6_addr(05) al27 d6_addr(06) an30 d6_addr(07) aj27 d6_addr(08) ak29 d6_addr(09) aj28 d6_addr(10) al29 d6_addr(11) ag21 d6_addr(12) ah27 d6_byteen(0) ag24 d6_byteen(1) af23 d6_cs al31 d6_data(00) al23 d6_data(01) am23 d6_data(02) al26 d6_data(03) am27 signal name grid position ibm powernp np2g network processor preliminary physical description page 90 of 539 np2_ds_sec02_phys_pinlist1.fm.01 february 12, 2003 table 2-38. complete signal pin listing by signal name (continued) d6_data(04) ab21 d6_data(05) an28 d6_data(06) an24 d6_data(07) al24 d6_data(08) ah25 d6_data(09) ae23 d6_data(10) ac21 d6_data(11) an25 d6_data(12) aj26 d6_data(13) ak27 d6_data(14) ae22 d6_data(15) ac22 d6_dqs(0) al30 d6_dqs(1) an31 d6_dqs(2) an33 d6_dqs(3) am31 d6_dqs_par(00) an32 d6_dqs_par(01) af21 d6_parity(00) am29 d6_parity(01) an23 d6_we aj25 da_ba(0) an29 da_ba(1) aa20 da_cas an27 da_clk al25 da_clk am25 da_ras ag25 db_ba(0) ag11 db_ba(1) ad13 db_cas aj12 db_clk ah19 db_clk aj18 db_ras ae13 dc_ba(0) d25 dc_ba(1) j17 signal name grid position dc_cas n19 dc_clk d23 dc_clk e23 dc_ras c21 dd_ba(0) a12 dd_ba(1) j13 dd_cas g11 dd_clk b13 dd_clk c13 dd_ras k13 de_ba(0) am01 de_ba(1) ah05 de_cas al02 de_clk aj04 de_clk aj05 de_ras ak03 dmu_a(00) v31 dmu_a(01) v29 dmu_a(02) v27 dmu_a(03) w33 dmu_a(04) w32 dmu_a(05) w31 dmu_a(06) w30 dmu_a(07) w29 dmu_a(08) w28 dmu_a(09) w27 dmu_a(10) w26 dmu_a(11) w25 dmu_a(12) w24 dmu_a(13) w23 dmu_a(14) y33 dmu_a(15) y31 dmu_a(16) y29 dmu_a(17) y27 dmu_a(18) y25 signal name grid position dmu_a(19) y23 dmu_a(20) aa33 dmu_a(21) aa32 dmu_a(22) aa31 dmu_a(23) aa30 dmu_a(24) aa29 dmu_a(25) aa28 dmu_a(26) aa27 dmu_a(27) aa26 dmu_a(28) aa25 dmu_a(29) ab33 dmu_a(30) ab31 dmu_c(00) l33 dmu_c(01) l32 dmu_c(02) l31 dmu_c(03) l30 dmu_c(04) l29 dmu_c(05) l28 dmu_c(06) l27 dmu_c(07) l26 dmu_c(08) l25 dmu_c(09) l24 dmu_c(10) l23 dmu_c(11) m33 dmu_c(12) m31 dmu_c(13) m29 dmu_c(14) m27 dmu_c(15) m25 dmu_c(16) m23 dmu_c(17) n33 dmu_c(18) n32 dmu_c(19) n31 dmu_c(20) n30 dmu_c(21) n29 dmu_c(22) n28 signal name grid position ibm powernp np2g preliminary network processor np2_ds_sec02_phys_pinlist1.fm.01 february 12, 2003 physical description page 91 of 539 table 2-38. complete signal pin listing by signal name (continued) dmu_c(23) n27 dmu_c(24) n26 dmu_c(25) n25 dmu_c(26) n24 dmu_c(27) n23 dmu_c(28) p33 dmu_c(29) p31 dmu_c(30) p29 dmu_d(00) d33 dmu_d(01) d31 dmu_d(02) g28 dmu_d(03) j29 dmu_d(04) e30 dmu_d(05) f33 dmu_d(06) f31 dmu_d(07) f29 dmu_d(08) g32 dmu_d(09) k25 dmu_d(10) g30 dmu_d(11) g29 dmu_d(12) e32 dmu_d(13) h33 dmu_d(14) h31 dmu_d(15) h29 dmu_d(16) h27 dmu_d(17) j33 dmu_d(18) j32 dmu_d(19) j31 dmu_d(20) j30 dmu_d(21) k27 dmu_d(22) j28 dmu_d(23) j27 dmu_d(24) j26 dmu_d(25) j25 dmu_d(26) k33 signal name grid position dmu_d(27) k31 dmu_d(28) k29 dmu_d(29) e31 dmu_d(30) g31 ds0_addr(00) a28 ds0_addr(01) n20 ds0_addr(02) m19 ds0_addr(03) b27 ds0_addr(04) c26 ds0_addr(05) b23 ds0_addr(06) c23 ds0_addr(07) g24 ds0_addr(08) h23 ds0_addr(09) j22 ds0_addr(10) a23 ds0_addr(11) c22 ds0_addr(12) e24 ds0_cs a31 ds0_data(00) p19 ds0_data(01) a32 ds0_data(02) b31 ds0_data(03) a33 ds0_data(04) c30 ds0_data(05) c31 ds0_data(06) f27 ds0_data(07) h21 ds0_data(08) c29 ds0_data(09) a29 ds0_data(10) e28 ds0_data(11) d29 ds0_data(12) e27 ds0_data(13) a30 ds0_data(14) a27 ds0_data(15) c27 ds0_data(16) h25 signal name grid position ds0_data(17) g26 ds0_data(18) j24 ds0_data(19) k23 ds0_data(20) a26 ds0_data(21) c25 ds0_data(22) c28 ds0_data(23) b29 ds0_data(24) m21 ds0_data(25) l19 ds0_data(26) d27 ds0_data(27) e26 ds0_data(28) a25 ds0_data(29) b25 ds0_data(30) g25 ds0_data(31) l22 ds0_dqs(0) f25 ds0_dqs(1) c24 ds0_dqs(2) a24 ds0_dqs(3) e25 ds0_we j23 ds1_addr(00) n17 ds1_addr(01) j18 ds1_addr(02) g18 ds1_addr(03) e17 ds1_addr(04) h17 ds1_addr(05) g19 ds1_addr(06) h19 ds1_addr(07) h15 ds1_addr(08) g15 ds1_addr(09) g17 ds1_addr(10) f17 ds1_addr(11) g16 ds1_addr(12) j16 ds1_cs e16 ds1_data(00) a22 signal name grid position ibm powernp np2g network processor preliminary physical description page 92 of 539 np2_ds_sec02_phys_pinlist1.fm.01 february 12, 2003 table 2-38. complete signal pin listing by signal name (continued) ds1_data(01) g23 ds1_data(02) k21 ds1_data(03) l20 ds1_data(04) f23 ds1_data(05) b21 ds1_data(06) a21 ds1_data(07) f21 ds1_data(08) e22 ds1_data(09) l18 ds1_data(10) l17 ds1_data(11) e21 ds1_data(12) d21 ds1_data(13) b19 ds1_data(14) a20 ds1_data(15) g22 ds1_data(16) j21 ds1_data(17) j15 ds1_data(18) j20 ds1_data(19) a19 ds1_data(20) e18 ds1_data(21) c20 ds1_data(22) e20 ds1_data(23) n18 ds1_data(24) f19 ds1_data(25) e19 ds1_data(26) a18 ds1_data(27) c18 ds1_data(28) k19 ds1_data(29) g21 ds1_data(30) g20 ds1_data(31) j19 ds1_dqs(0) b17 ds1_dqs(1) c19 ds1_dqs(2) d19 ds1_dqs(3) r18 signal name grid position ds1_we c17 dum a01 gnd ab04 gnd ab08 gnd ab12 gnd ab16 gnd ab18 gnd ab22 gnd ab26 gnd ab30 gnd ad02 gnd ad06 gnd ad10 gnd ad14 gnd ad20 gnd ad24 gnd ad28 gnd ad32 gnd af04 gnd af08 gnd af12 gnd af16 gnd af18 gnd af22 gnd af26 gnd af30 gnd ah02 gnd ah06 gnd ah10 gnd ah14 gnd ah20 gnd ah24 gnd ah28 gnd ah32 gnd ak04 signal name grid position gnd ak08 gnd ak12 gnd ak16 gnd ak18 gnd ak22 gnd ak26 gnd ak30 gnd am02 gnd am06 gnd am10 gnd am14 gnd am20 gnd am24 gnd am28 gnd am32 gnd b02 gnd b06 gnd b10 gnd b14 gnd b20 gnd b24 gnd b28 gnd b32 gnd d04 gnd d08 gnd d12 gnd d16 gnd d18 gnd d22 gnd d26 gnd d30 gnd f02 gnd f06 gnd f10 gnd f14 signal name grid position ibm powernp np2g preliminary network processor np2_ds_sec02_phys_pinlist1.fm.01 february 12, 2003 physical description page 93 of 539 table 2-38. complete signal pin listing by signal name (continued) gnd f20 gnd f24 gnd f28 gnd f32 gnd h04 gnd h08 gnd h12 gnd h16 gnd h18 gnd h22 gnd h26 gnd h30 gnd k02 gnd k06 gnd k10 gnd k14 gnd k20 gnd k24 gnd k28 gnd k32 gnd m04 gnd m08 gnd m12 gnd m16 gnd m18 gnd m22 gnd m26 gnd m30 gnd p02 gnd p06 gnd p10 gnd p14 gnd p17 gnd p20 gnd p24 signal name grid position gnd p28 gnd p32 gnd r15 gnd r19 gnd t04 gnd t08 gnd t12 gnd t16 gnd t18 gnd t22 gnd t26 gnd t30 gnd u14 gnd u17 gnd u20 gnd v04 gnd v08 gnd v12 gnd v16 gnd v18 gnd v22 gnd v26 gnd v30 gnd w15 gnd w19 gnd y02 gnd y06 gnd y10 gnd y14 gnd y17 gnd y20 gnd y24 gnd y28 gnd y32 i_freeq_th v21 signal name grid position iew_clk_a al05 iew_clk_a an05 iew_clk_b a05 iew_clk_b c05 jtag_tck aa22 jtag_tdi w22 jtag_tdo aa23 jtag_tms u22 jtag_trst t25 lu_addr(00) aa09 lu_addr(01) y11 lu_addr(02) aa10 lu_addr(03) ab07 lu_addr(04) ac09 lu_addr(05) ae06 lu_addr(06) ae07 lu_addr(07) ac01 lu_addr(08) r04 lu_addr(09) ag05 lu_addr(10) ag06 lu_addr(11) ac04 lu_addr(12) ad07 lu_addr(13) af07 lu_addr(14) ab05 lu_addr(15) ae08 lu_addr(16) ab09 lu_addr(17) aa05 lu_addr(18) aa11 lu_addr(19) u07 lu_clk aj03 lu_data(00) u15 lu_data(01) u13 lu_data(02) t09 lu_data(03) t07 lu_data(04) r07 signal name grid position ibm powernp np2g network processor preliminary physical description page 94 of 539 np2_ds_sec02_phys_pinlist1.fm.01 february 12, 2003 table 2-38. complete signal pin listing by signal name (continued) lu_data(05) r08 lu_data(06) w06 lu_data(07) w05 lu_data(08) u08 lu_data(09) v07 lu_data(10) v09 lu_data(11) u12 lu_data(12) v15 lu_data(13) w04 lu_data(14) v11 lu_data(15) w07 lu_data(16) w08 lu_data(17) y07 lu_data(18) v13 lu_data(19) w13 lu_data(20) w01 lu_data(21) w09 lu_data(22) y09 lu_data(23) aa06 lu_data(24) t15 lu_data(25) w10 lu_data(26) w12 lu_data(27) w14 lu_data(28) aa07 lu_data(29) aa08 lu_data(30) u01 lu_data(31) w11 lu_data(32) y05 lu_data(33) r05 lu_data(34) u10 lu_data(35) u03 lu_r_wrt ac08 mg_clk j07 mg_data j06 mg_nintr j08 signal name grid position mgrant_a(0) v19 mgrant_a(1) u19 mgrant_b(0) ag27 mgrant_b(1) ae25 operational c32 pci_ad(00) ab29 pci_ad(01) ab27 pci_ad(02) ab25 pci_ad(03) ac33 pci_ad(04) ac32 pci_ad(05) ac31 pci_ad(06) ac30 pci_ad(07) ac29 pci_ad(08) ac27 pci_ad(09) ac26 pci_ad(10) ac25 pci_ad(11) ac24 pci_ad(12) ad33 pci_ad(13) ad31 pci_ad(14) ad29 pci_ad(15) ad27 pci_ad(16) af29 pci_ad(17) af27 pci_ad(18) ag33 pci_ad(19) ag32 pci_ad(20) ag31 pci_ad(21) ag30 pci_ad(22) ag29 pci_ad(23) ag28 pci_ad(24) ah29 pci_ad(25) aj33 pci_ad(26) aj32 pci_ad(27) aj31 pci_ad(28) aj30 pci_ad(29) aj29 signal name grid position pci_ad(30) ak33 pci_ad(31) ak31 pci_bus_m_int ac23 pci_bus_nm_int g27 pci_cbe(0) ac28 pci_cbe(1) ad25 pci_cbe(2) af31 pci_cbe(3) ah31 pci_clk af33 pci_devsel ae29 pci_frame ae26 pci_grant al32 pci_idsel ah33 pci_inta am33 pci_irdy ae27 pci_par ae33 pci_perr ae31 pci_request al33 pci_serr ae32 pci_speed m07 pci_stop ae30 pci_trdy ae28 pgm_gnd j09 pgm_vdd l11 pio(0) n09 pio(1) n08 pio(2) n06 plla_gnd ag01 plla_vdd aj01 pllb_gnd g01 pllb_v dd e01 pllc_gnd g33 pllc_v dd e33 res_data t21 res_sync u21 signal name grid position ibm powernp np2g preliminary network processor np2_ds_sec02_phys_pinlist1.fm.01 february 12, 2003 physical description page 95 of 539 table 2-38. complete signal pin listing by signal name (continued) reserved_io(17) aj14 reserved_io(18) an16 reserved_io(19) p27 reserved_io(20) p25 reserved_io(21) p23 reserved_io(22) r33 reserved_io(23) r32 reserved_io(24) r31 reserved_io(25) r30 reserved_io(26) r29 reserved_io(28) r27 reserved_io(29) r26 reserved_io(30) r25 reserved_io(31) r24 reserved_io(32) r23 reserved_io(33) t33 reserved_io(34) t31 reserved_io(35) t29 reserved_io(36) t27 reserved_io(37) r22 reserved_io(38) t23 reserved_io(39) v25 reserved_io(40) u32 reserved_io(41) u31 reserved_io(42) u30 reserved_io(43) u29 reserved_io(44) u28 reserved_io(45) u27 reserved_io(46) u26 reserved_io(47) u25 reserved_io(48) u24 reserved_io(49) v33 reserved_io(50) y21 reserved_io(51) w21 reserved_io(52) r20 signal name grid position reserved_io(53) p21 reserved_io(54) r21 reserved_io(55) u23 reserved_io(56) v23 reserved_io(57) aa24 reserved_io(58) n22 reset e29 sch_addr(00) a07 sch_addr(01) b05 sch_addr(02) a04 sch_addr(03) e06 sch_addr(04) e07 sch_addr(05) e04 sch_addr(06) h07 sch_addr(07) f05 sch_addr(08) f07 sch_addr(09) c03 sch_addr(10) d05 sch_addr(11) a02 sch_addr(12) c04 sch_addr(13) b03 sch_addr(14) c02 sch_addr(15) d03 sch_addr(16) b01 sch_addr(17) c01 sch_addr(18) e05 sch_clk c07 sch_data(00) a10 sch_data(01) c10 sch_data(02) f09 sch_data(03) j11 sch_data(04) l12 sch_data(05) g09 sch_data(06) b09 sch_data(07) a09 signal name grid position sch_data(08) a06 sch_data(09) e08 sch_data(10) g06 sch_data(11) g07 sch_data(12) c06 sch_data(13) d07 sch_data(14) c09 sch_data(15) a08 sch_data(16) j10 sch_data(17) g08 sch_r_wrt g05 send_grant_a w20 send_grant_b t19 spare_tst_rcvr(0) u05 spare_tst_rcvr(1) e03 spare_tst_rcvr(2) a03 spare_tst_rcvr(3) t01 spare_tst_rcvr(4) al01 spare_tst_rcvr(5) g03 spare_tst_rcvr(6) v01 spare_tst_rcvr(7) v03 spare_tst_rcvr(8) t03 spare_tst_rcvr(9) u33 testmode(0) v05 testmode(1) u06 thermal_in u04 thermal_out u02 unused aa15 unused ab17 unused ac16 unused ad15 unused ae12 unused ae14 unused af13 unused ag12 signal name grid position ibm powernp np2g network processor preliminary physical description page 96 of 539 np2_ds_sec02_phys_pinlist1.fm.01 february 12, 2003 table 2-38. complete signal pin listing by signal name (continued) unused ah11 unused ah13 unused ah15 unused aj10 unused aj11 unused aj13 unused aj15 unused ak09 unused ak11 unused ak13 unused al12 unused al13 unused al14 unused al16 unused am13 unused am15 unused an11 unused an12 unused an13 unused an14 unused an15 unused k09 unused l01 unused l08 unused l09 unused m05 unused m09 unused m11 unused n05 unused n10 unused n12 unused p11 unused p13 unused r11 unused r12 signal name grid position unused r16 unused r28 unused u07 unused u11 unused w16 unused y15 v dd aa13 v dd aa21 v dd ab02 v dd ab10 v dd ab28 v dd ad04 v dd ad16 v dd ad22 v dd ad26 v dd af06 v dd af10 v dd af20 v dd af32 v dd ah12 v dd ah18 v dd ah26 v dd ah30 v dd ak02 v dd ak06 v dd ak14 v dd ak24 v dd am08 v dd am16 v dd am22 v dd am30 v dd b04 v dd b12 v dd b18 v dd b26 signal name grid position v dd d10 v dd d20 v dd d28 v dd d32 v dd f04 v dd f08 v dd f16 v dd f22 v dd h02 v dd h14 v dd h24 v dd h28 v dd k08 v dd k12 v dd k18 v dd k30 v dd m06 v dd m24 v dd m32 v dd n13 v dd n21 v dd p04 v dd p16 v dd p18 v dd p26 v dd t02 v dd t10 v dd t14 v dd t17 v dd t20 v dd t28 v dd u16 v dd u18 v dd v06 v dd v14 signal name grid position ibm powernp np2g preliminary network processor np2_ds_sec02_phys_pinlist1.fm.01 february 12, 2003 physical description page 97 of 539 table 2-38. complete signal pin listing by signal name (continued) v dd v17 v dd v20 v dd v24 v dd v32 v dd y08 v dd y16 v dd y18 v dd y30 vref1(0) ad23 vref1(1) k11 vref1(2) ac10 vref2(0) ac19 vref2(1) ad17 vref2(2) ac13 vref2(3) l14 vref2(4) k17 vref2(5) l21 vref2(6) y13 vref2(7) n11 vref2(8) l10 2.5 v ab06 2.5 v ab14 2.5 v ab20 2.5 v ad08 2.5 v ad12 2.5 v ad18 2.5 v af02 2.5 v af14 signal name grid position 2.5 v af24 2.5 v ah04 2.5 v ah08 2.5 v ah16 2.5 v ah22 2.5 v ak10 2.5 v ak20 2.5 v ak28 2.5 v am04 2.5 v am12 2.5 v am18 2.5 v am26 2.5 v b08 2.5 v b16 2.5 v b22 2.5 v b30 2.5 v d02 2.5 v d06 2.5 v d14 2.5 v d24 2.5 v f12 2.5 v f18 2.5 v f26 2.5 v h06 2.5 v h10 2.5 v h20 2.5 v k04 2.5 v k16 signal name grid position 2.5 v k22 2.5 v m02 2.5 v m10 2.5 v m14 2.5 v m20 2.5 v p08 2.5 v p12 2.5 v t06 2.5 v v02 2.5 v v10 2.5 v y04 2.5 v y12 3.3 v ab24 3.3 v ab32 3.3 v ad30 3.3 v af28 3.3 v ak32 3.3 v f30 3.3 v h32 3.3 v k26 3.3 v m28 3.3 v p22 3.3 v p30 3.3 v t24 3.3 v t32 3.3 v v28 3.3 v y22 3.3 v y26 signal name grid position note: all unused pins should be left unused on the card. ibm powernp np2g network processor preliminary physical description page 98 of 539 np2_ds_sec02_phys_pinlist2.fm.01 february 12, 2003 table 2-39. complete signal pin listing by grid position (continued) table 2-39. complete signal pin listing by grid position grid position signal name aa05 lu_addr(17) aa06 lu_data(23) aa07 lu_data(28) aa08 lu_data(29) aa09 lu_addr(00) aa10 lu_addr(02) aa11 lu_addr(18) aa12 d0_data(00) aa13 v dd aa14 d0_addr(04) aa15 unused aa16 d3_data(01) aa17 d3_addr(06) aa18 d2_data(03) aa19 d2_addr(12) aa20 da_ba(1) aa21 v dd aa22 jtag_tck aa23 jtag_tdo aa24 reserved_io(57) aa25 dmu_a(28) aa26 dmu_a(27) aa27 dmu_a(26) aa28 dmu_a(25) aa29 dmu_a(24) aa30 dmu_a(23) aa31 dmu_a(22) aa32 dmu_a(21) aa33 dmu_a(20) ab02 v dd ab04 gnd ab05 lu_addr(14) ab06 2.5 v ab07 lu_addr(03) ab08 gnd ab09 lu_addr(16) ab10 v dd ab11 d0_data(03) ab12 gnd ab13 d0_data(28) ab14 2.5 v ab15 d0_addr(05) ab16 gnd ab17 unused ab18 gnd ab19 d2_dqs(0) ab20 2.5 v ab21 d6_data(04) ab22 gnd ab23 c405_debug_halt ab24 3.3 v ab25 pci_ad(02) ab26 gnd ab27 pci_ad(01) ab28 v dd ab29 pci_ad(00) ab30 gnd ab31 dmu_a(30) ab32 3.3 v ab33 dmu_a(29) ac01 lu_addr(07) ac04 lu_addr(11) ac08 lu_r_wrt ac09 lu_addr(04) ac10 vref1(2) ac11 d0_data(13) ac12 d0_dqs(1) ac13 vref2(2) ac14 d0_addr(10) ac15 d0_data(29) grid position signal name ac16 unused ac17 d3_dqs(1) ac18 d3_addr(07) ac19 vref2(0) ac20 d2_addr(05) ac21 d6_data(10) ac22 d6_data(15) ac23 pci_bus_m_int ac24 pci_ad(11) ac25 pci_ad(10) ac26 pci_ad(09) ac27 pci_ad(08) ac28 pci_cbe(0) ac29 pci_ad(07) ac30 pci_ad(06) ac31 pci_ad(05) ac32 pci_ad(04) ac33 pci_ad(03) ad02 gnd ad04 v dd ad06 gnd ad07 lu_addr(12) ad08 2.5 v ad09 d0_data(01) ad10 gnd ad11 d0_data(23) ad12 2.5 v ad13 db_ba(1) ad14 gnd ad15 unused ad16 v dd ad17 vref2(1) ad18 2.5 v ad19 d3_we ad20 gnd grid position signal name ibm powernp np2g preliminary network processor np2_ds_sec02_phys_pinlist2.fm.01 february 12, 2003 physical description page 99 of 539 table 2-39. complete signal pin listing by grid position (continued) ad21 d2_addr(06) ad22 v dd ad23 vref1(0) ad24 gnd ad25 pci_cbe(1) ad26 v dd ad27 pci_ad(15) ad28 gnd ad29 pci_ad(14) ad30 3.3 v ad31 pci_ad(13) ad32 gnd ad33 pci_ad(12) ae06 lu_addr(05) ae07 lu_addr(06) ae08 lu_addr(15) ae09 d0_data(11) ae10 d0_data(22) ae11 d0_dqs(2) ae12 unused ae13 db_ras ae14 unused ae15 d3_data(03) ae16 d3_data(09) ae17 d2_data(08) ae18 d3_addr(05) ae19 d3_addr(12) ae20 d2_data(07) ae21 d2_data(09) ae22 d6_data(14) ae23 d6_data(09) ae24 d6_addr(02) ae25 mgrant_b(1) ae26 pci_frame ae27 pci_irdy grid position signal name ae28 pci_trdy ae29 pci_devsel ae30 pci_stop ae31 pci_perr ae32 pci_serr ae33 pci_par af02 2.5 v af04 gnd af06 v dd af07 lu_addr(13) af08 gnd af09 d0_data(20) af10 v dd af11 d0_addr(12) af12 gnd af13 unused af14 2.5 v af15 d3_data(14) af16 gnd af17 d3_addr(02) af18 gnd af19 d3_data(15) af20 v dd af21 d6_dqs_par(01) af22 gnd af23 d6_byteen(1) af24 2.5 v af25 d6_addr(04) af26 gnd af27 pci_ad(17) af28 3.3 v af29 pci_ad(16) af30 gnd af31 pci_cbe(2) af32 v dd grid position signal name af33 pci_clk ag01 plla_gnd ag03 d0_data(09) ag05 lu_addr(09) ag06 lu_addr(10) ag07 d0_data(02) ag08 d0_data(21) ag09 d0_dqs(0) ag10 d0_addr(11) ag11 db_ba(0) ag12 unused ag13 d3_data(00) ag14 d3_data(02) ag15 d3_data(13) ag16 d3_data(10) ag17 d3_data(12) ag18 d3_addr(04) ag19 d3_addr(00) ag20 d3_dqs(0) ag21 d6_addr(11) ag22 d2_data(10) ag23 d2_addr(07) ag24 d6_byteen(0) ag25 da_ras ag26 d6_addr(03) ag27 mgrant_b(0) ag28 pci_ad(23) ag29 pci_ad(22) ag30 pci_ad(21) ag31 pci_ad(20) ag32 pci_ad(19) ag33 pci_ad(18) ah02 gnd ah04 2.5 v ah05 de_ba(1) grid position signal name ibm powernp np2g network processor preliminary physical description page 100 of 539 np2_ds_sec02_phys_pinlist2.fm.01 february 12, 2003 table 2-39. complete signal pin listing by grid position (continued) ah06 gnd ah07 d0_data(10) ah08 2.5 v ah09 d0_dqs(3) ah10 gnd ah11 unused ah12 v dd ah13 unused ah14 gnd ah15 unused ah16 2.5 v ah17 d3_data(11) ah18 v dd ah19 db_clk ah20 gnd ah21 d2_addr(01) ah22 2.5 v ah23 d2_addr(04) ah24 gnd ah25 d6_data(08) ah26 v dd ah27 d6_addr(12) ah28 gnd ah29 pci_ad(24) ah30 v dd ah31 pci_cbe(3) ah32 gnd ah33 pci_idsel aj01 plla_vdd aj03 lu_clk aj04 de_clk aj05 de_clk aj06 d0_data(14) aj07 d0_data(16) aj08 d0_data(31) grid position signal name aj09 d0_addr(02) aj10 unused aj11 unused aj12 db_cas aj13 unused aj14 reserved_io(17) aj15 unused aj16 d3_addr(01) aj17 d3_addr(03) aj18 db_clk aj19 d2_data(01) aj20 d2_data(04) aj21 d2_data(14) aj22 d2_addr(00) aj23 d2_addr(11) aj24 d2_we aj25 d6_we aj26 d6_data(12) aj27 d6_addr(07) aj28 d6_addr(09) aj29 pci_ad(29) aj30 pci_ad(28) aj31 pci_ad(27) aj32 pci_ad(26) aj33 pci_ad(25) ak02 v dd ak03 de_ras ak04 gnd ak05 d0_data(15) ak06 v dd ak07 d0_data(30) ak08 gnd ak09 unused ak10 2.5 v ak11 unused grid position signal name ak12 gnd ak13 unused ak14 v dd ak15 d3_data(07) ak16 gnd ak17 d3_addr(11) ak18 gnd ak19 d3_addr(08) ak20 2.5 v ak21 d2_data(13) ak22 gnd ak23 d2_addr(10) ak24 v dd ak25 d2_dqs(1) ak26 gnd ak27 d6_data(13) ak28 2.5 v ak29 d6_addr(08) ak30 gnd ak31 pci_ad(31) ak32 3.3 v ak33 pci_ad(30) al01 spare_tst_rcvr(4) al02 de_cas al03 d0_data(12) al04 d0_data(08) al05 iew_clk_a al06 d0_data(26) al07 d0_data(19) al08 d0_addr(07) al09 d0_data(25) al10 d0_addr(00) al11 d0_addr(09) al12 unused al13 unused grid position signal name ibm powernp np2g preliminary network processor np2_ds_sec02_phys_pinlist2.fm.01 february 12, 2003 physical description page 101 of 539 table 2-39. complete signal pin listing by grid position (continued) al14 unused al15 d3_data(06) al16 unused al17 d3_data(04) al18 d3_cs al19 d3_addr(09) al20 d2_data(05) al21 d2_addr(09) al22 d2_cs al23 d6_data(00) al24 d6_data(07) al25 da_clk al26 d6_data(02) al27 d6_addr(05) al28 d6_addr(00) al29 d6_addr(10) al30 d6_dqs(0) al31 d6_cs al32 pci_grant al33 pci_request am01 de_ba(0) am02 gnd am03 d0_data(05) am04 2.5 v am05 d0_data(27) am06 gnd am07 d0_addr(06) am08 v dd am09 d0_we am10 gnd am11 d0_addr(08) am12 2.5 v am13 unused am14 gnd am15 unused grid position signal name am16 v dd am17 d3_data(05) am18 2.5 v am19 d2_data(12) am20 gnd am21 d2_addr(03) am22 v dd am23 d6_data(01) am24 gnd am25 da_clk am26 2.5 v am27 d6_data(03) am28 gnd am29 d6_parity(00) am30 v dd am31 d6_dqs(3) am32 gnd am33 pci_inta an01 d0_data(06) an02 d0_data(04) an03 d0_data(07) an04 d0_data(17) an05 iew_clk_a an06 d0_addr(03) an07 d0_data(18) an08 d0_data(24) an09 d0_cs an10 d0_addr(01) an11 unused an12 unused an13 unused an14 unused an15 unused an16 reserved_io(18) an17 d3_addr(10) grid position signal name an18 d2_data(00) an19 d2_data(06) an20 d2_data(11) an21 d2_addr(02) an22 d2_addr(08) an23 d6_parity(01) an24 d6_data(06) an25 d6_data(11) an26 d6_addr(01) an27 da_cas an28 d6_data(05) an29 da_ba(0) an30 d6_addr(06) an31 d6_dqs(1) an32 d6_dqs_par(00) an33 d6_dqs(2) a01 dum a02 sch_addr(11) a03 spare_tst_rcvr(2) a04 sch_addr(02) a05 iew_clk_b a06 sch_data(08) a07 sch_addr(00) a08 sch_data(15) a09 sch_data(07) a10 sch_data(00) a11 d4_addr(01) a12 dd_ba(0) a13 d4_data(31) a14 d4_data(24) a15 d4_data(19) a16 d4_data(11) a17 d4_data(04) a18 ds1_data(26) a19 ds1_data(19) grid position signal name ibm powernp np2g network processor preliminary physical description page 102 of 539 np2_ds_sec02_phys_pinlist2.fm.01 february 12, 2003 table 2-39. complete signal pin listing by grid position (continued) a20 ds1_data(14) a21 ds1_data(06) a22 ds1_data(00) a23 ds0_addr(10) a24 ds0_dqs(2) a25 ds0_data(28) a26 ds0_data(20) a27 ds0_data(14) a28 ds0_addr(00) a29 ds0_data(09) a30 ds0_data(13) a31 ds0_cs a32 ds0_data(01) a33 ds0_data(03) b01 sch_addr(16) b02 gnd b03 sch_addr(13) b04 v dd b05 sch_addr(01) b06 gnd b07 d4_addr(12) b08 2.5 v b09 sch_data(06) b10 gnd b11 d4_addr(07) b12 v dd b13 dd_clk b14 gnd b15 d4_data(25) b16 2.5 v b17 ds1_dqs(0) b18 v dd b19 ds1_data(13) b20 gnd b21 ds1_data(05) grid position signal name b22 2.5 v b23 ds0_addr(05) b24 gnd b25 ds0_data(29) b26 v dd b27 ds0_addr(03) b28 gnd b29 ds0_data(23) b30 2.5 v b31 ds0_data(02) b32 gnd b33 clock125 c01 sch_addr(17) c02 sch_addr(14) c03 sch_addr(09) c04 sch_addr(12) c05 iew_clk_b c06 sch_data(12) c07 sch_clk c08 d4_addr(09) c09 sch_data(14) c10 sch_data(01) c11 d4_addr(06) c12 d4_addr(00) c13 dd_clk c14 d4_data(17) c15 d4_data(03) c16 d4_data(10) c17 ds1_we c18 ds1_data(27) c19 ds1_dqs(1) c20 ds1_data(21) c21 dc_ras c22 ds0_addr(11) c23 ds0_addr(06) grid position signal name c24 ds0_dqs(1) c25 ds0_data(21) c26 ds0_addr(04) c27 ds0_data(15) c28 ds0_data(22) c29 ds0_data(08) c30 ds0_data(04) c31 ds0_data(05) c32 operational c33 core_clock d02 2.5 v d03 sch_addr(15) d04 gnd d05 sch_addr(10) d06 2.5 v d07 sch_data(13) d08 gnd d09 d4_addr(08) d10 v dd d11 d4_dqs(0) d12 gnd d13 d4_data(26) d14 2.5 v d15 d4_data(02) d16 gnd d17 d4_data(05) d18 gnd d19 ds1_dqs(2) d20 v dd d21 ds1_data(12) d22 gnd d23 dc_clk d24 2.5 v d25 dc_ba(0) d26 gnd grid position signal name ibm powernp np2g preliminary network processor np2_ds_sec02_phys_pinlist2.fm.01 february 12, 2003 physical description page 103 of 539 table 2-39. complete signal pin listing by grid position (continued) d27 ds0_data(26) d28 v dd d29 ds0_data(11) d30 gnd d31 dmu_d(01) d32 v dd d33 dmu_d(00) e01 pllb_v dd e03 spare_tst_rcvr(1) e04 sch_addr(05) e05 sch_addr(18) e06 sch_addr(03) e07 sch_addr(04) e08 sch_data(09) e09 d4_data(18) e10 d4_cs e11 d4_dqs(1) e12 d4_data(29) e13 d4_data(27) e14 d4_data(16) e15 d4_data(12) e16 ds1_cs e17 ds1_addr(03) e18 ds1_data(20) e19 ds1_data(25) e20 ds1_data(22) e21 ds1_data(11) e22 ds1_data(08) e23 dc_clk e24 ds0_addr(12) e25 ds0_dqs(3) e26 ds0_data(27) e27 ds0_data(12) e28 ds0_data(10) e29 reset grid position signal name e30 dmu_d(04) e31 dmu_d(29) e32 dmu_d(12) e33 pllc_v dd f02 gnd f04 v dd f05 sch_addr(07) f06 gnd f07 sch_addr(08) f08 v dd f09 sch_data(02) f10 gnd f11 d4_we f12 2.5 v f13 d4_data(30) f14 gnd f15 d4_data(13) f16 v dd f17 ds1_addr(10) f18 2.5 v f19 ds1_data(24) f20 gnd f21 ds1_data(07) f22 v dd f23 ds1_data(04) f24 gnd f25 ds0_dqs(0) f26 2.5 v f27 ds0_data(06) f28 gnd f29 dmu_d(07) f30 3.3 v f31 dmu_d(06) f32 gnd f33 dmu_d(05) grid position signal name g01 pllb_gnd g03 spare_tst_rcvr(5) g05 sch_r_wrt g06 sch_data(10) g07 sch_data(11) g08 sch_data(17) g09 sch_data(05) g10 d4_addr(04) g11 dd_cas g12 d4_data(22) g13 d4_data(08) g14 d4_data(07) g15 ds1_addr(08) g16 ds1_addr(11) g17 ds1_addr(09) g18 ds1_addr(02) g19 ds1_addr(05) g20 ds1_data(30) g21 ds1_data(29) g22 ds1_data(15) g23 ds1_data(01) g24 ds0_addr(07) g25 ds0_data(30) g26 ds0_data(17) g27 pci_bus_nm_int g28 dmu_d(02) g29 dmu_d(11) g30 dmu_d(10) g31 dmu_d(30) g32 dmu_d(08) g33 pllc_gnd h02 v dd h04 gnd h06 2.5 v h07 sch_addr(06) grid position signal name ibm powernp np2g network processor preliminary physical description page 104 of 539 np2_ds_sec02_phys_pinlist2.fm.01 february 12, 2003 table 2-39. complete signal pin listing by grid position (continued) h08 gnd h09 d4_data(06) h10 2.5 v h11 d4_addr(03) h12 gnd h13 d4_data(23) h14 v dd h15 ds1_addr(07) h16 gnd h17 ds1_addr(04) h18 gnd h19 ds1_addr(06) h20 2.5 v h21 ds0_data(07) h22 gnd h23 ds0_addr(08) h24 v dd h25 ds0_data(16) h26 gnd h27 dmu_d(16) h28 v dd h29 dmu_d(15) h30 gnd h31 dmu_d(14) h32 3.3 v h33 dmu_d(13) j06 mg_data j07 mg_clk j08 mg_nintr j09 pgm_gnd j10 sch_data(16) j11 sch_data(03) j12 d4_addr(02) j13 dd_ba(1) j14 d4_data(21) grid position signal name j15 ds1_data(17) j16 ds1_addr(12) j17 dc_ba(1) j18 ds1_addr(01) j19 ds1_data(31) j20 ds1_data(18) j21 ds1_data(16) j22 ds0_addr(09) j23 ds0_we j24 ds0_data(18) j25 dmu_d(25) j26 dmu_d(24) j27 dmu_d(23) j28 dmu_d(22) j29 dmu_d(03) j30 dmu_d(20) j31 dmu_d(19) j32 dmu_d(18) j33 dmu_d(17) k02 gnd k04 2.5 v k06 gnd k07 boot_picocode k08 v dd k09 unused k10 gnd k11 vref1(1) k12 v dd k13 dd_ras k14 gnd k15 d4_data(09) k16 2.5 v k17 vref2(4) k18 v dd k19 ds1_data(28) grid position signal name k20 gnd k21 ds1_data(02) k22 2.5 v k23 ds0_data(19) k24 gnd k25 dmu_d(09) k26 3.3 v k27 dmu_d(21) k28 gnd k29 dmu_d(28) k30 v dd k31 dmu_d(27) k32 gnd k33 dmu_d(26) l01 unused l04 boot_ppc l08 unused l09 unused l10 vref2(8) l11 pgm_vdd l12 sch_data(04) l13 d4_addr(05) l14 vref2(3) l15 d4_data(20) l16 d4_data(01) l17 ds1_data(10) l18 ds1_data(09) l19 ds0_data(25) l20 ds1_data(03) l21 vref2(5) l22 ds0_data(31) l23 dmu_c(10) l24 dmu_c(09) l25 dmu_c(08) l26 dmu_c(07) grid position signal name ibm powernp np2g preliminary network processor np2_ds_sec02_phys_pinlist2.fm.01 february 12, 2003 physical description page 105 of 539 table 2-39. complete signal pin listing by grid position (continued) l27 dmu_c(06) l28 dmu_c(05) l29 dmu_c(04) l30 dmu_c(03) l31 dmu_c(02) l32 dmu_c(01) l33 dmu_c(00) m02 2.5 v m04 gnd m05 unused m06 v dd m07 pci_speed m08 gnd m09 unused m10 2.5 v m11 unused m12 gnd m13 d4_addr(10) m14 2.5 v m15 d4_dqs(3) m16 gnd m17 d4_data(00) m18 gnd m19 ds0_addr(02) m20 2.5 v m21 ds0_data(24) m22 gnd m23 dmu_c(16) m24 v dd m25 dmu_c(15) m26 gnd m27 dmu_c(14) m28 3.3 v m29 dmu_c(13) m30 gnd grid position signal name m31 dmu_c(12) m32 v dd m33 dmu_c(11) n05 unused n06 pio(2) n07 cam_cp_response(13) n08 pio(1) n09 pio(0) n10 unused n11 vref2(7) n12 unused n13 v dd n14 d4_addr(11) n15 d4_dqs(2) n16 d4_data(15) n17 ds1_addr(00) n18 ds1_data(23) n19 dc_cas n20 ds0_addr(01) n21 v dd n22 reserved_io(58) n23 dmu_c(27) n24 dmu_c(26) n25 dmu_c(25) n26 dmu_c(24) n27 dmu_c(23) n28 dmu_c(22) n29 dmu_c(21) n30 dmu_c(20) n31 dmu_c(19) n32 dmu_c(18) n33 dmu_c(17) p02 gnd p04 v dd p05 cam_cp_response(02) grid position signal name p06 gnd p07 cam_cp_response(05) p08 2.5 v p09 cam_cp_response(09) p10 gnd p11 unused p12 2.5 v p13 unused p14 gnd p15 d4_data(28) p16 v dd p17 gnd p18 v dd p19 ds0_data(00) p20 gnd p21 reserved_io(53) p22 3.3 v p23 reserved_io(21) p24 gnd p25 reserved_io(20) p26 v dd p27 reserved_io(19) p28 gnd p29 dmu_c(30) p30 3.3 v p31 dmu_c(29) p32 gnd p33 dmu_c(28) r01 cam_cp_response(07) r04 lu_addr(08) r05 lu_data(33) r06 cam_cp_response(03) r07 lu_data(04) r08 lu_data(05) r09 cam_cp_response(10) grid position signal name ibm powernp np2g network processor preliminary physical description page 106 of 539 np2_ds_sec02_phys_pinlist2.fm.01 february 12, 2003 table 2-39. complete signal pin listing by grid position (continued) r10 cam_cp_response(08) r11 unused r12 unused r13 cam_cp_response(12) r14 cam_cp_response(11) r15 gnd r16 unused r17 d4_data(14) r18 ds1_dqs(3) r19 gnd r20 reserved_io(52) r21 reserved_io(54) r22 reserved_io(37) r23 reserved_io(32) r24 reserved_io(31) r25 reserved_io(30) r26 reserved_io(29) r27 reserved_io(28) r28 unused r29 reserved_io(26) r30 reserved_io(25) r31 reserved_io(24) r32 reserved_io(23) r33 reserved_io(22) t01 spare_tst_rcvr(3) t02 v dd t03 spare_tst_rcvr(8) t04 gnd t05 cam_cp_response(06) t06 2.5 v t07 lu_data(03) t08 gnd t09 lu_data(02) t10 v dd t11 cam_cp_response(01) grid position signal name t12 gnd t13 cam_cp_response(04) t14 v dd t15 lu_data(24) t16 gnd t17 v dd t18 gnd t19 send_grant_b t20 v dd t21 res_data t22 gnd t23 reserved_io(38) t24 3.3 v t25 jtag_trst t26 gnd t27 reserved_io(36) t28 v dd t29 reserved_io(35) t30 gnd t31 reserved_io(34) t32 3.3 v t33 reserved_io(33) u01 lu_data(30) u02 thermal_out u03 lu_data(35) u04 thermal_in u05 spare_tst_rcvr(0) u06 testmode(1) u07 lu_addr(19) u07 unused u08 lu_data(08) u09 cam_cp_response(00) u10 lu_data(34) u11 unused u12 lu_data(11) grid position signal name u13 lu_data(01) u14 gnd u15 lu_data(00) u16 v dd u17 gnd u18 v dd u19 mgrant_a(1) u20 gnd u21 res_sync u22 jtag_tms u23 reserved_io(55) u24 reserved_io(48) u25 reserved_io(47) u26 reserved_io(46) u27 reserved_io(45) u28 reserved_io(44) u29 reserved_io(43) u30 reserved_io(42) u31 reserved_io(41) u32 reserved_io(40) u33 spare_tst_rcvr(9) v01 spare_tst_rcvr(6) v02 2.5 v v03 spare_tst_rcvr(7) v04 gnd v05 testmode(0) v06 v dd v07 lu_data(09) v08 gnd v09 lu_data(10) v10 2.5 v v11 lu_data(14) v12 gnd v13 lu_data(18) v14 v dd grid position signal name ibm powernp np2g preliminary network processor np2_ds_sec02_phys_pinlist2.fm.01 february 12, 2003 physical description page 107 of 539 table 2-39. complete signal pin listing by grid position (continued) v15 lu_data(12) v16 gnd v17 v dd v18 gnd v19 mgrant_a(0) v20 v dd v21 i_freeq_th v22 gnd v23 reserved_io(56) v24 v dd v25 reserved_io(39) v26 gnd v27 dmu_a(02) v28 3.3 v v29 dmu_a(01) v30 gnd v31 dmu_a(00) v32 v dd v33 reserved_io(49) w01 lu_data(20) w04 lu_data(13) w05 lu_data(07) w06 lu_data(06) w07 lu_data(15) w08 lu_data(16) w09 lu_data(21) w10 lu_data(25) w11 lu_data(31) w12 lu_data(26) w13 lu_data(19) w14 lu_data(27) w15 gnd w16 unused w17 d3_data(08) w18 d2_data(02) grid position signal name w19 gnd w20 send_grant_a w21 reserved_io(51) w22 jtag_tdi w23 dmu_a(13) w24 dmu_a(12) w25 dmu_a(11) w26 dmu_a(10) w27 dmu_a(09) w28 dmu_a(08) w29 dmu_a(07) w30 dmu_a(06) w31 dmu_a(05) w32 dmu_a(04) w33 dmu_a(03) y02 gnd y04 2.5 v y05 lu_data(32) y06 gnd y07 lu_data(17) y08 v dd y09 lu_data(22) y10 gnd y11 lu_addr(01) y12 2.5 v y13 vref2(6) y14 gnd y15 unused y16 v dd y17 gnd y18 v dd y19 d2_data(15) y20 gnd y21 reserved_io(50) y22 3.3 v grid position signal name y23 dmu_a(19) y24 gnd y25 dmu_a(18) y26 3.3 v y27 dmu_a(17) y28 gnd y29 dmu_a(16) y30 v dd y31 dmu_a(15) y32 gnd y33 dmu_a(14) grid position signal name ibm powernp np2g network processor preliminary physical description page 108 of 539 np2_ds_sec02_phys_pinlist2.fm.01 february 12, 2003 ibm powernp np2g preliminary network processor np2_ds_sec03_pmm.fm.01 february 12, 2003 physical mac multiplexer page 109 of 539 3. physical mac multiplexer the physical mac multiplexer (pmm) moves data between physical layer devices and the network processor. the pmm interfaces with the network proc essor?s external ports in the ingress (i-pmm) and egress (e-pmm) directions. the pmm includes five data move r units (dmus), as illustrated in figure 3-1 . three dmus (a, c, and d) can each be independently configured as an ethernet medium access control (mac) or a packet over sonet (pos) mac. the device keeps a complete set of performance statistics on a per-port basis in either mode. each dmu moves data at 1 gigabit per second (gbps) in both the ingress and the egress directions. the wrap dmu enables traffic generated by the np2g?s egress side to move to the ingress side of the device. figure 3-1. pmm overview w d c np2g ingress eds dmu a c d w pmm egress eds dmu a ibm powernp np2g network processor preliminary physical mac multiplexer page 110 of 539 np2_ds_sec03_pmm.fm.01 february 12, 2003 3.1 ethernet overview for ethernet operation, the uplink/control point port (dmu a) can be configured as either a gigabit media- independent interface (gmii) or a ten-bit interface (tbi). the other data movers (dmu c & d) can be config- ured for either gigabit or fast ethernet. the same two gigabit modes are supported as on dmu a plus a serial media-independent interface (smii). in this mode, the single dmu mac can be configured as ten ports. figure 3-2 shows a sample np2g with the pmm configured for ethernet interfaces. dmu a is configured as a gigabit ethernet mac. dmus c and d are configured as fast ethernet macs. 3.1.1 ethernet interface timing diagrams the following figures show timing diagrams for the ethernet interfaces: figure 3-3 figure 3-4: gmii timing diagram on page 111 figure 3-5: tbi timing diagram on page 111 figure 3-6: gmii pos mode timing diagram on page 112. figure 3-2. ethernet mode figure 3-3. smii timing diagram dmu - a np2g phy gmii or tbi 1 gigabit ethernet port dmu - c phy dmu - d phy smii smii up to ten fast ethernet ports up to ten fast ethernet ports clock sync rx crs rx_dv rxd0 rxd1 rxd2 rxd3 rxd4 rxd5 rxd6 rxd7 crs tx_er tx_en txd0 txd1 txd2 txd3 txd4 txd5 txd6 txd7 tx_er tx ibm powernp np2g preliminary network processor np2_ds_sec03_pmm.fm.01 february 12, 2003 physical mac multiplexer page 111 of 539 figure 3-4. gmii timing diagram figure 3-5. tbi timing diagram rx_clk rx_dv rxd<7:0> rx_er fcs preamble sfd receive tx_clk tx_en txd<7:0> tx_er fcs preamble transmit tr i tx_clk tx_en txd[7:0] tx_er fcs preamble tx code group i = idle s = start of packet d = data t = end of packet (part 1) r = end of packet (part 2 or 3) isd d dd ddddd dd ddd rx_clk1 2.0 v rx_code_group[9:0] 1.4 v 0.8 v rx_clk0 t hold comma code-group valid data t setup t hold t setup receive clocks and receive data transmit data ibm powernp np2g network processor preliminary physical mac multiplexer page 112 of 539 np2_ds_sec03_pmm.fm.01 february 12, 2003 3.1.2 ethernet counters the np2g provides 36 ethernet statistics counters per mac (up to one million so ftware-defined, hardware- assisted counters), enabling support of many standard management information bases (mibs) at wire speed. table 3-1: ingress ethernet counters on page 112 and table 3-2: egress ethernet counters on page 114 show the statistics counters kept in each dmu when it operates in ethernet mode. these counters are acces- sible through the control access bus (cab) interface. figure 3-6. gmii pos mode timing diagram table 3-1. ingress ethernet counters (page 1 of 3) name / group counter no. group description notes short frames x?00? total number of frames received that were less than 64 octets long and were otherwise well-formed (had a good crc). 1, 2 fragments x?01? total number of frames received that were less than 64 octets long and had a bad crc. 1, 2 frames received (64 octets) x?02? total number of frames (inc luding bad frames) received that were 64 octets in length. 1, 2 frames received (65 to 127 octets) x?03? total number of frames (i ncluding bad frames) received that were between 65 and 127 octets in length inclusive. 1, 2 frames received (128 to 255 octets) x?04? total number of frames (including bad frames) received that were between 128 and 255 octets in length inclusive. 1, 2 frames received (256 to 511 octets) x?05? total number of frames (including bad frames) received that were between 256 and 511 octets in length inclusive. 1, 2 1. the states of vlan or jumbo have no effect on this count. 2. excluding framing bits but including crc octets 3. reception of frames meeting the criteria for this counter are aborted by the hardware. abort is indicated in the ingress port control block and in the ingress frame control block. if the frame has not been forwarded by the picocode, the picocode must enqueue the frame to the ingress discard queue. if the frame has been forw arded, then the egress hardware will discard the frame. furth er reception at the mac is inhibited until the next frame starts. 4. the maximum length of a jumbo frame is determined by the value in the ethernet jumbo frame size register (see section 13.26 beginning on page 489). rx_data receive valid byte tx_data transmit byte credit valid skip byte do not send ok to send valid valid valid do not send ok to send ok to send transmit valid byte ibm powernp np2g preliminary network processor np2_ds_sec03_pmm.fm.01 february 12, 2003 physical mac multiplexer page 113 of 539 frames received (512 to 1023 octets) x?06? total number of frames (i ncluding bad frames) received that were between 512 and 1023 octets in length inclusive. 1, 2 frames received (1024 to 1518 octets) x?07? total number of frames (i ncluding bad frames) received that were between 1024 and 1518 octets in length inclusive. 1, 2 jumbo frames x?14? total number of frames (i ncluding bad frames) received with a length between 1519 octets and the configured maximum length of a jumbo frame, or between 1519 octets and configured maximum length of a jum bo frame plus 4 if vlan is asserted. 4 long frames received x?08? 4 total number of long frames received with a good crc that were either: 1) longer than 1518 octets (excluding frami ng bits, but including crc octets), and were otherwise well-formed (good crc), vlan and jumbo deasserted 2) vlan frames that were longer than 1522 octets, with jumbo deasserted 3) jumbo frames that were longer than the configured maximum length of a jumbo frame in octets, with vlan deasserted 4) jumbo vlan frames that were longer than the configured maximum length of a jumbo frame plus 4 in octets 3, 4 jabber x?09? total number of long frames received with bad crc that were either: 1) longer than 1518 octets (excluding frami ng bits, but including crc octets), and were not well-formed (bad crc), vlan and jumbo not asserted 2) vlan frames that were longer than 1522 octets, with jumbo deasserted 3) jumbo frames that were longer than the configured maximum length of a jumbo frame in octets, with vlan deasserted 4) jumbo vlan frames that were longer than the configured maximum length of a jumbo frame plus 4 in octets 3, 4 frames with bad crc x?0a? total number of frames received th at were not long frames, but had bad crc. 2 unicast frames received x?0b? total number of good frames received that were directed to the unicast address (exclud- ing multicast frames, broadc ast frames, or long frames). broadcast frames received x?0c? 3 total number of good frames received that were directed to the broadcast address (excluding multicast frames or long frames). multicast frames received x?0d? total number of good frames received that were directed to the multicast address (excluding broadcast fram es, or long frames). total frames received x?0e? total number of frames (i ncluding bad frames, broadcast fr ames, multicast frames, uni- cast frames, and long frames) received. receive errors x?0f? total number of frames received in which the phy detected an error and asserted the rx_err signal. overruns x?13? 2 total number of frames received when the pmm internal buffer was full and the frame couldn?t be stored. includes frames in the process of being received when the pmm internal buffer becomes full. table 3-1. ingress ethernet counters (page 2 of 3) name / group counter no. group description notes 1. the states of vlan or jumbo have no effect on this count. 2. excluding framing bits but including crc octets 3. reception of frames meeting the criteria for this counter are aborted by the hardware. abort is indicated in the ingress port control block and in the ingress frame control block. if the frame has not been forwarded by the picocode, the picocode must enqueue the frame to the ingress discard queue. if the frame has been forw arded, then the egress hardware will discard the frame. furth er reception at the mac is inhibited until the next frame starts. 4. the maximum length of a jumbo frame is determined by the value in the ethernet jumbo frame size register (see section 13.26 beginning on page 489). ibm powernp np2g network processor preliminary physical mac multiplexer page 114 of 539 np2_ds_sec03_pmm.fm.01 february 12, 2003 pause frames x?10? total number of mac pause frames received that were well-formed and had a good crc. total pause time x?11? 1 total amount of time spent in a pause cond ition as a result of receiving a good pause mac frame. total octets received x?12? 0 total number of octets of data (including those in bad frames) received on the network. 2 table 3-2. egress ethernet counters (page 1 of 3) name counter no. group description cnt short frames x?00? total number of frames transmitt ed with less than 64 octets that had good crc. 1, 2 runt frames (bad crc) x?01? total number of frames trans mitted with less than 64 octets that had bad crc. 1, 2 frames transmitted (64 octets) x?02? total number of frames (including bad fr ames) transmitted that were 64 octets in length. 1 frames transmitted (65 to 127 octets) x?03? total number of frames (including bad frames) transmitted that were between 65 and 127 octets in length inclusive. 1, 3 frames transmitted (128 to 255 octets) x?04? total number of frames (including bad frames) transmitted that were between 128 and 255 octets in length inclusive. 1, 3 frames transmitted (256 to 511 octets) x?05? total number of frames (including bad frames) transmitted that were between 256 and 511 octets in length inclusive. 1, 3 frames transmitted (512 to 1023 octets) x?06? total number of frames (including bad frames) transmitted that were between 512 and 1023 octets in length inclusive. 1, 3 frames transmitted (1024 to 1518 octets) x?07? total number of frames (including bad frames) transmitted that were between 1024 and 1518 octets in length inclusive. 1, 3 jumbo frames x?16? total number of frames (including bad frames) transmitted with a length between 1519 octets and the configured maxi mum length of a jumbo frame, or between 1519 octets and configured maximum length of a jumbo frame plus 4 if vlan is asserted. if jumbo is not asserted, the frame is a long frame. 4 1. the states of vlan or jumbo have no effect on this count. 2. including the frame type byte. 3. excluding framing bits but including crc octets. 4. for np2g the maximum length of a jumbo frame is determined by the value in the ethernet ju mbo frame size register (see sec- tion 13.26 beginning on page 489). table 3-1. ingress ethernet counters (page 3 of 3) name / group counter no. group description notes 1. the states of vlan or jumbo have no effect on this count. 2. excluding framing bits but including crc octets 3. reception of frames meeting the criteria for this counter are aborted by the hardware. abort is indicated in the ingress port control block and in the ingress frame control block. if the frame has not been forwarded by the picocode, the picocode must enqueue the frame to the ingress discard queue. if the frame has been forw arded, then the egress hardware will discard the frame. furth er reception at the mac is inhibited until the next frame starts. 4. the maximum length of a jumbo frame is determined by the value in the ethernet jumbo frame size register (see section 13.26 beginning on page 489). ibm powernp np2g preliminary network processor np2_ds_sec03_pmm.fm.01 february 12, 2003 physical mac multiplexer page 115 of 539 long frames transmitted x?08? 4 total number of frames with good crc transmitted that were either: 1) longer than 1518 octets (excluding framing bits, but including crc octets), and were otherwise well-formed (good crc), vlan and jumbo are deasserted 2) vlan frames that were longer than 1522 octets with jumbo deasserted 3) jumbo frames that were longer than the configured maximum length of a jumbo frame in octets with jumbo deasserted 4) jumbo vlan frames that were longer than the configured maximum length of a jumbo frame plus 4 in octets 4 jabber x?09? total number of frames with bad crc transmitted that were either: 1) longer than 1518 octets (excluding framing bits, but including crc octets), and were otherwise well-formed (good crc), vlan and jumbo are deasserted 2) vlan frames that were longer than 1522 octets with jumbo deasserted 3) jumbo frames that were longer t han the configured maximum length of a jumbo frame in octets with jumbo deasserted 4) jumbo vlan frames that were longer than the configured maximum length of a jumbo frame plus 4 in octets 4 late collisions x?0a? total number of frames transmitted that experienced a network collision after 64 bytes of the frame had been transmitted. 1 total collisions x?0b? 3 best estimate of the total number of collisions on this ethernet segment. 1 single collisions x?0c? total number of frames transmitted t hat experienced one collision before 64 bytes of the frame were transmitted on the network. 1 multiple collisions x?0d? total number of frames transmitted t hat experienced more than one collision before 64 bytes of the frame were transmitted on the network. 1 excessive deferrals x?0e? total number of frames whose transmi ssion could not be started before the deferral time out expired. the deferral ti me out value is 24,416 media bit times. 1 underruns x?0f? total number of frames that were not completely transmitted because the data could not be obtained from the egress eds fast enough to maintain the media data rate. aborted frames x?17? total number of frames that had one of the following errors: - link pointer parity errors, - header qsb field specification which point beyond the end of frame, - invalid bci specification . when one of these errors occurs, the fr ame transmission is aborted by the egress pmm and the event is counted. information about the event is recorded in the aborted frame error indicator register. when an invalid bci specification is detec ted, twins associated with the frame are not returned to the free queue. table 3-2. egress ethernet counters (page 2 of 3) name counter no. group description cnt 1. the states of vlan or jumbo have no effect on this count. 2. including the frame type byte. 3. excluding framing bits but including crc octets. 4. for np2g the maximum length of a jumbo frame is determined by the value in the ethernet ju mbo frame size register (see sec- tion 13.26 beginning on page 489). ibm powernp np2g network processor preliminary physical mac multiplexer page 116 of 539 np2_ds_sec03_pmm.fm.01 february 12, 2003 crc error x?10? 2 total number of frames transmitted that had a legal length (excluding framing bit, but including crc octets) of bet ween 64 and 9018 octets, (64 and 9022 for vlan frames) inclusive, but had a bad crc. excessive collisions x?11? total number of frames that experienc ed more than 16 collisions during trans- mit attempts. these frames are dropped and not transmitted. unicast frames transmitted x?12? total number of good frames transmitted that were directed to the unicast address (not including multicas t frames or broadcast frames). broadcast frames transmitted x?13? total number of good frames transmitted that were directed to the broadcast address (not includi ng multicast frames). multicast frames transmitted x?14? total number of good frames transmitted t hat were directed to the multicast address (not including broadcast frames). total octets transmitted x?15? 0 total number of octets of data (inc luding those in bad frames) transmitted on the network. 3 table 3-2. egress ethernet counters (page 3 of 3) name counter no. group description cnt 1. the states of vlan or jumbo have no effect on this count. 2. including the frame type byte. 3. excluding framing bits but including crc octets. 4. for np2g the maximum length of a jumbo frame is determined by the value in the ethernet jumbo frame size register (see sec- tion 13.26 beginning on page 489). ibm powernp np2g preliminary network processor np2_ds_sec03_pmm.fm.01 february 12, 2003 physical mac multiplexer page 117 of 539 3.1.3 ethernet support table 3-3 lists the features and standards supported by a dmu in the different ethernet modes. table 3-3. ethernet support feature dmu bus mode 10/100 ethernet smii gigabit ethernet gmii gigabit ethernet tbi compatible with ieee 802.3 ? , 2000. x x x compliant with rfc 1757 management registers and counters (tx/rx counters). additional receive counters for total number of pause frames and total aggregate pause time. additional transmit counters for number of singl e collisions and number of multiple collisions. xxx supports the ieee standards on flow control by honor ing received pause frames and inhibiting frame transmission while maintain ing pause counter statistics. xxx supports smii to the phy. interfaces with up to ten phys that support the smii interface. each of the ten interfaces can have a bit rate of either 10 mbps or 100 mbps. x capable of handling ten ports of 10 mbps or 100 mbps media speeds, any speed mix. x supports half-duplex op erations at media speed on all ports. x supports binary exponential back-off (beb) co mpliant with the ieee 802.3: 1993 (e). x supports full duplex point-to-poin t operations at media speed. x x x detects vlan (8100 frame type) ethernet frames and accounts for them when calculating long frames. xxx supports two ethernet frame types (programmable) and, based on these, detects received frames with a type field that matches one of those types. a match instructs the multi-port 10/100 mac to strip the da, sa, and type fields from the received fram e and to instruct the higher device functions to queue the frame in a different queue. an example of a special functi on is to identify ethernet encaps ulated guided frames. a mismatch results in normal frame queueing and normal higher device processing. xxx programmable cyclic redundancy check (crc) insertion on a frame basis. with crc insertion disabled, mac transmits fram es as is (suitable for switch environments). with crc insertion enabled, the mac calculates and inserts the crc. xxx includes jumbo frame support. when configured, c an transmit and receive up to the configured maxi- mum length of a jumbo frame in octets. this is in creased by plus 4 octets when a vlan tagged frame is detected. for np2g, the maximum length of a jumbo frame is determined by the value in the ethernet jumbo frame size register (see section 13.26 beginning on page 489). xxx supports the ibm rx_byte_valid and tx_byte_credit signals. x can be combined with the tbi to form a complete tbi solution. x interfaces with any pma/pmi physical layer using t he pma service interface defined in the ieee 802.3 standard. x synchronizes the data received from the pma (two phase) clock with the ma c (single phase) clock. provides a signal to the mac indicating t hose clock cycles th at contain new data. x checks the received code groups (10 bits) for commas and establishes word synchronization. x calculates and checks th e tbi running disparity. x supports auto-negotiation including two next pages. x ibm powernp np2g network processor preliminary physical mac multiplexer page 118 of 539 np2_ds_sec03_pmm.fm.01 february 12, 2003 3.2 pos overview the uplink/control point port (dmu a) can support either clear-channel or channelized oc-12 when config- ured in packet over sonet (pos) mode. dmu c and dmu d can support either clear-channel or channelized oc-3c, oc-12, or oc-12c pos framers. table 3-4 shows the two dmu configuration modes: oc-3c and oc-12c. when configured for oc-3c, the dmu assumes that it must poll the four possible attached ports before transferring data. if the dmu is config- ured for oc-12c, the dmu does not poll the framer. figure 3-7 shows a configuration in which the pmm has oc-3c, oc-12, and oc-3 connections operating simultaneously. each of the three dmus has been configured to operate as single port or as four ports. each of the three dmus supports an 8-bit data interface in both the ingress and egress directions. table 3-4. dmu and framer configurations dmu configuration mode networks supported via pos framer oc-3c (8-bit mode) 4 x oc-3c per dmu or 1 x oc-12c per dmu oc-12c (8-bit mode) 1 x oc-12c per dmu figure 3-7. oc-3 / oc-3c / oc-12 configuration framer framer framer oc-12 connection oc-12c 4 x oc-3 or oc-3c connections 4 ports dmu a np2g dmu c dmu d 4 ports 4 ports connection oc-3 or oc-12c mode oc-12 mode 1 x logical channels 4 x logical channels 4 x logical channels oc-3c mode ibm powernp np2g preliminary network processor np2_ds_sec03_pmm.fm.01 february 12, 2003 physical mac multiplexer page 119 of 539 3.2.1 pos timing diagrams the following figures show timing diagrams for the different pos modes: oc-3c - figure 3-8: receive pos8 interface timing for 8-bit data bus (oc-3c) on page 119 - figure 3-9: transmit pos8 interface timing for 8-bit data bus (oc-3c) on page 120 oc-12c - figure 3-10: receive pos8 interface timing for 8-bit data bus (oc-12c) on page 120 - figure 3-11: transmit pos8 interface timing for 8-bit data bus (oc-12c) on page 121 figure 3-8. receive pos8 interface timing for 8-bit data bus (oc-3c) rxclk rxeof rxval rxdata rxenb rxaddr rxpfa 1 2 3 4 5 6 7 8 9 101112131415161718 1920 0 p 1 p 2 p 3 p 0 p 1 p 2 dp 2 dp 0 dp 0 dp 0 dp 0 dp 0 dp 0 dp 0 p 3 p 0 p 2 p 3 p 0 p 1 p 2 p 3 p 0 p 1 p 2 p 3 p 0 p 1 p 2 xx xx xx xx 21 dp 2 xx xx 1. data is being received from port #0 while the dmu is polling. 2. in clock cycle #3 the framer asserts rxpfa indicating data is available. in this example the dmu is configured for two cycles of framer latency (bus_delay = 1), therefore it is port #2 res ponding with rxpfa (clock cycle #1). 3. in clock cycle #6 the dmu deasserts rxenb (negative active ) to indicate it is starting the port selection process. 4. in clock cycle #8 the dmu puts p 2 on rxaddr. 5. in clock cycle #9 the dmu selects port p 2 by asserting rxenb. the port selected is the port whose address is on rxa- ddr the cycle before rxenb is asserted. 6. in clock cycle #16 the framer deasserts rxval (assumed t hat the framer was not ready to continue data transfer) and restarts data transfer to the dmu during clock cycle #17. 7. in clock cycle #18 the framer asserts rxeof marking the last transfer for the frame. 8. in clock cycle #19 the framer deasserts both rxeof and rxval completing the frame transfer. 9. in clock cycle #16 and #17 rxpfa is asserted indicating data is available on ports 0 and 1. 10. in clock cycle #20 the dmu starts the selection of the next port. dp 0 dp 2 xx dp 2 dp 2 dp 2 dp 2 ibm powernp np2g network processor preliminary physical mac multiplexer page 120 of 539 np2_ds_sec03_pmm.fm.01 february 12, 2003 figure 3-9. transmit pos8 interface timing for 8-bit data bus (oc-3c) figure 3-10. receive pos8 interface timing for 8-bit data bus (oc-12c) txclk txsof txeof txdata txenb txaddr txpfa 1 2 3 4 5 6 7 8 9 101112131415161718 1920 0 p 1 p 2 p 3 p 0 p 1 p 2 dp 2 p 3 p 0 p 1 p 2 p 3 p 0 p 1 p 2 p 3 p 0 p 1 p 2 p 3 p 0 p 1 xx xx 21 dp 2 1. in this figure it is assumed that the framer has a 2-cycle delay before responding to the dmu and that the dmu has bus_delay = 1. 2. in clock cycle #3 the framer responds to the poll by asserting txpfa, this indicates that the fifo for ports 2 and 3 have room for data (2 clock cycle delay). 3. in clock cycle #6 the dmu starts transferring a new fr ame to port 2 by asserting txsof, asserting txenb (nega- tive active), and putting data on txdata. 4. in clock cycle #12 the dmu asserts txeof indicating the last transfer of the frame. 5. in clock cycle #13 the dmu deasserts txenb to indicate that the dmu is in the port selection process. 6. in clock cycle #16 the framer asserts txpfa indicating it has data for port 3. 7. in clock cycle #19 the dmu asserts txenb and selects port 3. 8. in clock cycle #19 the dmu asserts txsof indicating the start of a new frame for port 3 and places data on txdata. dp 2 xx dp 2 dp 3 xx xx xx xx xx xx dp 2 dp 2 xx xx xx dp 3 dp 2 rxclk rxeof rxval rxdata rxaddr rxpfa 1 2 3 4 5 6 7 8 9 101112131415161718 1920 0 p 0 p 0 p 0 p 0 p 0 p 0 xx p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 data data 21 data 1. in clock cycle #1 the framer asserts rxpfa indicating it has data to trans fer to the dmu (for oc-12c operation the framer can tie rxpfa to a logical 1 and control data transfers with rxval). 2. in clock cycle #2 the dmu asserts rxenb (negative ac tive) selecting the port whose address was on rxaddr during clock cycle #1 (for oc-12c operation t he dmu must provide rxaddr from the card). 3. in clock cycle #4 the framer asserts rxval and starts t he data transfer to the dmu. data transfer continues as long as rxval is asserted. the framer must deassert rx val at the end of the frame, clock cycle #10, but can deassert and then reassert anytime within the frame. 4. in clock cycle #11 the dmu deasserts rxenb in re sponse to rxeof being asse rted at clock cycle #9. 5. in clock cycle #12 the dmu asserts rxenb in response to rxpfa being asserted. 6. in clock cycle #15 the framer starts the transfer of th e next frame by asserting rxval. the dmu accepts data as early as clock cycle #12 and will wa it (no limit) until the framer asserts rxval before accepting data. 7. the framer can control data transfer using rxval and t he dmu can control data transfer using rxenb. as noted above, rxpfa can remain asserted. data data xx data xx xx xx xx data data data data data xx xx data xx rxenb note : for oc-12c, rxaddr is not provided by the dmu. rxaddr must be provided by board logi c. there is a two cycle delay between the assertion of rxenb and rxval, the dm u can be configured to accept a one cycle delay. ibm powernp np2g preliminary network processor np2_ds_sec03_pmm.fm.01 february 12, 2003 physical mac multiplexer page 121 of 539 figure 3-11. transmit pos8 interface timing for 8-bit data bus (oc-12c) txclk txsof txeof txdata txaddr txpfa 1 2 3 4 5 6 7 8 9 101112131415161718 1920 0 p 0 p 0 p 0 xx p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 xx xx 21 dp 0 1. in clock cycle #0 the framer has txpfa asserted indicating it can accept data from the dmu. 2. in clock cycle #6 the dmu selects port 0 by asserti ng txenb (negative active). the dmu also asserts txsof indicating the beginning of the frame and places data on txdata. 3. in clock cycle #8 the framer indicates it can not ac cept more data by deasserting txpfa. the dmu requires 6 clock cycles to stop data transfer, hence data transfe r stops after clock cycle #13 by deasserting txenb. 4. in clock cycle # 15 the framer asserts txpf a indicating that it can accept more data. 5. in clock cycle #19 the dmu asserts tx enb indicating data is valid on txdata. 6. in clock cycle #20 the dmu asserts txeof indicating the last transfer of the frame. 7. in clock cycle #21 the dmu deasserts txeof and txenb. dp 0 xx dp 0 dp 0 xx xx xx dp 0 dp 0 dp 0 dp 0 dp 0 xx dp 0 txenb note : for oc-12c, txaddr is not provided by the dmu. txaddr must be provided by board logic. xx xx xx xx p 0 p 0 p 0 p 0 ibm powernp np2g network processor preliminary physical mac multiplexer page 122 of 539 np2_ds_sec03_pmm.fm.01 february 12, 2003 3.2.2 pos counters table 3-5 on page 122 and table 3-6 on page 124 provide information about the counters maintained to support pos interfaces. many of the counters defined in these tables deal with long frames. a long frame is a packet whose byte count exceeds the value held in the packet over sonet maximum frame size (pos_max_fs) register (see configuration on page 431). the by te count includes the cyclic redundancy check (crc) octets. reception of packets meeting the criteria for long frames is aborted by the hardware. abort is indicated in the ingress port control block and in the ingress frame control block. if the packet has not been forwarded by the picocode, the picocode must enqueue the packet to the ingress discard queue. if the packet has been forwarded, then the egress hardware w ill discard the frame. further receptio n at the mac is inhibited until the next packet starts. table 3-5. receive counter ram addresses for ingress pos mac (page 1 of 2) port name counter number description port 0 long frames received x?00? total number of frames received that were longer than the value contained in the pos maximum frame size register (pos_max_fs) including crc octets. frames with bad crc x?01? total number of frames received that had a length of the value contained in the pos maximum frame size register (pos_max_fs) or less, but had a bad crc. total good frames received x?02? total number of frames (excluding frames with bad crc, and long frames) received. receive errors x?03? total number of frames received in which the framer detected an error and asserted the rx_err signal. total octets received (including frames with errors) x?10? total number of octets of data (including those in bad frames) received on the network. port 1 (dmu c & d only) long frames received x?04? total number of frames received that were longer than the value contained in the pos maximum frame size register (pos_max_fs) including crc octets. frames with bad crc x?05? total number of frames received that had a length of the value contained in the pos maximum frame size register (pos_max_fs) or less, but had a bad crc. total good frames received x?06? total number of frames (excludi ng frames with a bad crc, and long frames) received. receive errors x?07? total number of frames received in which the framer detected an error and asserted the rx_err signal. total octets received (including frames with errors) x?11? total number of octets of data (including those in bad frames) received on the network. ibm powernp np2g preliminary network processor np2_ds_sec03_pmm.fm.01 february 12, 2003 physical mac multiplexer page 123 of 539 port 2 (dmu c & d only) long frames received x?08? total number of frames received that were longer than the value contained in the pos maximum frame size register (pos_max_fs) including crc octets. frames with bad crc x?09? total number of frames received that had a length of the value contained in the pos maximum frame size register (pos_max_fs) or less, but had a bad crc. total good frames received x?0a? total number of frames (excludi ng frames with a bad crc, and long frames) received. receive errors x?0b? total number of frames received in which the framer detected an error and asserted the rx_err signal. total octets received (including frames with errors) x?12? total number of octets of data (including those in bad frames) received on the network. port 3 (dmu c & d only) long frames received x?0c? total number of frames received that were longer than the value contained in the pos maximum frame size register (pos_max_fs) including crc octets. frames with bad crc x?0d? total number of frames received that had a length of the value contained in the pos maximum frame size register (pos_max_fs) or less, but had a bad crc. total good frames received x?0e? total number of frames (excludi ng frames with a bad crc, and long frames) received. receive errors x?0f? total number of frames received in which the framer detected an error and asserted the rx_err signal. total octets received (including frames with errors) x?13? total number of octets of data (including those in bad frames) received on the network. table 3-5. receive counter ram addresses for ingress pos mac (page 2 of 2) port name counter number description ibm powernp np2g network processor preliminary physical mac multiplexer page 124 of 539 np2_ds_sec03_pmm.fm.01 february 12, 2003 table 3-6. transmit counter ram addresses for egress pos mac (page 1 of 2) port name counter number description port 0 long frames transmitted x?00? total number of frames transmitted that were longer than the value contained in the pos maximum frame size register (pos_max_fs) including crc octets. frames with bad crc x?01? total number of frames transmitted that had a length of the value contained in the pos maximum frame register (pos_max_fs) or less, but had bad crc. total good frames transmitted x?02? total number of frames (excluding frames with a bad crc, and long frames) transmitted. transmit underruns x?03? total number of frames attempted to be transmitted but an under- run occurred in the np2g 1 . total octets transmitted (including frames with errors) x?10? total number of octets of data (including those in bad frames) transmitted on the network. aborted frames x?14? total number of frames that had one of the following errors: - link pointer parity errors, - header qsb field specification which point beyond the end of frame, - invalid bci specification . when one of these errors occu rs, the frame transmission is aborted by the egress pmm and the event is counted. information about the event is recorded in the aborted frame error indicator register. when an invalid bci specification is detected, twins associated with the frame are not returned to the free queue. port 1 (dmu c & d only) long frames transmitted x?04? total number of frames transmitted that were longer than the value contained in the pos maximum frame size register (pos_max_fs) including crc octets. frames with bad crc x?05? total number of frames transmitted that had a length of the value contained in the pos maximum frame register (pos_max_fs) or less, but had bad crc. total good frames transmitted x?06? total number of frames (excluding frames with a bad crc, and long frames) transmitted. transmit underruns x?07? total number of frames attempted to be transmitted, but an under- run occurred in the np2g 1 . total octets transmitted (including frames with errors) x?11? total number of octets of data (including those in bad frames) transmitted on the network. aborted frames x?15? total number of frames that had one of the following errors: - link pointer parity errors, - header qsb field specification which point beyond the end of frame, - invalid bci specification when one of these errors occu rs, the frame transmission is aborted by the egress pmm and the event is counted. information about the event is recorded in the aborted frame error indicator register. when an invalid bci specification is detected, twins associated with the frame are not returned to the free queue. 1. np2g does not detect underrun errors; underrun detection is perform ed by the attached framer only. ibm powernp np2g preliminary network processor np2_ds_sec03_pmm.fm.01 february 12, 2003 physical mac multiplexer page 125 of 539 port 2 (dmu c & d only) long frames transmitted x?08? total number of frames transmitted that were longer than the value contained in the pos maximum frame size register (pos_max_fs) including crc octets. frames with bad crc x?09? total number of frames transmitted that had a length of the value contained in the pos maximum frame register (pos_max_fs) or less, but had bad crc. total good frames transmitted x?0a? total number of frames (excluding frames with a bad crc, and long frames) transmitted. transmit underruns x?0b? total number of frames attempted to be transmitted, but an under- run occurred in the np2g 1 . total octets transmitted (including frames with errors) x?12? total number of octets of data (including those in bad frames) transmitted on the network. aborted frames x?16? total number of frames that had one of the following errors: - link pointer parity errors, - header qsb field specification which point beyond the end of frame, - invalid bci specification when one of these errors occu rs, the frame transmission is aborted by the egress pmm and the event is counted. information about the event is recorded in the aborted frame error indicator register. when an invalid bci specification is detected, twins associated with the frame are not returned to the free queue. port 3 (dmu c & d only) long frames transmitted x?0c? total number of frames transmitted that were longer than the value contained in the pos maximum frame size register (pos_max_fs) including crc octets. frames with bad crc x?0d? total number of frames transmitted that had a length of the value contained in the pos maximum frame register (pos_max_fs) or less, but had bad crc. total good frames transmitted x?0e? total number of frames (excluding frames with a bad crc, and long frames) transmitted. transmit underruns x?0f? total number of frames attempted to be transmitted but an under- run occurred in the np2g 1 . total octets transmitted (including frames with errors) x?13? total number of octets of data (including those in bad frames) transmitted on the network. aborted frames x?17? total number of frames that had one of the following errors: - link pointer parity errors, - header qsb field specification which point beyond the end of frame, - invalid bci specification . when one of these errors occu rs, the frame transmission is aborted by the egress pmm and the event is counted. information about the event is recorded in the aborted frame error indicator register. when an invalid bci specification is detected, twins associated with the frame are not returned to the free queue. table 3-6. transmit counter ram addresses for egress pos mac (page 2 of 2) port name counter number description 1. np2g does not detect underrun errors; underrun detection is perform ed by the attached framer only. ibm powernp np2g network processor preliminary physical mac multiplexer page 126 of 539 np2_ds_sec03_pmm.fm.01 february 12, 2003 3.2.3 pos support table 3-7 lists the features and standards supported by a dmu in the different pos modes. table 3-7. pos support feature pos mode oc-3c & oc-12c (8-bit) supports quad-port oc-3c connections, quad-port oc-12 connecti ons, or single-port oc-12c connections x compatible with flexbus? 3 - quad- 8 bit bus operational mode x compatible with flexbus? 3 - si ngle - 32 bit bus operational mode programmable crc insert ion on a frame basis. with crc insertion disabled, the mac transmits fr ames as is (suitable for switch environments). with crc insertion enabled, the mac calculates and inserts the crc. x the minimum frame length the np2g can handle at a sustai nable rate is 18 bytes. sma ller frames can be handled, but will consume the bandwidth of an 18-byte frame. an indirect back-pressure between the processor and the framer prevents frames from being lost, unless many sma ll frames are received back-to-back. x provides the following nine tx c ounters for testing and debugging purposes: number of bytes transmitted / received number of frames transmitted / received number of long frames transmitted / received number of frames with bad crc transmitted / received number of receive errors x ibm powernp np2g preliminary network processor np2_ds_sec04_ieds.fm.01 february 12, 2003 ingress enqueuer / dequeuer / scheduler page 127 of 539 4. ingress enqueuer / dequeuer / scheduler 4.1 overview the ingress enqueuer / dequeuer / scheduler (ingress eds) interfaces with the physical mac multiplexer (pmm), the embedded processor complex (epc), and the ingress-to-egress wrap (iew). frames that have been received on the data mover unit (dmu) interface are passed through the pmm to the ingress eds. the ingress eds collects the frame data in its internal data store; when it has received sufficient data, the ingress eds enqueues the frame to the epc for processing. th e ingress eds does not need to receive the entire frame before it enqueues the data (that is, it can operate in cut-through mode). once the epc processes the frame, it provides forwarding and quality of service (qos) information to the ingress eds. the ingress eds then invokes hardware configured flow control mechanisms and then either discards the frame or places it into a queue to await transmission. the ingress eds schedules all frames that cross the iew. after it selects a frame, the ingress eds passes the frame data to the iew, which segments the frame into data cells and sends them on to the egress eds. ibm powernp np2g network processor preliminary ingress enqueuer / dequeuer / scheduler page 128 of 539 np2_ds_sec04_ieds.fm.01 february 12, 2003 4.2 operation figure 4-1 illustrates the operations of the ingress eds discussed in this section. the frame demultiplexer (fd) receives incoming frames from the pmm. an fcb is allocated on-the-fly from the fcb free queue as each new frame starts. the fd wr ites each frame as a list of chained data buffers into its internal ingress data store. the buffer addresses are dequeued on-the-fly from the bcb free queue, which is the linked list of all currently available data buffer addresses. the epc can process the frames under one of the following conditions: cut-through mode is disabled and the frame has been completely received. cut-through mode is enabled and sufficient data has been received. the quantity of sufficient data in cut-through mode is programmable in increments of 64 bytes. the first 64 bytes of a frame, in most cases, contain the information to be used in layer 2, layer 3, and layer 4 forwarding. when a frame is ready for processing by the epc, the ingress eds enqueues its fcb to an input queue: either the i-gfq (for control frames) or the gdq (for data frames). figure 4-1. logical organization of ingress eds data flow management sof rings priority high unicast run queues multicast run queues to iew to any sof ring / from epc to epc frame demultiplexer from pmm fcb free queue bcb free queue gdq discard run queues output scheduler mc/discard scheduler low high low high low i-gfq ibm powernp np2g preliminary network processor np2_ds_sec04_ieds.fm.01 february 12, 2003 ingress enqueuer / dequeuer / scheduler page 129 of 539 the epc is responsible for recognizing that a frame is ready to be processed, dequeueing and processing it, and giving it back to the ingress eds (by enqueueing to a tdmu queue) for forwarding to the iew. the epc returns each frame in an ingress enqueue operation to a specific target data mover unit (tdmu) queue (as determined by the routing table lookup). at this point in the flow, the ingress eds flow control logic determines if the frame should be enqueued into the ingress scheduler (that is, added to the tdmu queue) or if it should be discarded. see section 4.3 ingress flow control on page 132 for details. tdmu queues are linked in start-of-frame (sof) rings. an sof ring can hold up to four tdmu queues. to maintain optimal ring structure, only non-empty tdmu queue are included in an sof ring. each sof ring is associated with a particular run queue , creating an sof ring / run queue set that provides a fair initiation of frame transmission to all dmus of the network processo r. fairness is achieved by a round- robin mechanism that successively selects each tdmu queue in the sof ring. when a tdmu queue is selected, the frame currently at its head is dequeued from the tdmu queue and enqueued in a run queue (the actual entry-point of data movement to the iew once sufficient data for forwarding has been received. there are two sof ring / run queue sets: one for unicast high priority traffic and one for unicast low priority traffic. four other sets are reserved for multic ast high and low priority traffic, and for high and low priority discard traffic. for each priority plane, round-robin scheduling is performed between the selected unicast candidate and the candidate from the multicast and discard run queues. these schedulers are controlled by the status (empty or non-empty) of each run queue, and by the flow control indication received from the egress side. absolute priority is enforced: the low priority candidat e is used only if there is no high priority candidate present at the time. the cut-through fu nction is supported by queueing partial frames that contain enoug h data to fill a cell. if, after scheduling to the ie w, enough data remains in the fr ame to fill another cell, then the frame is kept in the run queue. if all the frame data has not been received from the pmm, but there is insufficient data in the data store to fill the next cell, the fcb is removed from the run queue and left ?floating? (not pa rt of any queue). when the frame demultiplexer detects that there is enough data to fill a cell, or the last byte of the frame is received, it re-enqueues the frame in its run queue. if all the frame data has been received, the fcb stays in the run queue until all the data has been moved to the iew. at that point, the fcb is sent to the fcb free queue. as can be seen from the above description, the i-eds may have multiple frames ?in flight?. the number of frames that may be simultaneously in a state of transmis sion is controlled by the number of correlators avail- able, which is 64 for unicast and 32 for multicast. the i-eds maintains correlator free pools for unicast and multicast frames and for each priority (total of four free pools). note: for packed frames, two correlators are required, one for the frame completing and one for the frame that is starting (see table 5-1: cell header fields on page 137 and table 5-2: frame header fields on page 139). ibm powernp np2g network processor preliminary ingress enqueuer / dequeuer / scheduler page 130 of 539 np2_ds_sec04_ieds.fm.01 february 12, 2003 4.2.1 operational details this section provides more details about some of the operations described in section 4.2 . figure 4-2 details the structure of the start-of-frame (sof) rings acting as multiple-port entry points to the target data mover unit (tdmu) queues. an sof ring is a circular linked list of tdmu queues dynamically inserted into and removed from the ring. note that the multicast and discard sof rings contain only a single tdmu queue. figure 4-3: ingress eds logical structure on page 131 illustrates the various logical structures of the eds that are discussed in the rest of this section. a frame (or packet) is stored in the internal ingress data store in the form of a linked list of data buffers. each data buffer is a 64-byte area of the ingress data store. the ingress data store has 2048 data buffers avail- able, each with a unique identifier value (0 through 2047). data buffers are chained by next buffer control block address (nba) pointers located in buffer control blocks (bcbs). one bcb is associated with each data buffer and shares the same identifier value (there are 2048 bcbs). bcbs are physically located in an independent imbedded memory. figure 4-2. sof ring structure four tdmu queues round-robin scheduler to sof queue (maximum for sof queue) ibm powernp np2g preliminary network processor np2_ds_sec04_ieds.fm.01 february 12, 2003 ingress enqueuer / dequeuer / scheduler page 131 of 539 each frame is represented by a frame control block (fcb) that identifies the new frame by data location (the address of the first buffer in the data store) and control information (the source port from which this frame originated). 2048 fcbs are available in an independent embedded memory. each fcb contains parameters associated with the frame, such as the two pointers shown in figure 4-3 : the control block address (cba) points to the first data buffer of a frame (for frames whose transmission to the iew has not started), or the data buffer ready to be transmitted (for frames whose transmission to the iew has already started). the next fcb address (nfa) points to the fcb of the next frame in the queue. the fcb also maintains information about the amount of one frame?s data currently in the ingress data store. as the data is moved out of the data store ac ross the iew, the fcb accounting information reflects the reduction in data present in the data st ore. at the same ti me, more of the fram e?s data may still be arriving from the pmm, and the accoun ting information in the fcb will reflect the increase of da ta in the data store. frames are chained in queues which consist of fifo-lin ked lists of fcbs and the queue control blocks tdmu queues. a tdmu queue contains the information necess ary to manage the linked list of fcbs, particularly: head pointer: points to the first fcb in the queue tail pointer: points to the last fcb in the queue count: indicates how many fcbs are present in the queue next qcb address (nqa) pointer: points to the next tdmu queue. this pointer enables the chaining of tdmu queues and is the mechanism for creating the sof ring and tdmu queues. figure 4-3. ingress eds logical structure tdmu queue head pointer tail pointer count bcb data buffer nqa pointer tdmu queue chaining used for tdmu queues in sof ring frame cba data buffer data buffer tdmu queue head pointer tail pointer count nqa pointer tdmu queue head pointer tail pointer count nqa pointer linked list nba nba bcb bcb nfa nfa nfa fcb fcb fcb nfa fcb ibm powernp np2g network processor preliminary ingress enqueuer / dequeuer / scheduler page 132 of 539 np2_ds_sec04_ieds.fm.01 february 12, 2003 4.3 ingress flow control flow control (whether to forward or discard frames) in the network processor is provided by hardware assist mechanisms and by picocode that implements a selected flow control algorithm. in general, flow control algo- rithms require information about the congestion state of the data flow, the rate at which packets arrive, the current status of the data store, th e current status of the egress side, and so on. a transmit probability for various flows is an output of these algorithms. the network processor implements flow control in two ways: flow control is invoked when the frame is enqueued to a start-of-frame (sof) queue. the hardware assist mechanisms use the transmit probability along with tail drop congestion indicators to determine if a forwarding or discard action should be taken during frame enqueue operation. the flow control hardware uses the picocode?s entries in th e ingress transmit pro bability memory to determ ine what flow control actions are required. flow control is invoked when frame data enters the network processor. when the ingress ds is suffi- ciently congested, these flow cont rol actions discard either all frames, all data frames, or new data frames. the thresholds that control the invocation of these actions are bcb_fq threshold for guided traffic, bcb_fq_threshold_0, and bcb_fq_threshold_1 (see table 4-1: flow control hardware facili- ties on page 133 for more information). 4.3.1 flow control hardware facilities the hardware facilities listed in table 4-1 on page 133 are provided for the picocode's use when imple- menting a flow control algorithm. the picocode uses the information from these facilities to create entries in the ingress transmit prob ability memory. the flow control hardware uses these entries when determining what flow control actions are required. ibm powernp np2g preliminary network processor np2_ds_sec04_ieds.fm.01 february 12, 2003 ingress enqueuer / dequeuer / scheduler page 133 of 539 table 4-1. flow control hardware facilities name definition access bcb free queue (bcb_fq) control block register provides an instantaneous count of the nu mber of free buffers available in the ingress data store. cab bcb_fq threshold for guided traffic threshold for bcb_fq. when bcb_fq < bcb_fq_gt_th, no further buffers are allocated for incoming data. cab bcb_fq_threshold_0 threshold for bcb_fq. when bcb_fq < bcb_fq_threshold_0, no further buffers are allocated for incoming user traffic. gu ided traffic can still allocate new buffers. when this threshold is violated, an inte rrupt (class 0, bit 0) is signaled. a second threshold (bcb_fq_th_0_sa) can be configured which the bcb_fq must be exceeded before buffers will start being al located again for incoming user traffic after the bcb_fq has dropped below the bcb_fq_threshold_0 value (see bcb_fq_threshold_0 register (bcb_fq_th_0) on page 456). cab bcb_fq_threshold_1 threshold for bcb_fq. when bcb_fq < bcb_fq_threshold_1, no further buffers are allocated for new incoming user traffic. guided traffic and packets already started can still allocate new buffers. when this thres hold is violated, an interrupt (class 0, bit 1) is signaled. a second threshold (bcb_fq_th_1_sa) can be configured which the bcb_fq must be exceeded before buffers will start being allocated again for new incoming user traffic after the bcb_fq has dropped be low the bcb_fq_threshold_0 value (see bcb_fq_threshold_0 register (bcb_fq_th_0) on page 456). cab bcb_fq_threshold_2 threshold for bcb_fq. when bcb_fq < bcb_fq_threshold_2, an interrupt (class 0, bit 2) is signaled. cab flow control ingress free queue threshold (fq_p0_th) threshold for bcb_fq used when determining flow control actions against priority 0 traffic. when bcb_fq < fq_p0_th, the fl ow control hardware discards the frame. cab flow control ingress free queue threshold (fq_p1_th) threshold for bcb_fq used when determining flow control actions against priority 1 traffic. when bcb_fq < fq_p1_th, the fl ow control hardware discards the frame. cab bcb fq arrival count arrival rate of data into the ingress data store. this counter increments each time there is a dequeue from the bcb free queue. when read by picocode via the cab, this counter is set to 0 (read with reset). cab ingress free queue count exponentially weighted moving average calculated ewma of the bcb fq (bcb_fq_ewma). cab flow control ingress free queue threshold (fq_sbfq_th) threshold for bcb_fq. when bcb_fq < fq _sbfq_th, the i_freeq_th is set to 1. this may be used by external dev ices assisting in flow control. cab unicast/multicast status 0 threshold status of the priority 0 tdmu queues and the multicast queue. the count and the threshold are compared for each dmu. the results are combined into a sin- gle bit result. if tdmu_qcb.qcnt > tdmu_qcb.th, the bit is set to 1; if not, it is set to 0. cab egress status 0 this 1-bit register contains the congestion status of the egress data stores. the con- gestion status is the result a compar ison between the configured threshold and the ewma of the offered rate of priority 0 traffic (see table 6-1: flow control hardware facilities on page 148). hard- ware only egress status 1 this 1-bit register contains the congestion status of the egress data stores. the con- gestion status is the result a compar ison between the configured threshold and the ewma of the offered rate of priority 1 traffic (see table 6-1: flow control hardware facilities on page 148). hard- ware only ibm powernp np2g network processor preliminary ingress enqueuer / dequeuer / scheduler page 134 of 539 np2_ds_sec04_ieds.fm.01 february 12, 2003 4.3.2 hardware function 4.3.2.1 exponentially weighted moving average (ewma) the hardware generates ewma values for the bcb_fq count, thus removing the burden of this calculation from the picocode. in general, ewma for a counter x is calculated as follows: ewma_x = (1 - k) * ewma_x + k * x this calculation occurs for a configured sample period and k {1, 1/2, 1/4, 1/8}. 4.3.2.2 flow control hardware actions when the picocode enqueues a packet to be transmitted to the egress side, the flow control hardware exam- ines the state of the fq_p0_th and fq_p1_th threshold statuses and the priority of the enqueued packet to determine what flow control action is required. if the fcinfo field of the fcbpage of the enqueued packet is set to x?f?, flow control is disabled and the packet is forwarded. for priority 0 packets, egress status 0 is exceeded, the packet is discarded (tail drop discard). the pico- code must set up a counter block to count these discards. for priority 1 packets, if fq_p1_th is exceeded, th e packet is discarded (tail drop discard). otherwise, the transmit probability table is ac cessed and the value obtained is compared against a random number ( {0 ...1}) generated by the hardware. when the trans mit probability is less than the random number, the packet is discarded. the index into the transmit probability table is qqqtcc, where: qqq quality of service (qos) class taken from th e dscp (ingress fcbpage tos field bits 7:5). t egress status; one bit corresponding to the egress congestion (zero when the frame is multicast). cc diffserv code point (dscp) assigned color (ingress fcbpage fcinfo field bits 1:0). ibm powernp np2g preliminary network processor np2_ds_sec05_iew.fm.01 february 12, 2003 ingress-to-egress wrap page 135 of 539 5. ingress-to-egress wrap the ingress-to-egress wrap (iew) provides an interface to connect the ingress side of the np2g to the egress side. it supports 3.25 to 4 gigabits per second (g bps) throughput. an arbiter sits between the ingress cell data mover (i-cdm) and ingress cell interface (i-ci). the arbiter directs the data traffic from the i-cdm and probe to the i-ci. figure 5-1 shows the main functional blocks of the iew. the iew supports the following: building a cell header and fr ame header for each frame segmenting a frame into 64-byte cells cell packing the main units, described in following sections, are: ingress cell data mover (i-cdm) ingress cell interface (i-ci) egress cell interface (e-ci) egress cell data mover (e-cdm) 5.1 ingress cell data mover the ingress cell data mover (i-cdm) is the logical interface between the ingress enqueuer / dequeuer / scheduler?s (eds) frame data flow and the iew?s cell da ta flow. the i-cdm segments the frames into cells and passes the cells to the i-ci. the i-cdm also provides the following frame alteration functions: vlan insert or overlay. the four bytes comprising the vlan type field (x?8100?) and the tag control field are placed after the 12th byte of the frame. n-byte delete. bytes may be deleted from the incoming frame prior to being sent to the egress side. the ingress eds controls the i-cdm data input by requesting the i-cdm to transmit data to the egress side. to do this, the ingress eds gives the i-cdm the control information necessary to transmit one segment (either 48 or 58 bytes) of data from the selected frame. the control information consists of a buffer control block (bcb) address, frame control block (fcb) record contents, and the bcb address of the next frame of figure 5-1. ingress-to egress wrap functional blocks i-ci arb e-ci e-cdm from ingress eds to egress eds i-cdm probe ibm powernp np2g network processor preliminary ingress-to-egress wrap page 136 of 539 np2_ds_sec05_iew.fm.01 february 12, 2003 the same priority (used for packing). with this information, the i-cdm builds a cell under a quadword-aligned format compatible with the data structure in the egress data store. the logical cell structure contains three fields: cell header, frame header, and data. the first cell of a frame contains a cell header, a frame header, and 48 bytes of frame data. following cells of a frame contain a cell header followed by 58 bytes of frame data. the final cell of a frame contains the cell header, remaining bytes of frame data, and any necessary bytes to pad out the remainder of the cell. to increase the effective bandwidth through the iew, the network processor implements frame packing where the remaining bytes of a final cell contain the frame header and beginning bytes of the next frame. packing is used with unicast frames when the priority of the next frame is the same as the priority of the preceding frame. in this case, the packed cell contains a 6-byte cell header, the remaining data bytes of the first frame, a 10-byte frame header of the second frame, and some data bytes of the second frame. packing of frames occurs on 16-byte boundaries within a cell. to complete the logical cell, the i-cdm assembles control information from the fcb that was sent from the ingress eds, and utilizes data bytes read from the ingress data store buffers. logical cells are passed to the i-ci using a grant handshake. 5.1.1 cell header a cell header is a 6-byte field holdin g control information for the cell. a cell header is sent with each cell through the iew. figure 5-2 illustrates the forma t of a cell header; table 5-1 on page 137 provides the field definitions. figure 5-2. cell header format byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 r r r qt correlator endptr r st ucnmc reserved ibm powernp np2g preliminary network processor np2_ds_sec05_iew.fm.01 february 12, 2003 ingress-to-egress wrap page 137 of 539 table 5-1. cell header fields field name definition notes ucnmc unicast - multicast indicator. this 1-bit field indicates the format of the frame carried in this cell. ?0? multicast format. guided traffic must be sent in multicast format. ?1? unicast format. 1 st(1:0) frame state indicator (2-bit field). pr ovides information about the status of the frame currently being carried in the cell. 00 continuation of current frame (the cell contains a middle portion of a frame, but no start or end of a frame) 01 end of current frame. this code point must be us ed when the cell format va lue is '11' (packed frame format). (the cell contains the end of frame if ?frame format? is indicated by the cell format value, or the end of one frame and the beginning of another fr ame if ?packed frame format? is indicated.) 10 start of new frame (the cell contains the start of a frame, but no end of a frame) 11 start and end of new frame. used for frames 48 bytes or smaller. this code point is also used to indi- cate a reassembly abort command. a bort is indicated when the end pointer field value is ?0?. an aborted frame is discarded by the e-eds. at the point of reassembly, cells for a frame are expected to follow a star t, continuation (may not be present for short frames) and end sequence. hardware in the e- eds detects when this sequence is not followed and reports these errors in the reasse mbly sequence error count register. frames with reassembly sequence errors are discarded. correlator correlator values 0 - 63 are us ed for unicast traffic. correlator values 0- 31 are used for multicast traffic. 1 qt(1:0) queue type (2-bit field). used to determine the required handling of the cell and the frame. bits 1:0 description 0x user traffic that is enqueued into a data queue (grx or gbx). 1x guided traffic that is enqueued into the guided frame queue. x0 cell may be dropped due to congestion. x1 cell may not be dropped due to congestion. qt(0) is set to 1 by the iew hardware when fc info field of the frame header is set to x?f?. endptr end pointer (6-bit field). the endptr fi eld is a byte offset within the cell which indicates the location of the last data byte of the current frame in the cell when the st field indicates end of current frame (st = ?01? or ?11?). valid values of the endptr field are in the range of 6 through 63. an endptr value of 0 is used only with an st value of '11' to indicate an abort comma nd. values of 1 through 5 are reserved. in all other cases (st = ?00? or ?10? ), this field contains sequence checking informatio n used by the frame reas- sembly logic in the network processor. the sequence checking information consis ts of a sequence number placed into this field. the first cell of a frame is assigned a sequence number of 0. in a pack ed cell, the sequence number is not placed into the endptr field since the field must cont ain the end pointer for the preceding fram e; the next cell fo r this frame will contain a sequence number of 1. s equence numbers increment from 0 to 63 and will wrap if necessary. r reserved field, transmitted as ?0?. 1. this field is used by the egress reassembly l ogic in selection of the reassembly control block. ibm powernp np2g network processor preliminary ingress-to-egress wrap page 138 of 539 np2_ds_sec05_iew.fm.01 february 12, 2003 5.1.2 frame header a frame header is a 10-byte field containing control information used in egress processing and is sent once per frame. a frame header can immediately follow the cell header, or with packing enabled, it can also be placed at the start of the 2nd (d10), 3rd (d26), or 4th (d42) qw of the cell. figure 5-3 illustrates the format of a frame header; table 5-2 on page 139 provides the field definitions. figure 5-3. frame header format 1. see description of the correlator field in frame header fields on page 139. r r byte 0 byte 1 byte 2 fhe(31:8) byte 6 byte 7 byte 8 fhe(7:0) byte 9 stake (7:6) mc uc mc uc (1:0) lid stake(5:0) mid(16:0) lid(20:2) sp byte 4 byte 5 byte 3 correlator 1 (overwritten) dsu ucnmc fhf fc info ibm powernp np2g preliminary network processor np2_ds_sec05_iew.fm.01 february 12, 2003 ingress-to-egress wrap page 139 of 539 5.2 ingress cell interface the ingress cell interface (i-ci) performs formatting on the cell headers to conform with the cell format previ- ously defined. the i-ci unit relies on an internal fifo buffer (written by the i-cdm at the network processor core clock rate and read at the iew clock rate). table 5-2. frame header fields field name description notes ucnmc unicast - multicast indicator. this 1-bit field indicates the format of the frame header. ?0? multicast format. ?1? unicast format. 1 fc info flow control information (4-bit field). indicates the type of connection used for this frame. connection type encoding is used by the np2g?s flow control mechanisms. 2 lid lookup identifier (21 bit field). used by the egress processing to locate the necessary information to forward the frame to the appropriate target port with the correct qos. 3 mid multicast identifier (17 bit field). used by the egress pr ocessing to locate the multicast tree information which is used to forward the frame to the appropr iate target ports with the correct qos. 3 stake available only for the multicast format of the frame header. this 8-bit field is used by egress processing to locate the start of the layer 3 header. 3 dsu dsu indicator. available only for t he unicast format of the frame header. this 4-bit field indicates which egress data stores are used by this frame when toggle mode is disabled (see 13.2 toggle mode register on page 444). defined as follows (where ?r? indicates a reserv ed bit that is transmitted as ?0? and is not modified or checked on receipt): 0rr0 data store 0 0rr1 data store 1 1rr0 data store 0 and data store 1 1rr1 data store 0 and data store 1 fhf frame header format. software controlled field. this fiel d, with the addition of the uc field, is used by the hardware classifier in the epc to determine the code ent ry point for the frame. the uc field and the fhf form a 5-bit index into a configurable lookup table of code entry points used for egress processing. sp source port of the frame. fhe frame header extension (32-bit field) . used by ingress processing to pass information to egress processing. the contents of this field depend on the fhf value used by egress processing to interpret the field. informa- tion passed reduces the amount of frame parsing r equired by egress processing when determining how to forward the frame. r reserved field, transmitted as ?0?. correlator correlator values 0-63 are used for unicast traffi c. correlator values 0-31 ar e used for multicast traffic. 1. this field is used by egress reassembly logic in selection the reassembly control block. it is also used by the hardware clas sifier. 2. this field is passed through the ingress flow control before the frame is enqueued for transmission through the iew. it can b e used by software to allow the hardware to make further flow cont rol decisions on egress by passing connection information (type and dscp). 3. this field is passed by the hardware but is defined and used by the software. ibm powernp np2g network processor preliminary ingress-to-egress wrap page 140 of 539 np2_ds_sec05_iew.fm.01 february 12, 2003 5.3 egress cell interface the egress cell interface (e-ci) receives cells from the iew and passes data cells to the egress cell data mover (e-cdm). the e-ci assists in egress data flow control by throttling the ingress traffic to prevent data overruns. it does this by passing the egress congestion status back to the ingress scheduler. 5.4 egress cell data mover the egress cell data mover (e-cdm) is the logical interface between the cell data flow of the e-ci and the frame data flow of the egress eds. the e-cdm serves as a buffer for cells flowing from the e-ci to the egress eds. the e-cdm extracts control information, such as the frame correlator, which is passed to the egress eds. the egress eds us es this control information, along with data from the e-cdm, to re-assemble the cells into frames. ibm powernp np2g preliminary network processor np2_ds_sec06_eeds.fm.01 february 12, 2003 egress enqueuer / dequeuer / scheduler page 141 of 539 6. egress enqueuer / dequeuer / scheduler the egress enqueuer / dequeuer / scheduler (egres s eds) interfaces with the physical mac multiplexer (pmm), the embedded processor complex (epc), and the ingress-to-egress wrap (iew). it is responsible for handling all the buffer, frame, and queue management for reassembly and transmission on the egress side of the network processor. the egress eds reassembles data that have been transported from the ingress side. each cell received from the iew is examined and stored in the appropriate egress data store (egress ds) for reassembly into its original frame. when the frame is completely received from the iew, the egress eds enqueues it to the epc for processing. once the epc processes the frame, it provides forwarding and quality of service (qos) information to the egress eds. the egress eds then invokes hardware configured flow control mechanisms and then enqueues it to either the scheduler, when enabled, or to a target port (tp) queue for transmission to the egress pmm (which, in turn, sends th e data to physical layer devices). the egress eds supports the following functions, as illustrated in figure 6-1 on page 142: external egress data store automatic allocation of buffer and frame control blocks for each frame epc queues (gfq, gtq, gr0, gr1, gb0, gb1, and gpq) target port queues with two priorities buffer thresholds and flow control actions bandwidth and best effort scheduling reading and writing of frame data stored in egress data store up to 512 k buffer twins depending on memory configuration up to 512 k of frame control blocks (fcbs) depending on memory configuration unicast and multicast frames cell packing up to 21 external ports plus wrap port interface to the pmm discard function hardware initialization of internal and external data structures ibm powernp np2g network processor preliminary egress enqueuer / dequeuer / scheduler page 142 of 539 np2_ds_sec06_eeds.fm.01 february 12, 2003 6.1 functional blocks figure 6-1 illustrates the functi onal blocks of the egress eds. the list fo llowing the figure explains each func- tional block. figure 6-1. egress eds functional blocks e data store interface writes the external egress ds during frame reassembly and reads them during frame transmission. also gives the epc access to the egress ds. the data store interface supports two external data stores: ds0 and ds1. dpq discard port queue. releases twin buffers back to the free queue stack. the pico- code uses this queue to discard frames where header twins have been allocated. e-gdq discard queue stack. holds frames that need to be discarded. the hardware uses this queue to discard frames when the egress ds is congested or to re-walk a frame marked for discard for a half-duplex port. the picocode uses this queue to discard frames that do not have header twins allocated. egress pcb egress port control block. contains the necessary information to send a frame to the egress pmm for transmissi on. the egress eds uses this information to walk the twin buffer chain and send the data to the egress pmm?s output port. there is a pcb entry for each target port, plus one for discard and one for wrap. each entry holds information for two frames: the current frame being sent to the pmm port and the next frame to be sent. data store interface egress pcb rcb release logic mcc tables flow control wrapq dpq tp39q_p1 tp0q_po gb1 gb0 gr1 gr0 gtq gfq fqs egress pmm epc e-gdq ds gpq fcbfq scheduler iew ibm powernp np2g preliminary network processor np2_ds_sec06_eeds.fm.01 february 12, 2003 egress enqueuer / dequeuer / scheduler page 143 of 539 fcbfq frame control block free queue. lists free egress fcbs. fcbs store all the infor- mation needed to describe the frame on the egress side, such as starting buffer, length, mcc address, frame alteration, and so on. the egress eds obtains an fcb from the free queue when the epc enqueues the frame to either a flow qcb (see flow queues on page 155) or a tp after epc processing and flow control actions are complete. fqs free queue stack. holds a list of free egress twin buffers which are used by the egress eds during frame reassembly and by the epc during frame alteration. the twin buffers store the frame data or frame alteration header twins and also contain the link pointer to the next buffer in the chain. the fqs obtains a new free twin buffer any time the egress eds needs one and returns free twin buffers after frames are discarded or transmitted. gb0, gb1 low priority data queues. gb0 is for frames stored in egress ds0. gb1 is for frames stored in egress ds1. gfq guided frame queue. queue that contains guided frames for delivery for the egress side of the network processor to the guided frame handler. gpq powerpc queue. queue that contains frames re-enqueued for delivery to the general powerpc handler (gph) thread for processing. gr0, gr1 high priority data queues. gr0 is for frames stored in egress ds0. gr1 is for frames stored in egress ds1. gtq general table queue. queue that contains guided frames re-enqueued by pico- code for delivery to the general table handler (gth) thread. mcc table multicast count table. each entry stores the number of multicast frames associ- ated with a particular set of twin buffers. if a frame is to be multicast to more than one target port, the epc enqueues the frame to each target port, causing an entry in the mcc table to be incremented. as each target port finishes its copy of the frame, the mcc table entry is decremented. when all ports have sent their copies of the frame, the associated twin buffers are released. rcb reassembly control block. used by the egress eds to re assemble the cells received from the ingress side into their original frames. contains pointers to the egress ds to specify where the contents of the current cell should be stored. helps the egress eds keep track of the frame length and which epc queue to use. release logic releases twin buffers after the pmm has finished with the contents of the buffer. the release logic checks the mcc table to determine if the buffer can be released or is still needed for some other copy of a multicast frame. tp0q - tp39q target port queues. hold linked lists of frames destined for a tp. two queues are associated with each of the 21 possible tps. these queues are prioritized from high (p0) to low (p1) using a strict priority service scheme (all higher priority queues within a target port set must be empty before starting a lower priority queue). ibm powernp np2g network processor preliminary egress enqueuer / dequeuer / scheduler page 144 of 539 np2_ds_sec06_eeds.fm.01 february 12, 2003 6.2 operation the egress eds receives cells from the ingress-to-egress wrap (iew) along with information that has been preprocessed by the egress cell data mover (cdm) such as the reassembly correlator, multicast indication, priority, and target data store (ds). the two egress dss, ds0 and ds1, use alternating write windows, meaning the egress eds can write one cell to one data store each ?cell window time? (the time needed to store an entire cell (64 bytes) in external dram). ce ll window time is configured using the dram parameter register?s 11/10 field. the egress eds reads the cell data out of the cdm and uses the reassembly correlator, multicast indica- tion, and priority information to index into the reas sembly control block (rcb). the rcb contains all the information needed to reassemble the frame, including the buffer address to use in the egress ds. the cell data is stored in the buffer and the rcb is updated to prepare for the next cell associated with the same frame. the egress eds manages 192 rcb entries, and each entry contains information such as start-of- frame indicator, data store buffer address, current reassembled frame length, and queue type. the egress eds uses the rcb information to rebuild each frame. the egress eds uses a free buffer from the head of the free queue stack (fqs) as needed to store frame data in the egress ds. the egress eds stores the cell data in the appropriate buffer and also stores the buffer chaining information over the cell header data. when a packed cell arrives, the egress eds stores each frame?s information in two separate twin buffers. the first portion of the packed cell contains the end of a frame. this data is stored in the appropriate twin buffer as pointed to by the rcb. the remaining portion of the packed cell is the beginning of another frame and this data is stored in a second twin buffer as indicated by the second frame?s rcb entry. figure 6-2 illustrates the cell buffers and storage in an egress ds. wrapq wrap queue. two wrap queues, one for guided frames and one for data frames, send frames from the egress side to the ingress side of the network processor. these queues are typically used for debug or diagnostic purposes. ibm powernp np2g preliminary network processor np2_ds_sec06_eeds.fm.01 february 12, 2003 egress enqueuer / dequeuer / scheduler page 145 of 539 when the entire frame is reassembled, the egress eds enqueues it to one of several epc queues. if the reassembled frame is a guided frame, the egress eds uses the gfq. high priority frames are placed in either the gr0 or the gr1. low priority frames are placed in either the gb0 or the gb1. the epc services these queues and requests a programmable amount of read data from the various frames in order to process them (see table 7-84: port configuration memory content on page 262). the egress eds reads the data from the egress data store and passes it back to the epc. additional reads or writes can occur while the epc is processing the frame. the egress eds performs all necessary reads or writes to the egress data store as requested by the epc. when the frame has been processed, the epc enqueues the frame to the egress eds. if the frame?s destina- tion is the general table handler (gth), the egress eds enqueues the frame to the gtq. if the frame is to figure 6-2. cell formats and storage in the egress ds ch 1 (0:5) fh 1 (0:9) fd 1 (00:15) fd 1 (16:31) fd 1 (32:47) ch 1 (0:5) fh 1 (0:9) fd 1 (00:15) fd 1 (16:31) fd 1 (32:47) ch 1 (0:5) fd 1 (48:57) fd 1 (58:73) fd 1 (74:89) fd 1 (90:105) lp 1 (0:5) fd 1 (48:57) fd 1 (58:73) fd 1 (74:89) fd 1 (90:105) fqs fqs ch 2 (0:5) fd 2 (22:31) fd 2 (32:47) fd 2 (48:63) fd 2 (64:79) lp 2 (0:5) fd 2 (22:31) fd 2 (32:47) fd 2 (48:63) fd 2 (64:79) ch 1 (0:5) fd 1 (106:115) fd 1 (116:120) fh 2 (0:9) fd 2 (00:05) fd 2 (06:21) ch 1 (0:5) fd 1 (106:115) fd 1 (116:120) na (0:10) fh 2 (0:9) fd 2 (00:05) fd 2 (06:21) 128-byte linked twin buffers for frame 1 128-byte linked twin buffers for frame 2 non-packed start of frame cell non-packed continuation cell packed end of frame cell non-packed continuation cell ch = cell header fh = frame header fd = frame data lp = link pointer na = unused bytes data buffer data buffer twin buffer ibm powernp np2g network processor preliminary egress enqueuer / dequeuer / scheduler page 146 of 539 np2_ds_sec06_eeds.fm.01 february 12, 2003 be discarded, it is placed in the dpq. if the frame needs to be wrapped to the ingress side, it is placed in the wrap queue (if the scheduler is disabled) or into a qc b configured for wrap traffic. all other frames are subject to flow control actions. if flow control does no t discard the frame, the frame is placed into the sched- uler, if enabled, or placed directly into a target port q ueue. each target port supports two priorities and there- fore has two queues. the epc indicates which target port and which priority should be used for each frame enqueued. the two queues per port use a strict priority sc heme, which means that all high priority traffic must be transmitted before any lower priority traffic will be sent. frames destined for the scheduler, target ports, or wrap ports have a frame control block (fcb) assigned by the egress eds. the fcb holds all the information needed to transmit the frame including starting buffer address, frame length, and frame alteration inform ation, as illustrated in figure 6-3 . if the epc needs to forward more than one copy of the frame to different target ports, an entry in the mcc table is used to indi- cate the total number of copies to send. the epc enqueues the frame to different target ports or different flow qcbs and each enqueue creates a new fcb with (possibly) its own unique frame alteration. figure 6-3. tpq, fcb, and egress frame example target port queues frame control blocks target port 5 target port 9 multicast frame last frame in target port queue 5 first frame in target port queue 9 unicast frame last frame in target port queue 9 unicast frame first frame in target port queue 5 h c = 2 t h c = 2 t fba fl = y fba fl = y fba fl = x fba fl = z h = head t = tail c = queue count fba = first buffer address fl = frame length buf = buffer lp = link pointer frame length = x bytes frame length = y bytes frame length = z bytes buf 32 buf 12 buf 3 buf 9 buf 7 buf 23 buf 15 buf 39 buf 99 lp = 9 lp = 15 lp = 23 lp = 39 lp = 99 lp = 7 ibm powernp np2g preliminary network processor np2_ds_sec06_eeds.fm.01 february 12, 2003 egress enqueuer / dequeuer / scheduler page 147 of 539 when a frame reaches the head of a target port queue, it is placed in the egress port control block (pcb) entry for that port and the fcb for that frame is plac ed on the fcb free queue. the egress eds uses the pcb to manage frames being sent to the pmm for tr ansmission. the pcb stores information needed to retrieve frame data, such as current buffer address and frame length, from the egress ds. the pcb allows up to 21 frames to be retrieved simultaneously from the egress ds. the pcb also supports the wrap port and the discard port queue. as data is retrieved from the egress ds and passed to the pmm, the pcb moni- tors transfers and stores buffer link pointers that enable the pcb to walk the buffer chain for the frame. when the entire buffer chain has been traversed, the pcb entry is updated with the next frame for that target port. as the pmm uses the data from each buffer, it passes the buffer pointer back to the release logic in the egress eds. the release logic examines the mcc table entry to determine if the buffer should be returned to the fqs. (half-duplex ports will not have their t win buffers released until th e entire frame has been trans- mitted, in order to support the reco very actions that are necessary when a collision occurs on the ethernet media.) if the mcc entry indicates that no other copies of this frame are needed, the buffer pointer is stored in the fqs. however, if the m cc entry indicates that other copies of this frame are still being used, the egress eds decrements the mcc entry, but does no further action with this buffer pointer. the dpq contains frames that have been enqueued for discard by the epc and by the release logic. the hardware uses the dpq to discard the last copy of frames transmitted on half duplex ports. the dpq is dequeued into the pcb?s discard entry, where the frame data is read from the ds to obtain buffer chaining information necessary to locate all twin buffers of the frame and to release these twin buffers back to the free pool (fqs). 6.3 egress flow control flow control (whether to forward or discard frames) in the network processor is provided by hardware assist mechanisms and picocode that implements a selected fl ow control algorithm. in general, flow control algo- rithms require information about the congestion state of the data flow, including the rate at which packets arrive, the current status of the data store, and so on. a transmit probabilit y for various flows is an output of these algorithms. the network processor implements flow control in two ways: flow control is invoked when the frame is enqueued to either a target port queue or a flow queue control block (qcb). the hardware assist mechanisms use the trans mit probability along wi th tail drop conges- tion indicators to determine if a forwarding or discard action should be taken during frame enqueue oper- ation. the flow control hardware uses the picocode?s entries in the egress tran smit probability memory to determine what flow control actions are required. flow control is invoked when frame data enters the network processor. when the egress ds is suffi- ciently congested, these flow control actions discard all frames. the threshold that controls the invocation of these actions is fq_es_threshold_0 (see table 6-1: flow control hardware facilities on page 148 for more information). 6.3.1 flow control hardware facilities the hardware facilities listed in table 6-1 are provided for the picocode's use when implementing a flow control algorithm. the picocode uses the information from thes e facilities to create entries in the egress transmit probability memory. the flow control hardware uses these entr ies when determining what flow control actions are required. ibm powernp np2g network processor preliminary egress enqueuer / dequeuer / scheduler page 148 of 539 np2_ds_sec06_eeds.fm.01 february 12, 2003 table 6-1. flow control hardware facilities (page 1 of 2) name definition access free queue count instantaneous count of the number of fr ee twins available in the egress data store. cab fq_es_threshold_0 threshold for free queue count. when the fr ee queue count < fq_es_threshold_0, no further twins are allocated for incoming data. us er packets that have st arted reassembly are discarded when they receive data when this thresh old is violated. guided traffic is not dis- carded. the number of packets discarded is counted in the reassemb ly discard counter. when this threshold is violated, an in terrupt (class 0, bit 4) is signaled. cab fq_es_threshold_1 threshold for free queue count. when the fr ee queue count < fq_es_threshold_1, an interrupt (class 0, bit 5) is signaled. cab fq_es_threshold_2 threshold for free queue count. when the fr ee queue count < fq_es_threshold_2, an interrupt (class 0, bit 6) is signaled, and if enabled by dmu configuration, the ethernet mac preamble is reduced to 6 bytes. cab arrival rate counter the arrival rate of data into the egress data store. this counter increments each time there is a dequeue from the twin free queue. when read by picocode via the cab, this counter is set to 0 (read with reset). cab fq count ewma the calculated ewma of the free queue count. cab p0 twin count the number of twins in priority 0 packets that have been enqueued to flow queues, but have not been dequeued from target port queues. cab p1 twin count the number of twins in priority 1 packets that have been enqueued to flow queues, but have not been dequeued from target port queues. cab p0 twin count threshold threshold for p0 twin count. it is used when de termining flow control actions against priority 0 traffic. when p0 twin count > p0 twin count threshold, the flow control hardware will discard the frame. cab p1 twin count threshold threshold for p1 twin count. it is used when de termining flow control actions against priority 1 traffic. when p1 twin count > p1 twin count threshold, the flow control hardware will discard the frame. cab egress p0 twin count ewma the calculated ewma based on the count of the number of twins allocated to p0 traffic dur- ing the sample period. hardware maintains a count of the number of twins allocated to p0 traffic at enqueue. cab egress p1twin count ewma the calculated ewma based on the count of the number of twins allocated to p1 traffic dur- ing the sample period. hardware maintains a count of the number of twins allocated to p1 traffic at enqueue. cab egress p0 twin count ewma threshold the congestion status of the egress data store. it is the result of a comparison between this configured threshold and the ewma of the offered rate of priority 0 traffic (p0 twin count ewma > p0 twin count ewma threshold). this information is trans mitted to the ingress side via the res_data i/o and is collected in the status 0 register in t he ingress flow control hardware. cab ibm powernp np2g preliminary network processor np2_ds_sec06_eeds.fm.01 february 12, 2003 egress enqueuer / dequeuer / scheduler page 149 of 539 6.3.2 remote egress status bus the remote egress status (res) bus communicates the congestion state of the egress data stores to the ingress flow control. the ingress portion of each np2g can then preemptively discard frames to reduce consumption of egress bandwidth. 6.3.2.1 bus sequence and timing the res bus passes status information from the egress side of the np2g back to the ingress side. it consists of a data signal (res_data) and a synchronous signal (res_sync), both of which can be monitored by external logic. figure 6-4 on page 149 shows a timing diagram of the operation of the res bus. figure 6-4 illustrates the timings used for res_sync and res_data. res_sync is shown positive active (the falling transition is used to determine where the res_ data bus sequence starts). the res bus operates on the same clock frequency as the internal iew clock. this clock period can range from 8 ns to 10 ns. however, the res bus cloc k is not necessarily in phase with the iew clock. egress p1 twin count ewma threshold the congestion status of the egress data store. it is the result of a comparison between this configured threshold and the ewma of the offered rate of priority 0 traffic. (p1 twin count ewma > p1 twin count ewma threshold). this information is transmitted to the egress side via the res_data i/o and is collected in the status 1 register in the i ngress flow control hard- ware. cab target port th_pq+fq target port port queue plus egress scheduler (f low qcb) threshold. the target port queues maintain a count of the number of twins allocate d to the target port. the count is incremented on enqueue (after flow control transmit action is taken) and decremented on dequeue from the target port. thresholds for each priority c an be configured for all ports. when the number of twins assigned to a target port queue exceeds t he threshold, its threshold exceed status is set to 1. the status is used to index into t he transmit probability memory for packets going to the target port. cab qcb threshold flow queue threshold. when the number of twin s assigned to this flow queue exceeds this threshold, the threshold exceed status is set to 1. the status is used to index into the trans- mit probability memory. cab figure 6-4. res bus timing table 6-1. flow control hardware facilities (page 2 of 2) name definition access res_sync res_data reserved reserved zp0p1 reserved reserved 1 2 3 4 8 iew cycles sampling points active transition z ibm powernp np2g network processor preliminary egress enqueuer / dequeuer / scheduler page 150 of 539 np2_ds_sec06_eeds.fm.01 february 12, 2003 the np2g puts four values on the res_ data signal. each value is held for eight iew clock cycles. therefore, each np2g time slot is 32 iew clock cycles. the pr otocol for sending the conge stion information is as follows: 1. high-z . the np2g keeps its res_data line in high imped ance for eight iew clock cycles. this allows the bus to turn around from one np2g to another. 2. p0 . the np2g drives its priority 0 (p0) egress data store congestion information for eight iew clock cycles. congestion is indicated when the egress p0 twin count ewma register value is greater than the egress p0 twin count ewma threshold register value. 3. p1 . the np2g drives its priority 1 (p1) egress data store congestion information for eight iew clock cycles. congestion is indicated when the egress p1 twin count ewma register value is greater than the egress p1 twin count ewma threshold register value. 4. reserved . the np2g drives a low value for eight iew clock cycles. this is reserved for future use. the ingress flow control samples res_data during the midpoint of its eight iew clock cycles. the res_sync signal is driven to its active state during the reserved cycle of the last time slot. the res_sync signal has a period equal to 512 iew clock periods. 6.3.2.2 configuration the res bus is activated by enabling the ingress and eg ress functions of the internal res data logic via the res_bus_configuration_en register. three bits in this register enable different functions: the i_res_data_en bit enables the ingress logic to capture the res_data. the e_res_data_en bit enables the egress logic to send its status on res_data. the e_res_sync_en bit enables the np2g to drive res_sync. ibm powernp np2g preliminary network processor np2_ds_sec06_eeds.fm.01 february 12, 2003 egress enqueuer / dequeuer / scheduler page 151 of 539 6.3.3 hardware function 6.3.3.1 exponentially weighted moving average the hardware generates exponentially weighted moving average (ewma) values for the free queue count and the p0/p1 twin counts, thus removing the burden of this calculation from the picocode. in general, ewma for a counter x is calculated as follows: ewma_x = (1 - k) * ewma_x + k * x this calculation occurs for a configured sample period and k {1, 1/2, 1/4, 1/8}. 6.3.3.2 flow control hardware actions when the picocode enqueues a packet to be transmitted to a target port, the flow control logic examines the state of the target port th_pq+fq, and the priority of the enqueued packet to determine if any flow control actions are required. if the fcinfo field of the fcbpage of the enqueued packet is set to x?f?, flow control is disabled and the packet is forwarded without regard to any of the congestion indicators. for priority 0 packets, if target port th_pq+fq or p0 twin count threshold is exceeded, then the packet is discarded. the picocode must set up a counter block to count these discards. for priority 1 packets, if p1 twin count threshol d is exceeded, then the packet will be discarded. other- wise the transmit probability found in the qcb (availa ble only when the scheduler is enabled) and the transmit probability table are access ed. the smaller of thes e values is compared against a random num- ber ( { 0 ... 1} ) generated by the hardware. when the tr ansmit probability is zero or is less than the ran- dom number, the packet is discarded. the picocode must set up a counter block to count these discards. the index into the transmit probability table is ttccfp, where: tt packet type (egress fcbpage fcinfo field bits 3:2). cc dscp assigned color (egress fcbpage fcinfo field bits 1:0) f threshold exceeded status of the target flow queue (qcb threshold exceeded) p threshold exceeded status of the target port queue (target port th_pq+fq exceeded) ibm powernp np2g network processor preliminary egress enqueuer / dequeuer / scheduler page 152 of 539 np2_ds_sec06_eeds.fm.01 february 12, 2003 6.4 the egress scheduler the egress scheduler provides shaping functions in th e network processor. the egress scheduler manages bandwidth on a per frame basis by determining the bandwid th a frame requires (that is, the number of bytes to be transmitted) and comparing this against the bandwidth permitted by the configuration of the frame?s flow queue. the bandwidth used by the first frame affects when the scheduler permits the transmission of the second frame of a flow queue. the egress scheduler c haracterizes flow queues with the parameters listed in table 6-2 . table 6-3 lists valid combinations of the parameters described in table 6-2 . figure 6-5 on page 153 presents a graphical representation of the egress scheduler. table 6-2. flow queue parameters parameter description low -latency sustainable bandwidth (lls) provides guaranteed bandwidth with qualitative latency reduction. lls has higher service prio rity than nls. flow queues connected to lls have bet- ter latency characteristics than flow queues connected to nls. normal-latency sustainable bandwidth (nls) provides guaranteed bandwidth. peak bandwidth service (pbs) provides addi tional bandwidth on a best-effort basis. queue weight allows the scheduler to assign available (t hat is, not assigned or currently not used by lls and nls) bandwidth to flow queues using best effort or pbs services. assignment of different ratios of the av ailable bandwidth is ac complished by assign- ing different queue weights to queues that share the same target port. table 6-3. valid combinations of scheduler parameters qos lls nls weight pbs low latency with guaranteed bw shaping x normal latency with guaranteed bw shaping x best effort x best effort with peak rate xx normal latency with guaranteed bw shaping and best effort xx normal latency with guaranteed bw shaping and best effort and peak rate xxx ibm powernp np2g preliminary network processor np2_ds_sec06_eeds.fm.01 february 12, 2003 egress enqueuer / dequeuer / scheduler page 153 of 539 figure 6-5. the egress scheduler 5 nls flow 0 flow 1 lls 511 0 511 0 511 511 flowid 0 flowid 511 0 511 0 511 511 flowid 0 wfq port 39 peak bandwidth service (pbs) 511 0 511 0 511 511 flowid 0 1 0 flow 2047 511 flowid 0 wfq port 0 511 0 3 1 2 4 2 1 3 discard wrap port 0 port 39 port 39 port 0 port 38 port 38 high-priority target port queues lo w-priority target port queues 4 ibm powernp np2g network processor preliminary egress enqueuer / dequeuer / scheduler page 154 of 539 np2_ds_sec06_eeds.fm.01 february 12, 2003 6.4.1 egress scheduler components the egress scheduler consists of the following components: scheduling calendars 2047 flow queues (flow qcb addresses 1-2047) and 2047 associated scheduler control blocks (scbs) target port queues discard queue wrap queue 6.4.1.1 scheduling calendars the egress scheduler selects a flow queue to service ev ery scheduler_tick. the duration of a scheduler_tick is determined by the configuration of the dram parameter register 11/10 field (bit 6 only). when this register field is set to 0, a scheduler_tick is 150 ns. when the field is set to 1, a scheduler_tick is 165 ns. there are three types of scheduling calendars used in t he egress calendar design: time-based, weighted fair queuing (wfq), and wrap. time-based calendars the time-based calendars are used for guaranteed bandwidth (lls or nls) and for peak bandwidth service (pbs). weighted fair qu euing calendars the wfq calendars allocate available bandwidth to co mpeting flows on a per-port basis. available bandwidth is the bandwidth left over after the flows in the time-based calendars get their bandwidth. a wfq calendar is selected for service only when no service is required by the time-based calendars and the target port queue does not exceed a programmable threshold. the use of this threshold is the method that assures the wfq calendar dequeues frames to the target port at a rate equal to the port's available bandwidth. wrap calendar the wrap calendar is a 2-entry calendar for flows that use the wrap port. calendar type selection algorithm selection among calendar types occurs each scheduler_tick based on the following priority list: 1. time-based lls 2. time-based nls 3. time-based pbs 4. wfq 5. wrap ibm powernp np2g preliminary network processor np2_ds_sec06_eeds.fm.01 february 12, 2003 egress enqueuer / dequeuer / scheduler page 155 of 539 6.4.1.2 flow queues there are 2047 flow queues (flow queue control block (qcb) addresses 1-2047) and scheduler control blocks. a flow qcb contains information about a single flow, as well as information that must be configured before the flow qcb can be used. configuring sustainab le bandwidth (ssd) the sustained service rate (ssr) is defined as the minimum guaranteed bandwidth provided to the flow queue. it is implemented using either the lls or nls calendars. the following transform is used to convert the ssr from typical bandwidth specifications to scheduler step units (ssd field in the qcb): ssd = (512 (bytes) / scheduler_tick (sec)) / sustained_service_rate (bytes/sec) the flow qcb ssd field is entered in exponential notation as x *16 y , where x is the ssd.v field and y is the ssd.e field . when an ssr is not specified, the flow qcb ssd field must be set to 0 during configuration. values of ssd that would cause the calendars to wr ap should not be specified. once the maximum frame size is known, ssd max can be bound by: ssd max 1.07 * (10e + 9) / maximum frame size (bytes) for best scheduler accuracy, the smallest value for ssd.e should be specified. in order to accomplish this, ssd.v min that shall be specified is: ssd.e ssd.v min comments 0 10 allows 2.4 gbps flow specification 1..3 32 an ssd value of 0 indicates that this flow queue has no defined guaranteed bandwidth component (ssr). configuring flow qcb fl ow control thresholds when the number of bytes enqueued in the flow queue exceeds the flow qcb threshold (th), the flow queue is congested. the flow control hardware uses th is congestion indication to select the transmit proba- bility. the following tr ansform is used to specify this threshold: th.v and th.e fields are components of the flow cont rol threshold field . a twin buffer contains approxi- mately 106 bytes. a th value of 0 disables threshold checking. th.e threshold value (units in twin buffers) 0 th.v * 2**6 1 th.v * 2**9 2 th.v * 2**12 3 th.v * 2**15 ibm powernp np2g network processor preliminary egress enqueuer / dequeuer / scheduler page 156 of 539 np2_ds_sec06_eeds.fm.01 february 12, 2003 configuring best effort service (qd) the queue weight is used to distribute available bandwidth among queues assigned to a port. the remaining available bandwidth on a port is distributed among contending queues in proportion to the flow?s queue weight. the following transform is used to convert the queue weight into scheduler step units (qd field in the qcb): qd = 1 / (queue weight) a qd of 0 indicates that the flow queue has no best effort component. configuring peak best effort bandwidth (psd) peak service rate is defined as the additional bandwidth that this flow queue is allowed to use (the difference between the guaranteed and the peak bandwidth). for example, if a service level agreement provided for a guaranteed bandwidth of 8 mbps and a peak bandwidth of 10 mbps, then the peak service rate is 2 mbps. the following transform is used to convert peak service rate from typical bandwidth specifications to sched- uler step units (psd field in the qcb): psd = (512 (bytes) / scheduler_tick (sec )) / peak_service_rate (bytes/sec) the flow qcb psd field is expressed in exponential notation as x *16 y , where x is the psd.v field and y is the psd.e field. a psd value of 0 indicates that th is flow queue has no peak service rate component. for best scheduler accuracy, the smallest value for psd.e should be specified. in order to accomplish this, psd.v min that shall be specified is: psd.e psd.v min 010 1..3 32 ta r g e t po r t the destination target port (tp) id. target port priority the target port priority (p) field selects either the low-latency sustainable bandwidth (lls) or normal-latency sustainable bandwidth (nls) calendar for the guaranteed bandwidth component of a flow queue. values of 0 (high) and 1 (low) select the lls or nls calendar respectively. during an enqueue to a tp queue, the p selects the correct queue. this field is also used in flow control. transmit probability flow control uses the transmit probab ility field. the picocode flow control algorithms u pdate this field periodi- cally. ibm powernp np2g preliminary network processor np2_ds_sec06_eeds.fm.01 february 12, 2003 egress enqueuer / dequeuer / scheduler page 157 of 539 6.4.1.3 target port queues there are 46 target port queues, including 21 target ports, a discard port, and a wrap port, each with two priorities. the scheduler dequeues frames from flow qcbs and places them into the target port queue that is designated by the flow qcb?s target port (tp) and priority (p) fields. a combination of a work-conserving round-robin and absolute priority selection services target port queues. the round-robin selects among the 21 media ports (target port ids 0, 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31, 34, 35, 38, and 39) within each priority class (high and low, as shown in figure 6-5 on page 153). the absolute priority makes a secondary selection based on the following priority list: 1. high priority target port queues 2. low priority target port queues 3. discard queue 4. wrap queue the following information must be configured for each target port queue. port queue threshold (th_pq) when the number of bytes enqueued in the target port queue exceeds the port queue threshold, the corre- sponding weighted fair queueing (wfq) calendar cannot be selected for service. this back pressure to the wfq calendars assures th at best effort traffic is not allowed to fill the target port queue ahead of frames dequeued from the low-latency sustainable bandwidth (lls) and normal-latency sustainable bandwidth (nls) calendars. the back pressure is the mechanism by which the target port bandwidth is reflected in the operation of the wfq calendars. the following transform is used to specify th_pq: th_pq = port_queue_threshold (bytes) / 106 (bytes) when configuring this threshold, use a value larger than the maximum transmission unit (mtu) of the target port. port queue + flow queue threshold (th_pq+fq) this is the threshold for the total number of bytes in the target port queue plus the total number of bytes in all flow queues that are configured for this target port. when this threshold is exceeded by the value in the queue, the target port is congested. the flow control me chanisms use this congestion indication to select a transmit probability. the following transform is us ed to specify th_pq+fq: th_pq+fq = port_queue+scheduler_threshold (bytes) / 106 (bytes) ibm powernp np2g network processor preliminary egress enqueuer / dequeuer / scheduler page 158 of 539 np2_ds_sec06_eeds.fm.01 february 12, 2003 6.4.2 configuring flow queues table 6-4 on page 158 illustrates ho w to configure a flow qcb using th e same set of sc heduler parameter combinations found in table 6-3: valid combinations of scheduler parameters on page 152. 6.4.2.1 additional configuration notes once the scheduler is enabled via the memory configuration register, the picocode is unable to enqueue directly to a target port queue. to disable the scheduler, the software system design must assure that the scheduler is drained of all traffic. the control access bus (cab) can examine all target port queue counts; when all counts are zero, the scheduler is drained. a flow queue control block (qcb) must be configured for discards (tp = 41). a sustained service rate must be defined (ssd 0). a peak service rate and queue weight must not be specified (psd = 0 and qd = 0). two flow qcbs must be defined for wrap traffic. one must be defined for guided traffic (tp = 40), and one for frame traffic (tp = 42). for these qcbs, the peak service rate and sustained service rate must not be specified (psd = 0 and ssd = 0). queue weight must not be zero (qd 0). 6.4.3 scheduler accuracy and capacity scheduler accuracy and capacity are affected by the 11/10 cycle select (bit 6) and the ds_d4_refresh_rate (bit 13) fields of the dram parameter register (see section 13.1.2 dram parameter register (dram_parm) on page 434). these limit the number of packets per second that can be processed by the scheduler. when this limit is exceeded, the packets are delayed, the accuracy of the scheduler is affected, and best effort traffic might not be serviced. the 10-cycle mode co rresponds to a tick rate of 150 ns and 11 -cycle mode corresponds to a tick rate of 165 ns. the normal refresh rate corresponds to a refresh overhead of 1%; double refresh rate has a 2% over- head. the number of packets per second that can be scheduled accurately is determined by the following equation: packets per second = (1 - refresh_overhead) / tick_rate (seconds) for example, if tick_rate = 165 ns and the refresh_ overhead is 1%, t he scheduler will accurately schedule 6 million packets per second (mpps). for a given media rate, the minimum sustainable packet size for the scheduler is determined by the following equation: table 6-4. configure a flow qcb qos qcb.p qcb.sd qcb.psd qcb.qd low latency with guaranteed bw shaping 0 00 0 normal latency with guaranteed bw shaping 1 00 0 best effort 100 0 best effort with peak rate 1 0 0 0 normal latency with guaranteed bw shaping with best effort 1 00 0 normal latency with guaranteed bw shaping with best effort, and peak rate 1 0 0 0 ibm powernp np2g preliminary network processor np2_ds_sec06_eeds.fm.01 february 12, 2003 egress enqueuer / dequeuer / scheduler page 159 of 539 bytes per packet = (1 / (1 - refresh_overhead)) * tick_rate (seconds) / packet * media_rate (bits per sec- ond) * (1 byte / 8 bits) using the tick_rate and refresh_overhead from the previous equation and a media_rate of 2.48 gigabits per second (gbps), the minimum sustainable packet size is 51.7 bytes. for a given minimum packet length, the maximum bandwid th that can be successfully scheduled is deter- mined by the following equation: maximum bandwidth scheduled (bits per second) = packet_length (bytes) * (8 bits/ 1 byte) * (1 / tick_rate (seconds)) * (1 - refresh_overhead) using the tick_rate and refresh_overhead from the previous equation and a packet length of 48 bytes, the maximum bandwidth that can be successfully scheduled is 2.3 gbps. ibm powernp np2g network processor preliminary egress enqueuer / dequeuer / scheduler page 160 of 539 np2_ds_sec06_eeds.fm.01 february 12, 2003 ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 161 of 539 7. embedded processor complex 7.1 overview the embedded processor complex (epc) performs all processing functions for the np2g. it provides and controls the programmability of the np2g. in general, the epc acce pts data for proce ssing from both the ingress and egress enqueuer / dequeuer / schedulers. the epc, under picocode control and with hardware- assisted coprocessors, determines what forwarding action is to be taken on the data. the data may be forwarded to its final destination, or may be discarded. the epc consists of the followin g components, as illustrated in figure 7-1 on page 164: six dyadic protocol processor units (dppu) each dppu consists of two core language processors (clps), 10 shared coprocessors, one coproces- sor data bus, one coprocessor command bus, and a shared memory pool. each clp contains one arithmetic and logic unit (alu) and supports two picocode threads, so each dppu has four threads (see section 7.1.1 thread types on page 165 for more information). although there are 24 independent threads, each clp can execute the command of only one of its picocode threads, so at any instant only 12 threads are executing on all of the clps. the clps and coprocessors contain independent copies of each thread?s registers and arrays. most coprocessors perform specialized functions as described below, and can operate concurrently with each other and with the clps. interrupts and timers the np2g has four interrupt vectors. each interrupt can be configured to initiate a dispatch to occur to one of the threads for processing. the device also has four timers that can be used to generate periodic interrupts. instruction memory the instruction memory consists of eight embedded rams that are loaded during initialization and con- tain the picocode for forwarding frames and managing the system. the total size is 32 k instructions. the memory is 8-way interleaved, wit h each interleave providing four instruction words per access. ibm powernp np2g network processor preliminary embedded processor complex page 162 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 control store arbiter (csa) the csa controls access to the control store (cs) which allocates memory bandwidth among the threads of all the dyadic protocol processors. the cs is shared among the tree search engines and the picocode can directly access the cs through commands to the tree search engine (tse) coprocessor. the tse coprocessor also accesses the cs during tree searches. dispatch unit the dispatch unit dequeues frame information from the ingress-eds and egress-eds queues. after dequeue, the dispatch unit reads part of the frame from the ingress or egress data store (ds) and places it into the datapool. as soon as a thread bec omes idle, the dispatch unit passes the frame (with appropriate control information) to the thread for processing. the dispatch unit also handles timers and interrupts by dispatching the work required for these to an available thread. completion unit (cu) the cu performs two functions: - it provides the interfaces between the epc and the ingress and egress edss. each eds performs an enqueue action whereby a frame address, together with appropriate parameters, is queued in a transmission queue or a dispatch unit queue. - the cu guarantees frame sequence. since multip le threads can process frames belonging to the same flow, the cu ensures that all frames are enqueued in the ingress or egress transmission queues in the proper order. hardware classifier (hc) the hc parses frame data that is dispatched to a thread. the results are used to precondition the state of a thread by initializing the thread?s general purpose and coprocessor scalar registers and a starting instruction address for the clp. parsing results indicate the type of layer 2 encapsulation, as well as some information about the layer 3 packet. recognizable laye r 2 encapsulations inclu de ppp, 802.3, dix v2, llc, snap header, and vlan tagging. reportable layer 3 information includes ip and ipx network protocols, five programmable network protocols, the detection of ip option fi elds, and transport protocols (udp, tcp) for ip. ingress and egress data store interface and arbiter each thread has access to the ingress and egress data store through a data store coprocessor. read access is provided when reading ?more data? and write access is provided when writing back the con- tents of the shared memory pool (smp) to the data store. one arbiter is required for each data store since only one thread at a time can access either data store. control access bus (cab) arbiter each thread has access to the cab, which permits access to all memory and registers in the network processor. the cab arbiter arbitrates among the threads for access to the cab. ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 163 of 539 debugging and single-step control the cab enables the gfh thread to control each thread on the device for debugging purposes. for example, the cab can be used by the gfh thread to run a selected thread in single-step execution mode. (see section 12. debug facilities on page 429 for more information.) policy manager the policy manager is a hardware assist of the epc that performs policy management on up to 1 k ingress flows. it supports four management algori thms. the two algorithm pairs are ?single rate three color marker? and ?two rate three color marker,? both of which can be operated in color-blind or color- aware mode. the algorithms are specified in ietf rfcs 2697 and 2698, available at http://www.ietf.org . counter manager the counter manager is a hardware assist engine us ed by the epc to manage counters defined by the picocode for statistics, flow control, and policy management. the counter manager is responsible for counter updates, reads, clears, and writes. the counter manager's interface to the counter coprocessor provides picocode acce ss to these functions. semaphore manager the semaphore manager assists in controlling access to shared resources, such as tables and control structures, through the use of semaphores. it grants se maphores either in dispatch order (ordered sema- phores) or in request order (unordered semaphores). ludeftable, comptable, and free queues are tables and queues for use by the tree search engine. for more information, see section 8.2.5.1 the ludeftable on page 307. ibm powernp np2g network processor preliminary embedded processor complex page 164 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 figure 7-1. embedded processor complex block diagram control store arbiter h0 h1 z0 d2 d6 on-chip memories off-chip memories dispatch unit ingress ds egress ds interface instruction memory cab arbiter debug & single step control ingress eds queue egress eds queue ingress data ingress data store interface (rd) egress data egress data store interface (rd) cab ludeftable comptable freeqs interrupts freezeepc exception d0 completion unit counter manager policy manager hardware classifier d3 powerpc core interrupt dppu 1 dppu 6 tree search engine store and arbiter (rd+wr) and arbiter (rd+wr) store interface interface interrupts & timers 405 semaphore manager ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 165 of 539 7.1.1 thread types the epc has 24 threads that can simultaneously process 24 frames. a thread has a unique set of general purpose, scalar, and array registers, but shares exec ution resources in the clp with another thread and execution resources in the coprocessors with three other threads. each clp within a dppu can run two threads, making four threads per dppu, or 24 total. the first dppu contains the gfh, gth, and the ppc threads and the other seven dppus contain the gdh threads. these five types of threads are described in the following list: general data handler (gdh) there are 20 gdh threads. gdhs ar e used for forwarding frames. guided frame handler (gfh) there is one gfh thread available in the epc. a guided frame can only be processed by the gfh thread, but the gfh can be configured to process data fr ames like a gdh thread. the gfh executes guided frame-related picocode, runs device management re lated picocode, and exchanges control information with a control point function or a remote network processor. when there is no such task to perform and the option is enabled, the gfh may execute frame forwarding-related picocode. general table handler (gth) there is one gth thread available in the epc. the gth executes tree management commands not available to other threads. the gth performs actions including hardware assist to perform tree inserts, tree deletes, tree aging, and rope management. the gth can process data frames like a gdh when there are no tree management functions to perform. general powerpc handler request (gph-req) there is one gph-req thread available in the epc. the gph-req thread processes frames bound to the embedded powerpc. work for this thread is the result of a re-enqueue action from another thread in the epc to the gpq queue. the gph-req thread moves data bound for the powerpc to the powerpc?s mailbox (a memory area) and then notifies the powerpc that it has data to process. see section 10.8 mailbox communications and dram interface macro on page 381 for more information. general powerpc handler response (gph-resp) there is one gph-resp thread available in the epc. the gph-resp thread processes responses from the embedded powerpc. work for this thread is dispatched due to an interrupt initiated by the powerpc and does not use dispatch unit memory. all the information used by this thread is found in the embedded powerpc?s mailbox. see section 10.8 mailbox communications and dram interface macro on page 381 for more information. ibm powernp np2g network processor preliminary embedded processor complex page 166 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 7.2 dyadic protocol processor unit (dppu) this section describes the basic functionality of the dppu. two aspects of the dppu are discussed in detail in separate sections: section 7.3 beginning on page 173 discusses the operational codes (opcodes) for the core language processors (clps), and section 7.4 beginning on page 202 cover?s the dppu?s coproces- sors. each dppu consists of the following functional blocks, as illustrated in figure 7-2 . two core language processors (clps) ten coprocessors a coprocessor data bus a coprocessor command bus (the coprocessor databus and coprocessor execution interfaces) a 4-kb shared memory pool (1 kb per thread) each clp supports two threads, so each dppu has four threads which execute the picocode that is used to forward frames, update tables, and maintain the network processor. each dppu interfaces with the following functional blocks of the epc: instruction memory dispatch unit control store arbiter (csa) completion unit (cu) hardware classifier interface and arbiter to the ingress and egress data stores control access bus (cab) arbiter debugging facilities counter manager policy manager ludeftable queue comp free queue semaphore manager ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 167 of 539 7.2.1 core language processor (clp) each dppu contains two clps. the clp executes the epc?s core instruction set and controls thread swap- ping and instruction fetching. each clp is a 32-bit picoprocessor consisting of: 16 32-bit or 32 16-bit general purpose registers (gprs) per thread. (for more information, see table 7- 1: core language processor address map on page 169 .) a one-cycle alu supporting an instruction set that includes: - binary addition and subtraction - bit-wise logical and, or, and not - compare - count leading zeros - shift left and right logical - shift right arithmetic - rotate left and right figure 7-2. dyadic protocol proc essor unit functional blocks processor processor shared memory pool cpdi arbiter cpei arbiter checksum string cab interface counter policy 4 cab arbiter counter manager policy manager tree search engine coprocessor coprocessor instruction memory interface instruction memory interface hardware classifier hardware classifier cab access core language core language dyadic protocol processor unit copy execution interface completion unit enqueue data ingress ds interface egress ds interface dispatcher smdi data interface dispatcher arbiter shared memory data interface semaphore semaphore manager store crb cop response bus ibm powernp np2g network processor preliminary embedded processor complex page 168 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 - bit manipulation commands: set, clear, test, and flip - gpr transfer of halfword to halfword, word to word, and halfword to word with and without sign extensions - all instructions can be coded to run conditionally. this eliminates the need for traditional branch-and- test coding techniques, which improves performance and reduces the size of the code. all arithmetic and logical instructions can be coded to execute without setting alu status flags. management for handling two threads with zero overhead for context switching read-only scalar registers that provide access to the following information: - interrupt vectors -timestamps - output of a pseudo random number generator - picoprocessor status - work queue status (such as the ingress and egress data queues) - configurable identifiers for more information, see table 7-1: core language processor address map on page 169 . 16-word instruction prefetch shared by each thread instruction execution unit that executes branch instructions, instruction fetch, and coprocessor access coprocessor data interface (cpdi) with the following features: - access from any byte, halfword, or word of a gpr to an array, or from an array to a gpr - access to coprocessor scalar registers - various sign, zero, and one extension formats - quadword transfers within the coprocessor arrays - quadword reset to zero of coprocessor arrays coprocessor execution interface (cpei) with the following features: - synchronous or asynchronous coprocessor operation - multiple coprocessor synchronization - synchronization and branch-on-coprocessor return code ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 169 of 539 7.2.1.1 core language processor address map figure 7-3. core language processor table 7-1. core language processor address map (page 1 of 3) name register (array) 1 number size (bits) access description pc x?00? 16 r program counter. address of the next instruction to be executed. alustatus x?01? 4 r the current alu status flags: 3zero 2 carry 1sign 0overflow linkreg x?02? 16 r/w link register. return address for the most recent subroutine 1. a number in parentheses is the array number for this coproc essor. each array has a register number and an array number. alu instruction execution unit cpei interface cpdi interface instruction fetch interface instruction stack 8x32b flags control immediate data cpei cpdi instruction memory 128b interface gpr pool 16x32b gpr pool 16x32b cpei arbiter cpdi arbiter scalar registers coprocessor data interface ibm powernp np2g network processor preliminary embedded processor complex page 170 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 copstatus x?03? 10 r indicates whether the coprocessor is busy or idle. a coprocessor that is busy will stall the clp when the coprocessor command was executed synchronously or a wait command was issued for the coprocessor. 1 coprocessor is busy 0 coprocessor is idle coprtncode x?04? 10 r the definition of ok/ko is defined by the coprocessor. 1ok 0not ok threadnum x?05? 5 r the thread number (0..31) stack_link_ptr x?06? 4 r the current point er value into the clp link stack. timestamp x?80? 32 r free-running, 1 ms timer randomnum x?81? 32 r random number for programmer?s use intvector0 x?83? 32 r read-only copy of interrupt vector 0. reading this register has no effect on the actual interrupt vector 0. intvector1 x?84? 32 r read-only copy of interrupt vector 1. reading this register has no effect on the actual interrupt vector 1. intvector2 x?85? 32 r read-only copy of interrupt vector 2. reading this register has no effect on the actual interrupt vector 2. intvector3 x?86? 32 r read-only copy of interrupt vector 3. reading this register has no effect on the actual interrupt vector 3. idlethreads x?87? 32 r indicates that a thread is enabled and idle qvalid x?88? 32 r indicates status of the queues (valid or invalid). reserved x?89? 6 r reserved. sw_defined_a x?8a? 32 r software-defined register sw_defined_b x?8b? 32 r software-defined register sw_defined_c x?8c? 32 r software-defined register sw_defined_d x?8d? 32 r software-defined register version_id x?8f? 32 r contains the version number of the hardware. gprw0 x?c0? 32 r general purpose register w0 gprw2 x?c1? 32 r general purpose register w2 gprw4 x?c2? 32 r general purpose register w4 gprw6 x?c3? 32 r general purpose register w6 gprw8 x?c4? 32 r general purpose register w8 gprw10 x?c5? 32 r general purpose register w10 gprw12 x?c6? 32 r general purpose register w12 gprw14 x?c7? 32 r general purpose register w14 gprw16 x?c8? 32 r general purpose register w16 gprw18 x?c9? 32 r general purpose register w18 table 7-1. core language processor address map (page 2 of 3) name register (array) 1 number size (bits) access description 1. a number in parentheses is the array number for this coproc essor. each array has a register number and an array number. ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 171 of 539 7.2.2 clp opcode formats the core instructions (opcodes) of the clp, their form ats, and their definitions are discussed in detail in sec- tion 7.3 beginning on page 173 . 7.2.3 dppu coprocessors all data processing occurs in the ten dppu coprocessors. they are discussed in detail in section 7.4 begin- ning on page 202 . gprw20 x?ca? 32 r general purpose register w20 gprw22 x?cb? 32 r general purpose register w22 gprw24 x?cc? 32 r general purpose register w24 gprw26 x?cd? 32 r general purpose register w26 gprw28 x?ce? 32 r general purpose register w28 gprw30 x?cf? 32 r general purpose register w30 pgramstack0 x?fc? (0) 128 r/w entries in the program stack (used by the clp hardware to build instruction address stacks fo r the branch and link commands) pgramstack1 x?fd? (1) 128 r/w entries in the program stack (used by the clp hardware to build instruction address stacks fo r the branch and link commands) table 7-1. core language processor address map (page 3 of 3) name register (array) 1 number size (bits) access description 1. a number in parentheses is the array number for this coproc essor. each array has a register number and an array number. ibm powernp np2g network processor preliminary embedded processor complex page 172 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 7.2.4 shared memory pool the 4-kb shared memory pool is used by all threads running in the dppu. each thread uses 1 kb and is subdivided into the following areas: table 7-2. shared memory pool quadword address owning coprocessor array 0-2 enqueue fcb page 1a 3 data store configuration quadword 4-6 enqueue fcb page 1b 7 clp stack 0 8-10 enqueue fcb page 2 11 clp stack 1 12-15 data store scratch memory 0 16-23 data store datapool 24-31 data store scratch memory 1 32-47 tse tree search results area 0 40-47 tse tree search results area 1 48-63 tse tree search results area 2 56-63 tse tree search results area 3 ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 173 of 539 7.3 clp opcode formats this section describes the core instructions (opcodes) of the clp, their formats, and their definitions. clp opcodes fall into four categories: control opcodes, al u opcodes, data movement opcodes, and coprocessor execution opcodes. shaded areas of the opcode show which bits uniquely identify the opcode. 7.3.1 control opcodes most control opcodes have a condition field (cond) th at indicates under what condition of the alu flags z (zero), c (carry), n (negative), and v (overflow) this command should be executed. the clp supports 15 dif- ferent signed and unsigned conditions. table 7-3. condition codes (cond field) value alu flag comparison meaning 0000 z = 1 equal or zero 0001 z = 0 not equal or not zero 0010 c = 1 carry set 0011 c = 1 and z = 0 unsigned higher 0100 c = 0 or z = 1 unsigned lower or equal 0101 c = 0 unsigned lower 0110 - reserved 0111 don?t care always 1000 n = 0 signed positive 1001 s = 1 signed negative 1010 n = v signed greater or equal 1011 z = 0 and n = v signed greater than 1100 z = 1 or (n/ = v) signed less than or equal 1101 n/ = v signed less than 1110 v = 1 overflow 1111 v = 0 no overflow ibm powernp np2g network processor preliminary embedded processor complex page 174 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 7.3.1.1 nop opcode the nop opcode executes one cycle of time and does not change any state within the processor. 7.3.1.2 exit opcode the exit opcode terminates the current instruction st ream. the clp will be put in to an idle state and made available for a new dispatch. the exit command is executed conditionally, and if the condition is not true, it will be equivalent to a nop opcode. pseudocode: if (cond) then clp_state_machine <- idle else nop end if 7.3.1.3 test and branch opcode the test and branch opcode tests a single bit within a gp r register. if the desired condition is met, the thread will branch. the r field is the gpr register to be test ed. the bp field represents the bit position within the gpr to be tested. the c field represents the test condition: if c = 1, the branch is taken if the bit tested is a ?1?; if c = 0, the branch is taken if the bit tested is a ?0?. th e branch target id is calculat ed by using the disp16 field as a displacement from the program counter (pc). this command does not set the alu flags. pseudocode: if r(bp)=c then pc <- pc + disp16 else nop end if type 313029282726252423222120191817161514131211109876543210 nop 0 0 0 0 1 00000000000000000000000000 0 exit 0 0 0 1 0 000 cond 00000000000000000000 test and branch 0 0 0 1 0 1 c bp r disp16 branch and link 0 0 0 1 1h 1 1 cond rt target16 return 0 0 0 1 1 0 0 0 cond 000000000000000 00000 branch register 0 0 0 1 1h 0 0 cond rt 00000000000 10000 branch pc relative 0 0 0 1 1 0 1 0 cond 0 0 0 0 disp16 branch reg+off 0 0 0 1 1 0 0 1 cond rt target16 ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 175 of 539 7.3.1.4 branch and link opcode the branch and link opcode performs a conditional branch, adds one to the value of the current program counter, and places it onto the program stack. opcode fields rt, h, and target16 determine the destination of the branch. if rt is in the range of 1 - 15, it is the word address of a gpr register, the contents of which are used as the base of the branch desti nation. if rt is 0, the base of the branch destination will be 0x?0000?. the h field indicates which half of the gpr register is used as the base address. an h = 0 indicates the even half of the gpr register (high half of the gpr) and h = 1 indicates the odd half. the target16 field is added to the base to form the complete branch de stination. if the linkptr register in dicates that the branch and link will overflow the 16-entry program stack, a stack error occurs. pseudocode: if (cond) then -- put ia+1 onto the program stack if (linkptr=endofstack) then stackerr <- 1 else programstack(linkptr+1) <- pc + 1 end if -- load the ia with the branch target if (rt=0) then pc <- target16 elsif (h=0) then pc <- gpr(rt)(31:16) + target16 else pc <- gpr(rt)(15:0) + target16 end if else nop end if ibm powernp np2g network processor preliminary embedded processor complex page 176 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 7.3.1.5 return opcode the return opcode performs a conditional branch with the branch destination being the top of the program stack. if the linkptr register indicates that the stack is empty, a stack error occurs. pseudocode: if (cond) then if (linkptr=emptystack) then stackerr <- 1 else pc <- programstack(linkptr) end if else nop end if 7.3.1.6 branch register opcode the branch register opcode performs a conditional branch. opcode fields rt and h determine the destination of the branch. the rt field is the wo rd address of a gpr register of wh ich the contents will be used as the branch destination. the h field indicates which half of the gpr register will be used. an h = 0 indicates the even half of the gpr register (high half of the gpr), and h = 1 indicates the odd half. pseudocode: if (cond) then if (h=0) then pc <- gpr(rt)(31:16) + target16 else pc <- gpr(rt)(15:0) + target16 end if else nop end if 7.3.1.7 branch pc relative opcode the branch pc relative opcode performs a conditional branch. opcode fields pc and disp16 determine the destination of the branch. the contents of the pc field are used as the base of the branch destination. the disp16 field will be added to the base to form the complete br anch destination. pseudocode: if (cond) then pc <- pc + disp16 else nop end if ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 177 of 539 7.3.1.8 branch reg+off opcode the branch register plus offset op code will perform a conditio nal branch. the opcode fi elds rt and target16 determine the destination of the branch. if rt is in the range of 1 - 15, it is the word address of a gpr register of which the contents of the high halfword (or even half) are used as the base of the branch destination. if rt is 0, the base of the branch destination is x?0000?. the target16 field is added to the base to form the com- plete branch destination. pseudocode: if (cond) then if (rt=0) then pc <- target16 else pc <- gpr(rt)(31:16) + target16 end if else nop end if ibm powernp np2g network processor preliminary embedded processor complex page 178 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 7.3.2 data movement opcodes the data movement opcodes are used to transfer data to and from the coprocessor?s scalar registers and arrays. the opcodes support 23 options of direction, size , extension, and fill, represented by the ot5 field. data movement opcodes access the processor data interface (pdi). figure 7-4. ot5 field definition: loading halfword/word gprs from a halfword/word array gpr word register 0 1 2 ot5 field load odd halfword register from array halfword 0 array d d d d load even halfword register from array halfword d d d d 1 2 3 load word register from array halfword zero extended 0 s load word register from array halfword sign extended d d load word register from array word byte hw 0 1 6 (hex) 3 ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 179 of 539 figure 7-5. ot5 field definition: loading gpr byte from array byte gpr word register ot5 field load byte 3 of gpr from array byte 8 array d d load byte 2 of gpr from array byte 9 a b load byte 1 of gpr from array byte load byte 0 of gpr from array byte byte hw 0 1 d d d d d d (hex) 23 01 ibm powernp np2g network processor preliminary embedded processor complex page 180 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 figure 7-6. ot5 field definition: loading gpr halfword/word from array byte gpr word register ot5 field load odd halfword gpr from array byte c array d d load even halfword gpr from array byte d e f load even halfword gpr from array byte zero extended load halfword gpr from array byte sign extended byte hw 0 1 d d d d 0 s d 0 d s 4 d d 5 d d 0 0 0 s s s load word gpr from array byte zero extended load word gpr from array byte sign extended (hex) 23 01 zero extended sign extended ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 181 of 539 figure 7-7. ot5 field definition: store gpr byte/halfword/word to array byte/halfword/word gpr word register ot5 field store byte 3 of gpr to array byte 18 array d d 19 1a 1b byte hw 0 1 d d d d d d d d d d 10 11 d d 16 store byte 2 of gpr to array byte store byte 1 of gpr to array byte store byte 0 of gpr to array byte store odd halfword gpr to array halfword store even halfword gpr to array halfword store word gpr to array word (hex) 23 01 ibm powernp np2g network processor preliminary embedded processor complex page 182 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 7.3.2.1 memory indirect opcode the memory indirect opcode transfers data between a gpr and a coprocessor array via a logical address in which the base offset into the array is contained in a gpr. the logical address consists of a coprocessor number, coprocessor array, base address, and an offs et. the c# field indicates the coprocessor which will be accessed. the ca field indi cates which array of the c oprocessor will be accessed. the offset into the array is the contents of gpr, indicated by ra as a base plus th e six bits of immediate offset, off6. ra is a half-word address in the range of 0 - 7. the x indicates whether or not the transaction will be in cell header skip mode. the memory indirect opcode is executed conditionally if the alu flags meet the condition represented by the cond field. the word address of the gpr register used to transfer or receive data from the array is indicated by the field r. the actual direction, size, extension format, and location of gpr bytes affected are indicated by the ot5 field. pseudocode: if (cond) then addr.coprocessor number <= c# addr.coprocessor array <= ca addr.array offset <= gpr(ra)+off6 addr.x_mode <= x if (ot5 = load) then gpr(r,ot5) <= array(addr) else array(addr) <= gpr(r,ot5) end if; end if type 313029282726252423222120191817161514131211109876543210 memory indirect 0 0 1 ot5 cond r x ra c# ca off6 memory add indirect 0 1 0 ot5 cond r x ra 0000 off8 memory direct 0 1 1ot5 cond rx 0 off2 c# ca off6 scalar access 0 1 1ot5 cond r0 1 0 0 c# cr scalar immed 1 1 0 1 c# cr imm16 transfer qw 1 1 0 0 c#d cad 00 qwoffd 0000 c#s cas 0 1qwoffs zero array 1 1 0 000 size cond boffset x000 c# ca 1 1 qwoffs ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 183 of 539 7.3.2.2 memory address indirect opcode the memory address indirect opcode transfers data between a gpr and a coprocessor data entity (scalar or array) by mapping the coprocessor logical address into the base address held in the gpr indicated by ra. since not all of the coprocessors have arrays, maximum size arrays, or the maximum number of scalars, the address map will have many gaps. data access via this method is the same as access via the more logic- based method. the final address is formed by the contents of gpr indicated by ra plus off8 (eight bits). ra is a half-word address in the range of 0 - 7. the x indicates whether or not the transaction will be in cell header skip mode. the memory address indirect opcode is executed conditionally if the alu flags meet the condition repre- sented by the cond field. the word address of the gpr register used to transfer or receive data from the array is indicated by the field r. the actual directi on, size, extension format, and location of gpr bytes affected are indicated by the ot5 field. pseudocode: if (cond) then address <= gpr(ra) + off8 addr.array_notscalar <= address(14) addr.coprocessor number <= address(13:10) addr.coprocessor array <= address(9:8) (if an array access) addr.scalar address <= address(7:0) (if a scalar access) addr.array offset <= address(7:0) (if an array access) addr.x_mode <= x if (ot5 = load) then if (addr.array_notscalar=1) then gpr(r,ot5) <= array(addr) else gpr(r,ot5) <= scalar(addr) end if; else if (addr.array_notscalar=1) then array(addr) <= gpr(r,ot5) else scalar(addr) <= gpr(r,ot5) end if; end if; end if ibm powernp np2g network processor preliminary embedded processor complex page 184 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 7.3.2.3 memory direct opcode the memory direct opcode transfers data between a gpr and a coprocessor array via a logical address that is specified in the immediate portion of the opcode. the logical address consists of a coprocessor number, coprocessor array, and an offset. the c# field indicates the coprocessor that is accessed. the ca field indi- cates which array of the coprocessor is accessed. the offs et is made up of eight bits: the most significant two bits are located in field off2 and the remaining six bits are in off6. the x indicates whether or not the transac- tion will be in cell header skip mode. the memory direct opcode is executed conditionally if the alu flags meet the condition represented by the cond field. the word address of the gpr register used to transfer or receive data from the array is indicated by the r field. the actual direction, size, extension format, and loca- tion of gpr bytes affected are indicated by the ot5 field. pseudocode: if (cond) then addr.coprocessor number <= c# addr.coprocessor array <= ca addr.array offset <= off2 & off6 addr.x_mode <= x if (ot5 = load) then gpr(r,ot5) <= array(addr) else array(addr) <= gpr(r,ot5) end if; end if 7.3.2.4 scalar access opcode the scalar access opcode transfers data between a gpr and a scalar register via a logical address that con- sists of a coprocessor number and a scalar register number. the c# field indicates the coprocessor that is accessed. the scalar register number is indicated by th e cr field. the scalar access opcode is executed con- ditionally if the alu flags meet the condition represented by the cond field. the word address of the gpr register used to transfer or receive data from the scalar register is indicated by the r field. the actual direc- tion, size, extension format, and location of gpr bytes affected are indicated by the ot5 field. pseudocode: if (cond) then addr.coprocessor number <= c# addr.scalar number <= ca if (ot5 = load) then gpr(r,ot5) <= scalar(addr) else scalar(addr) <= gpr(r,ot5) end if; end if ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 185 of 539 7.3.2.5 scalar immediate opcode the scalar immediate opcode writes immediate data to a scalar register via a logical address that is com- pletely specified in the immediate portion of the opcode. the logical address consists of a coprocessor num- ber and a coprocessor register number. the c# field indi cates the coprocessor that is accessed. the cr field indicates the scalar register number. the data to be written is the imm16 field. pseudocode: addr.coprocessor number <= c# addr.scalar register number <= ca scalar(addr) <= imm16 7.3.2.6 transfer quadword opcode the transfer quadword opcode transfers quadword data from one array location to another using one instruc- tion. the source quadword is identified by the c#s (coprocessor number), cas (source array number), and qwoffs (quadword offset into the array). the destination quadword is identified by the c#d, cad, and qwoffd.this transfer is only valid on quadword boundaries. pseudocode: saddr.coprocessor number <= c#s saddr.array number <= cas saddr.quadword offset <= qwoffs daddr.coprocessor number <= c#d daddr.array number <= cad daddr.quadword offset <= qwoffd array(daddr) <= array(saddr) ibm powernp np2g network processor preliminary embedded processor complex page 186 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 7.3.2.7 zero array opcode the zero array opcode zeroes out a portion of an array with one instruction. the size of the zeroed-out por- tion can be a byte, halfword, word, or quadword. quadword access must be on quadword address bound- aries. accesses to a byte, halfwo rd, or word can begin on any by te boundary and will have the same characteristics as any gpr-based write to the array. for example, if the array is defined to wrap from the end to the beginning, the zero array command wraps from the end of the array to the beginning. the c# field indi- cates the coprocessor that will be ac cessed. the ca field indicates wh ich array of the coprocessor is accessed. the qwoff is the quadword offset into the array, and the boff is the byte offset into the array. the x indicates whether or not the transaction is in cell header skip mode. the opcode is executed conditionally if the alu flags meet the condition represented by the cond field. the actual size of the access is defined by the size field (byte = 00, halfword = 01, word = 10, q uadword = 11). for quadword accesses boff should equal 0x0. pseudocode: if (cond) then addr.coprocessor number <= c# addr.array number <= ca addr.quadword offset <= qwoff addr.byte offset <= boff if size = 00 then array(addr) <= 0x00 if size = 01 then array(addr : addr+1) <= 0x0000 if size = 10 then array(addr : addr+3) <= 0x00000000 if size = 11 then array(addr : addr+15) <= 0x0000000000000000000000000000000 end if; ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 187 of 539 7.3.3 coprocessor execution opcodes the coprocessor execution opcodes are used to initiate operations or synchronize operations with the copro- cessors. the execution type opcodes initiate accesses on the processor execution interface (pei). a com- mand to a coprocessor consists of six bits of coproc essor operation and 44 bits of coprocessor arguments. the definition of the operation and ar gument bits is coprocessor dependent. a coprocessor can operate synchronously or asynchronously. sync hronous operation means the execution of the thread initiating the coprocessor command stalls until the coprocessor operation is complete. asyn- chronous operation means the executing thread will not stall when a coprocessor execution command is issued, but rather can continue operating on the instruction stream. it is important to re-synchronize a copro- cessor command that was issued asynchronously before using resources that the coprocessor needs for execution of the command. this can be done wi th the ?wait? coprocessor execution opcodes. the clp runs the instruction stream of two threads in which only one thread can actually execute in a given cycle. the clp thread that owns priority cannot be sta lled by the execution of the non-priority thread. priority is granted to the only active thread in a clp or to th e thread that is given priority by the other thread. the coprocessor execution opcodes indicated by the p bit in the following opcode map can give up the priority status of the thread. type 313029282726252423222120191817161514131211109876543210 execute direct 1 1 1 1c#p cpop a 0imm16 execute indirect 1 1 1 1c#p cpop a 1r imm12 execute direct conditional 1 1 1 0c# cond op 0 1imm16 execute indirect conditional 1 1 1 0c# cond op 1 1r imm12 wait 1 1 1 00000p000 000 0 mask16 wait and branch 1 1 1 0c#p000 10ok 0target16 ibm powernp np2g network processor preliminary embedded processor complex page 188 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 7.3.3.1 execute direct opcode the execute direct opcode initiates a coprocessor co mmand in which all of the operation arguments are passed immediately to the opcode. the c# field indicates which coproc essor will execute the command. the cpopfield is the coprocessor operation field. the im m16 field contains the operation arguments that are passed with the command. the a field indicates whethe r the command should be executed asynchronously. the p field indicates if the thread should give up priority. pseudocode: exe.coprocessor number <= c# exe.coprocessor operation <= cpop exe.coprocessor arguments <= 0000000000000000000000000000 & imm16 coprocessor <= exe if a=1 then pc <= pc+1 else pc <= stall end if if p=1 then priorityowner(other thread)<= true else priorityowner(other thread)<= priorityowner(other thread) end if; ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 189 of 539 7.3.3.2 execute indirect opcode the execute indirect opcode initiates a coprocessor command in which the operation arguments are a combi- nation of a gpr register and an immediate field. the field c# indicates which coprocessor the command is to be executed on. the field cpop is the coprocessor oper ation field. the r field is the gpr register to be passed as part of the operation arguments. the imm12 field contains the immediate operation arguments that are passed. the a field indicates whether the command should be executed asynchronously. the p field indicates if the thread should give up priority. pseudocode: exe.coprocessor number <= c# exe.coprocessor operation <= cpop exe.coprocessor arguments <= imm12 & gpr(r) coprocessor <= exe if a=1 then pc <= pc+1 else pc <= stall end if if p=1 then priorityowner(other thread)<= true else priorityowner(other thread)<= priorityowner(other thread) end if; 7.3.3.3 execute direct conditional opcode the execute direct conditional opcode is similar to the execute direct opcode except that the execute direct conditional opcode command can be issued conditionally based on the cond field. to make room in the opcode for the cond field, the coprocessor opcode field (op) is shortened to two bits. because the high order four bits of the coprocessor operation are assumed to be zeros, conditional operations are restricted to the lower four commands of a coprocessor. he command is assumed to be synchronous because the opcode does not have a bit to indicate whether it is asynchronous or synchronous. priority cannot be released with this opcode. pseudocode: if (cond) then exe.coprocessor number <= c# exe.coprocessor operation <= 0000&op exe.coprocessor arguments <= 0000000000000000000000000000 & imm16 coprocessor <= exe end if ibm powernp np2g network processor preliminary embedded processor complex page 190 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 7.3.3.4 execute indirect conditional opcode the execute indirect conditional opcode is similar to th e execute indirect opcode exce pt that the execute indi- rect command can be issued conditionally based on the cond field. to make room in the opcode for the cond field, the coprocessor opcode field (op) is shortened to two bits. because the high order four bits of the copro- cessor operation are assumed to be 0s, conditional operations are restricted to the lower four commands of a coprocessor. the command is assumed to be synchronous because the opcode does not have a bit to indi- cate whether it is asynchronous or synchronous. priority cannot be released with this opcode. pseudocode: if (cond) then exe.coprocessor number <= c# exe.coprocessor operation <= 0000&op exe.coprocessor arguments <= imm12 & gpr(r) coprocessor <= exe end if 7.3.3.5 wait opcode the wait opcode synchronizes one or more coprocessors . the mask16 field (see the register bit list table in section 7.3.3 on page 187) is a bit mask (one bit per coproc essor) in which the bit number corresponds to the coprocessor number. the thread stalls until all coprocessors indicated by the mask complete their operations. priority can be released with this command. pseudocode: if reduction_or(mask16(i)=coprocessor.busy(i)) then pc <= stall else pc <= pc + 1 end if if p=1 then priorityowner(other thread)<= true else priorityowner(other thread)<= priorityowner(other thread) end if; ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 191 of 539 7.3.3.6 wait and branch opcode the wait and branch opcode synchronizes with one copr ocessor and branch on its one bit ok/ko flag. this opcode causes the thread to stall until the coprocessor represented by c# is no longer busy. the ok/ko flag is then compared with the field ok. if they are equal, the thread branches to the address in the target16 field. priority can be released with this command. pseudocode: if coprocessor.busy(c#)=1 then pc <= stall elsif coprocessor.ok(c#)=ok then pc <= target16 else pc <= pc+1 end if if p=1 then priorityowner(other thread)<= true else priorityowner(other thread)<= priorityowner(other thread) end if; ibm powernp np2g network processor preliminary embedded processor complex page 192 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 7.3.4 alu opcodes alu opcodes are used to manipulate gpr registers with arithmetic and logical functions. all of these opcodes execute in a single cycle. these opcodes are also used to manipulate the alu status flags used in condition execution of opcodes. all alu opcodes are ex ecuted conditionally based upon the cond field. 7.3.4.1 arithmetic immediate opcode the arithmetic immediate opcode performs an arithmetic function on a gpr register in which the second operand is a 12-bit immediate value. the word gpr operand and destination gpr are specified in the r field and the immediate operand is represented by imm4&imm8. the actual portion of the gpr and extension of the immediate operand are shown in the ot3i table. the arithmetic function performed is given in the aluop field. this aluop functions of and, or, xor, tst, and compare are not used with this opcode and have a different opcode when the second operand is an immediate value. arithmetic opcodes can be performed without changing the alu status flags if the i field is a 1. pseudocode: if (cond) then alu.opr1 <= gpr(r,ot3i) alu.opr2 <= ot3i(imm4&imm8) gpr(r,ot3i) <= aluop.result(alu.opr1,alu.opr2) if (i=0) then alustatus <= aluop.flags(alu.opr1, alu.opr2) end if end if type 313029282726252423222120191817161514131211109876543210 arithmetic immediate 1 0 0 0 i ot3i cond r imm12(11:8) aluop imm12(7:0) logical immediate 1 0 0 1 i h lop cond r imm16 compare immediate 1 0 1 0 0 0 ot2i cond r imm16 load immediate 1 0 1 1 ot4i cond r imm16 arithmetic/ logical register 1 1 0 0 i ot3r cond rd rs aluop 0 0 0 0wh nm count leading zeros 1 0 1 0 1hdwi cond rd rs 000000000hn0 ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 193 of 539 table 7-4. aluop field definition aluop function pseudocode flags modified zcnv 0000 add result = opr1 + opr2 x x x x 0001 add w/carry result = opr1 + opr2 + c x x x x 0010 subtract result = opr1 - opr2 x x x x 0011 subtract w/carry result = opr1 - opr2 - c x x x x 0100 xor result = orp1 xor opr2 x x 0101 and result = opr1 and opr2 x x 0110 or result = opr1 or opr2 x x 0111 shift left logical result = opr1 <-opr2 , fill with 0s c = c when opr2 = 0 else c = 0 when opr2 > n else c = opr1(n - opr2); where n = size of opr1 xxx 1000 shift right logical result = fill with 0, opr1 ->opr2 c = c when opr2 = 0 else c = 0 when opr2 > n else c = opr1(opr2 - 1); wher e n = size of opr1 xxx 1001 shift right arithmetic result = fill with s, opr1 ->opr2 c = c when opr2 = 0 else c = opr1(n - 1) when opr2 > n else c = opr1(opr2 - 1); wher e n = size of opr1 xxx 1010 rotate right result = fill with opr1, opr1 ->opr2 c = c when opr 2 = 0 else c= opr1(modn(opr2 - 1)); where n = size of opr1 xxx 1011 compare opr1 - opr2 x x x x 1100 test opr1 and opr2 x x 1101 not result = not(opr1) x x 1110 transfer result = opr2 1111 reserved reserved ibm powernp np2g network processor preliminary embedded processor complex page 194 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 figure 7-8. ot3i field definition gpr register ot3i field odd halfword gpr, 0 imm12 imm12 imm12 1 2 3 0 s byte hw 0 1 imm12 0 0 0 imm12 1 imm12 s s immediate field with 0 extend even halfword gpr, immediate field with 0 extend odd halfword gpr, immediate field with sign extend even halfword gpr, immediate field with sign extend word gpr, immediate field with 0 extend word gpr, immediate field with sign extend 01 2 3 ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 195 of 539 7.3.4.2 logical immediate opcode the logical immediate opcode performs the logical functions and, or, xor, and test on a gpr register in which the second operand is a 16-bit immediate value. the r field specifies the word gpr operand and desti- nation gpr, and the h field specifies the even (h = 0) or odd (h = 1) halfword of this gpr. the immediate operand is represented by imm16. the arithmetic func tion performed is given in the lop field. logical opcodes can be performed without changing the alu status flags if the i field is a 1. pseudocode: if (cond) then alu.opr1 <= gpr(r:h) alu.opr2 <= imm16 gpr(r:h) <= lop.result(alu.opr1,alu.opr2) if (i=0) then alustatus <= lop.flags(alu.opr1, alu.opr2) end if end if 7.3.4.3 compare immediate opcode the compare immediate opcode performs the compare functions on a gpr register in which the second operand is a 16-bit immediate value. the source gpr operand and destination gpr are specified in the r field, and the immediate operand is represented by imm16. the actual portion of the gpr and extension of the immediate operand are shown in figure 7-9 . the compare immediate opcode always changes the alu status flags. pseudocode: if (cond) then alu.opr1 <= gpr(r,ot2i) alu.opr2 <= ot2i(imm16) alustatus <= compare(alu.opr1, alu.opr2) end if table 7-5. lop field definition lop function pseudocode flags modified zcnv 00 xor result = orp1 xor opr2 x x 01 and result = opr1 and opr2 x x 10 or result = opr1 or opr2 x x 11 test opr1 and opr2 x x ibm powernp np2g network processor preliminary embedded processor complex page 196 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 7.3.4.4 load immediate opcode the operation arguments of the load immediate opcode are a combination of a gpr register and a 16-bit immediate field. the source gpr operand and destinati on gpr are specified by the r field and the immedi- ate operand is represented by imm16. the actual port ion of the gpr and extension of the immediate oper- and are shown in figure 7-10 and figure 7-11 . load immediate opcode never changes the alu status flags if executed. pseudocode: if (cond) then gpr(r,ot4i) <= ot4i(imm16) end if figure 7-9. ot2i field definition: compare halfword/word immediate gpr register ot2i field compare odd gpr register with immediate data 0 imm16 imm16 compare even gpr register with immediate data imm16 imm16 1 2 3 compare word gpr register with immediate data zero extend 0 s compare word gpr register with immediate data sign extend byte hw 0 1 01 2 3 ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 197 of 539 figure 7-10. ot4i field definition load immediate halfword/word gpr register ot5 field load odd halfword gpr from immediate data 0 imm16 load even halfword gpr from immediate data 1 load word gpr from immediate data zero extended load word gpr from immediate data 0 postpend load word gpr from immediate data byte hw 0 1 2 6 imm16 imm16 imm16 4 imm16 1 extended 5 imm16 load word gpr from immediate data 1 postpend 3 imm16 load word gpr from immediate data sign extended s 1 1 0 0 01 2 3 ibm powernp np2g network processor preliminary embedded processor complex page 198 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 figure 7-11. ot4i field definition: load immediate byte ot4i field load gpr byte 3 from low byte of immediate data 8 d load gpr byte 2 from low byte of 9 a b load gpr byte 1 from low byte of immediate data load gpr byte 0 from low byte of immediate data byte hw 0 1 d d d immediate data gpr register 01 2 3 ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 199 of 539 7.3.4.5 arithmetic register opcode the arithmetic register opcode performs an arithmetic function on a gpr register in which the second oper- and is also a gpr register. the first gpr operand and the destination gpr are specified by the word address r1 and the specific portion to be used is encoded in ot3r. the second operand source is represented by word address r2 with the h field determining the even or odd halfword if the ot3r field indicates a halfword is needed. if the aluop is a shift or rotate command, the second operand source is used as the amount of the shift or rotate. otherwise, ot3r indicates the relationship between the two operands. if the aluop is a logical operation (and, or, xor, test), the second operand source can then further be modified by the m and n fields. the m field is the mask field and, if active, crea tes a 1-bit mask in which the ?1? bit is represented by the second operand source. the n field is the invert field and, if active, will invert the second operand source. if both the m and n fields are ?1?, the mask is created before the inversion. table 7-6 show how to use these fields to create other operations from the basic logic commands. the arithmetic function performed is given in the aluop field. arithmetic opcodes can be performed without changing the alu status flags if the ?i? field is set to ?1?. arithmetic opcodes can be performed without writing back the data if the ?w? field is set to '1'. pseudocode: if (cond) then alu.opr1 <= gpr(r1,ot3r) alu.opr2 <= gpr(r2,h) if m=1 then alu.opr2 <= bitmask(alu.opr2) end if if n=1 then alu.opr2 <= not(alu.opr2) end if if 'w' = '0' then gpr(r2,ot3i) <= aluop.result(alu.opr1,alu.opr2) end if; if (i=0) then alustatus <= aluop.flags(alu.opr1, alu.opr2) end if end if table 7-6. arithmetic opcode functions function aluop m n bit clear and 1 1 bit set or 1 0 bit flip xor 1 0 ibm powernp np2g network processor preliminary embedded processor complex page 200 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 figure 7-12. ot3r field definition gpr (r1) register ot3r field odd halfword of 0 gpr2 even halfword of gpr r1 is operand1 gpr r2 is a halfword gpr2 gpr2 1 2 3 word gpr r1 is operand 1 zero extended 0 s word gpr r1 is operand 1 gpr r2 is halfword zero extend gpr2 word gpr r1 is operand 1 gpr r2 is a word byte hw 0 1 6 gpr r1 is operand1 gpr r2 is a halfword gpr r2 is halfword operand gpr2 01 2 3 ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 201 of 539 7.3.4.6 count leading zeros opcode the count leading zeros opcode returns the number of zero s from left to right until the first 1-bit is encoun- tered. this operation can be performed on a halfword or word gpr register. there is a second variation of this command in which the return value of this command is the bit position of the first ?1? from left to right in the gpr. the gpr to be analyzed is determined by the r fields. if the gpr is a halfword instruction, the h field indicates whether the even or odd half is used. the destination register is always a halfword register and is represented by the rd field and halfword indicator ?hd?. the w field indicates whether the operation is a word or halfword. the n field determines if the command counts the number of leading zeros (n = 0) or if the command returns the bits position of the first one (n = 1) . the only flag for this command is the overflow flag, which is set if the gpr being tested cont ains all zeros. the setting of this flag can be inhibited if the i field is a one. pseudocode: if (cond) then alu.opr1 <= gpr(rs,h) alu.result <= count_zero_left_to_right(alu.opr1) if n=1 then gpr(rd,hd) <= not(alu.result) else gpr(rd,hd) <= alu.result end if if (i=0) then alustatus <= aluop.flags(alu.opr1, alu.opr2) end if end if ibm powernp np2g network processor preliminary embedded processor complex page 202 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 7.4 dppu coprocessors each dppu coprocessor is a specialized hardware assist engine that runs in parallel with the two clps and performs functions that would otherwise require a la rge amount of serialized picocode. dppu functions include modifying ip headers, maintaining flow informatio n used in flow control algorithms, accessing internal registers via the cab, maintaining counts for flow control and for standard and proprietary management infor- mation blocks (mib), and enqueueing frames to be forwarded. the dppu coprocessors are: a thread?s address space is a distributed model in wh ich registers and arrays reside within the coprocessors (each coprocessor maintains resources for four threads and, for address mapping purposes, the clp is considered to be a coprocessor). each coprocessor can have a maximum of 252 scalar registers and four arrays. the address of a scalar register or array within the dppu becomes a combination of the coprocessor number and the address of the entity within the coprocessor. likewise, the coprocessor instruction is a combination of the coprocessor number and the coprocessor opcode. the epc coprocessors are numbered as shown in table 7-7 . the number is used in accesses on both the coprocessor execute and data interfaces. the tse is mapped to two coprocessor locations so that a thread can execute two searches simultaneously. tree search engine see section 8. tree search engine on page 285 . data store see section 7.4.2 beginning on page 203. control access bus (cab) interface see section 7.4.3 beginning on page 220. enqueue see section 7.4.4 beginning on page 223. checksum see section 7.4.5 beginning on page 241. string copy see section 7.4.6 beginning on page 246. policy see section 7.4.7 beginning on page 247. counter see section 7.4.8 beginning on page 248. coprocessor response bus see section 7.4.9 beginning on page 252. semaphore see section 7.4.10 beginning on page 253. ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 203 of 539 7.4.1 tree search engine coprocessor the tree search engine (tse) coprocessor has commands for tree management, direct access to the control store (cs), and search algorithms such as full match (fm), longest prefix match (lpm), and software- managed tree (smt). for complete in formation, see section 8. tree search engine on page 285 . 7.4.2 data store coprocessor the data store coprocessor provides an interface between the epc and the ingress data store, which contains frames that have been received from the media, and the egress data store, which contains reas- sembled frames received from the iew. the data store coprocessor also receives configuration information during the dispatch of a timer event or interrupt. each thread supported by the data store coprocessor ha s one set of scalar registers and arrays defined for it. the scalar registers control the accesses between the shared memory pool and the ingress and egress data stores. the data store coprocessor maintains them. the arrays are defined in the shared memory pool (see 7.2.4 shared memory pool on page 172): the datapool, which can hold eight quadwords two scratch memory arrays, which hold eight and four quadwords respectively the configuration quadword array, which holds port configuration data dispatched to the thread. the shared memory pool arrays function as a work area for the data store coprocessor: instead of reading or writing small increments (anything less than a quadword, or 16 bytes) directly to a data store, a larger amount (one to four quadwords per operation) of frame data is read from the data store into these shared memory pool arrays or from the these arrays into the data store. the data store coprocessor has nine commands available to it. these commands are detailed in section 7.4.2.2 data store coprocessor commands on page 210. table 7-7. coprocessor instruction format coprocessor number coprocessor 0 core language processor (clp) 1 data store interface 2 tree search engine 0 3 tree search engine 1 4 cab interface 5 enqueue 6 checksum 7 string copy 8policy 9 counter 10 coprocessor response bus (crb) 11 semaphore ibm powernp np2g network processor preliminary embedded processor complex page 204 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 7.4.2.1 data store coprocessor address map table 7-8. data store coprocessor address map (a thread?s scalar registers and arrays that are mapped within the data store coprocessor) (page 1 of 2) name register (array) 1 number size (bits) access description dsa x?00? 19 r/w address of ingress or egress data store. used in all commands except ?read more? and ?dirty?. (ingr ess uses the leas t significant 11 bits and egress uses all 19 bits for the address.) lma x?01? 6 r/w quadword address of shared memory pool. used in all commands except ?read more?. (see 7.2.4 shared memory pool on page 172.) ccta x?02? 19 r/w current address of the ingress data buffer or the egress twin that was dispatched to the thread into the datapool. used in ?read more? and ?dirty? commands. the value is unitized at dispatch and updated on ?read more? commands that pass though cell or twin boundaries. nqwa x?03? 3 r/w indicates the qw address used for both the datapool and the qw in the datastore buffer/twin. see edirty (update egress dirty quad- words) command on page 218 , idirty (update ingress dirty quad- words) command on page 219 , rdmoree (read more quadword from egress) command on page 215 , and rdmorei (read more quadword from ingress) command on page 217 for details. iprotocoltype x?04? 16 r layer 3 protocol identifier set by the hardware classifier (see 7.7 hardware classifier on page 264). dirtyqw x?05? 8 r/w quadwords in the datapool that have been written and therefore may not be equivalent to the corresponding data store data. used by the dirty update commands to write back any modified data into the corre- sponding data store. bci2byte x?06? 14/20 r/w a special-purpose register. the pico code running in the clp writes a bci value, but when the register is read, it returns the 14-bit byte count represented by the bci. the format of the bci can be changed by configuration (see section 13.3 bci format register on page 444). the bci value input to this register must match the configured format. disp_dsu x?07? 2 r/w initialized during dispatch to contai n the same value as the dsu field in the egress fcbpage. this register is used by egress write com- mands to determine which egress data store the data store copro- cessor should access when writing data. this register has no meaning for ingress frames. disp_dsusel x?08? 1 r/w initialized during dispatch to contain the same value as the dsu_sel field in the egress fcbpage. this register is used by egress read commands to determine which egress data store the data store coprocessor should access when reading data. this register has no meaning for ingress frames. disp_ingress x?09? 1 r dispatched frame?s type 0 egress frame 1 ingress frame 1. a number in parentheses is the array number for this coproc essor. each array has a register number and an array number. ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 205 of 539 the datapool and data store access upon frame dispatch, the dispatch unit automatically copies the first n quadwords of a frame from the data store into the first n quadword positions of the datapool. the value of n is programmable in the port config- uration memory. typically, values of n are as follows: the read more commands (rdmorei and rdmoree) assist the picocode?s reading of additional bytes of a frame by automatically reading the frame data into the datapool at the next quadword address and wrapping automatically to quadword 0 when the boundary of the da tapool is reached. the picocode can also read or write the ingress and egress data stores at an absolute address, independent of reading sequential data after a dispatch. the datapool for ingress frames for an ingress dispatch, the n quadwords are stored in the datapool at quadword-address 0, 1, ? n - 1. each quadword contains raw frame-bytes, (there are no cell header or frame headers for ingress frames in the datapool). after an ingress dispatch, the datapool contains the first n*16 bytes of the frame, where the first byte of the frame has byte address 0. the ingress datapool byte address definitions are listed in table 7-9 . bci2byte_wchk x?0e? 24 w the bci2byte_wchk write only regist er is added. bci values (the for- mat of which can be configured (see section 13.3 bci format regis- ter on page 444) written to this register are checked and a byte count value is generated. the results are read from the bc2byte register. when an invalid bci value is written, a result of zero is returned. an invalid bci is defined in one of the following ways: number of data buffers (weight) = 0 number of data buffers (weight) = 1 and ending byte location < starting byte location starting byte location or ending byte location < 6 configqw x?fc? (0) 128 r/w port configuration table entry for this frame scratchmem0 x?fd? (1) 512 r/w user defined array (use to store temporary information, build new frames, and so on) scratchmem1 x?fe? (2) 1024 r/w user defined array (use to store temporary information, build new frames, and so on) datapool x?ff? (3) 1024 r/w contains frame data from the dispatch unit n = 4 ingress frame dispatch n = 2 egress unicast frame dispatch n = 4 egress multicast frame dispatch n = 0 interrupts and timers table 7-8. data store coprocessor address map (a thread?s scalar registers and arrays that are mapped within the data store coprocessor) (page 2 of 2) name register (array) 1 number size (bits) access description 1. a number in parentheses is the array number for this coproc essor. each array has a register number and an array number. ibm powernp np2g network processor preliminary embedded processor complex page 206 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 when reading more than n quadwords of a frame (using the rdmorei command), the hardware automati- cally walks the data store?s buffer control block (bcb) chain as required. quadwords read from the data store are written to the datapool at consecutive quadword-locations, starting at quadword address n (where n is the number of quadwords written to the datapool by the dispatch unit during frame dispatch). the quad- word-address wraps from 7 - 0. therefore, the picocode must save quadword 0 in case it is required later (for example, the quadword can be copied to a scratch array). the ingress data store can also be written and read with an absolute address. the address is a bcb address. reading from an absolute address can be used for debugging and to inspect the contents of the ingress ds. for absolute ingress data store access (reads and writes), the picocode must provide the address in the ingress data store, the quadword address in the datapool, and the number of quadwords to be transferred. figure 7-13 shows an example of a frame stored in the ingress data store: table 7-9. ingress datapool byte address definitions quadword byte address 0 0123456789101112131415 1 16171819202122232425262728293031 2 32333435363738394041424344454647 3 48495051525354555657585960616263 4 64656667686970717273747576777879 5 80818283848586878889909192939495 6 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 7 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 207 of 539 the datapool for egress frames for an egress dispatch, the n quadwords are stored in the datapool at a starting quadword-address that is determined by where the frame header starts in the twin, which in turn depends on how the frame is packed in the iew cell and stored in the egress data store (see figure 7-14 ). general-purpose register (gpr) r0 is initialized during di spatch as shown in table 7-10: egress frames datapool quadword addresses on page 208. gpr r0 can be used as an index into the datapool so that the variability of the location of the start of the frame in the datapool is transparent to the picocode. figure 7-13. a frame in the ingress data store quadword a quadword b quadword c quadword d frame quadword a quadword b quadword c quadword d data quadword a quadword b quadword c quadword d frame data frame data cell address a0 cell address a1 cell address a2 ingress data store a1 a2 a0 (current buffer) a2 a1 bcbs ibm powernp np2g network processor preliminary embedded processor complex page 208 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 figure 7-14. frame in the egress data store (illustrating the effects of different starting locations) table 7-10. egress frames datapool quadword addresses frame start in twin buffer frame q uadword address in the datapool gpr r0 quadword a 0 0 quadword b 1 10 quadword c 2 26 quadword d 3 42 quadword a quadword b quadword c quadword d start quadword a ch ch ch ch quadword a quadword b quadword c quadword d quadword a quadword b quadword c quadword d quadword a quadword b quadword c quadword d quadword a quadword b quadword c quadword d start quadword b ch ch ch ch quadword a quadword b quadword c quadword d quadword a quadword b quadword c quadword d quadword a quadword b quadword c quadword d fh fh quadword a quadword b quadword c quadword d start quadword c ch ch ch ch quadword a quadword b quadword c quadword d quadword a quadword b quadword c quadword d quadword a quadword b quadword c quadword d fh quadword a quadword b quadword c quadword d start quadword d ch ch ch ch quadword a quadword b quadword c quadword d quadword a quadword b quadword c quadword d quadword a quadword b quadword c quadword d fh quadword a quadword b quadword c quadword d quadword a quadword b quadword c quadword d ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 209 of 539 the relationship between quadwords a, b, c, and d in the twin buffer and the location of the quadword in the datapool is always maintained. that is, quadword a is always stored at quadword address 0 or 4, quadword b is always stored at quadword address 1 or 5, quadwo rd c is always stored at quadword address 2 or 6, and quadword d is always stored at quadword address 3 or 7. in contrast with the ingress side, the egress datapool contains cell headers. when the exact content of the twin-buffer is copied into the datapool, it may include the 6-byte np2g cell header if the quadword being copied comes from quadword a in the twin buffer. the datapool can be accessed in two modes: normal datapool access: accesses all bytes in the datapool, including the 6-byte cell header. for example, it can be used for guided frames where information in the cell header may be important, or for debugging and diagnostics. cell header skip datapool access: automatically skips the cell header from the datapool. the hardware assumes a cell header to be present at quadword-address 0 and 4. for example, accessing datapool[2] accesses the byte with phys- ical address 8, datapool[115] accesses the byte wit h physical address 127, and datapool[118] also accesses the byte with physical address 8. the maximum index that can be used for this access mode is 231. this mode is shown in table 7-11 . fewer frame-bytes may be available in the datapool for the egress due to the presence of cell headers. table 7-12 shows the number of frame-bytes in the datapool after a frame dispatch. table 7-11. datapool byte addressing with cell header skip quadword byte address 0 ?????? 0 116 1 117 2 118 3 119 4 120 5 121 6 122 7 123 8 124 9 125 1 10 126 11 127 12 128 13 129 14 130 15 131 16 132 17 133 18 134 19 135 20 136 21 137 22 138 23 139 24 140 25 141 2 26 142 27 143 28 144 29 145 30 146 31 147 32 148 33 149 34 150 35 151 36 152 37 153 38 154 39 155 40 156 41 157 3 42 158 43 159 44 160 45 161 46 162 47 163 48 164 49 165 50 166 51 167 52 168 53 169 54 170 55 171 56 172 57 173 4 ?????? 58 174 59 175 60 176 61 177 62 178 63 179 64 180 65 181 66 182 67 183 5 68 184 69 185 70 186 71 187 72 188 73 189 74 190 75 191 76 192 77 193 78 194 79 195 80 196 81 197 82 198 83 199 6 84 200 85 201 86 202 87 203 88 204 89 205 90 206 91 207 92 208 93 209 94 210 95 211 96 212 97 213 98 214 99 215 7 100 216 101 217 102 218 103 219 104 220 105 221 106 222 107 223 108 224 109 225 110 226 111 227 112 228 113 229 114 230 115 231 ibm powernp np2g network processor preliminary embedded processor complex page 210 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 for example, when 24 bytes of frame data are always needed, the port configuration memory must be programmed with the n (number of quadwords to dispatch) equal to two. when 32 bytes are always needed, the number of quadwords to dispatch must be set to three. after a dispatch, picocode can use the rdmoree command when more frame data is required. one, two, three, or four quadwords can be requested. consult the ?guaranteed? column in table 7-12 to translate the necessary number of bytes into the greater number of quadwords that must be read. for example, if the pico- code must dig into the frame up to byte 64, five quadwords are required. in this example, the number of quad- words specified with the rdmoree command equals 5 - n, where n is the number of quadwords initially written in the datapool by the dispatch unit. as a general rule, each set of four quadwords provides exactly 58 bytes. 7.4.2.2 data store coprocessor commands the data store coprocessor provides the following commands: table 7-12. number of frame-bytes in the datapool number of quadwords read start quadword a start quadword b start quadword c start quadword d guaranteed 1 10161616 10 2 26323226 26 3 42484242 42 4 58585858 58 5 68747474 68 6 84909084 84 7 100 106 100 100 100 8 116 116 116 116 116 command opcode description wreds 0 write egress data store. enables the clp to read data from one of the arrays in the shared memory pool (datapool and scratch memory array) and write it to the egress data store (in multiples of quad- words only). for more information, see wreds (write egress data store) command on page 212. rdeds 1 read egress data store. enables the clp to read data from the egress data store and write it into one of the arrays in the shared memory pool (in multiples of quadwords only). for more information, see rdeds (read egress data store) command on page 213. wrids 2 write ingress data store. enables the clp to write data to the ingress data store (in multiples of quad- words only). for more information, see wrids (write ingress data store) command on page 214. rdids 3 read ingress data store. enables the clp to read dat a from the ingress data store (in multiples of quadwords only). for more information, see rdids (read ingress data store) command on page 214. ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 211 of 539 note: the egress data store has a longer access time than the ingress data store. for better performance, as much frame parsing should be done on the ingress side as possible. rdmoree 5 read more frame data from the egress data store. a hardware assisted read from the egress data store. rdmoree continues reading the frame from where the dispat ch or last ?read more? command left off and places the data into the datapool. as dat a is moved into the datapool, the hardware tracks the current location in the frame that is being read and captures the link pointer from the twin buffers in order to determine the address of the next twin buffe r. this address is used by the hardware for subse- quent rdmoree requests until the twin is exhausted and the next twin is read. since the datapool is essentially a map of a twin's content, the frame data might wrap within the datapool; the picocode keeps track of the data?s location within the datapool. for more information, see edirty (update egress dirty quadwords) command on page 218 rdmorei 7 read more frame data from the ingress data store. a hardware assisted read from the ingress data store. rdmorei continues reading the frame from where the dispatch or last ?read more? command left off and places the data into the datapool. as dat a is moved into the datapool, the hardware tracks the current location in the frame that is being read and captures the link maintained in the buffer control block area in order to determine the address of the frame?s next data buffer. this address is used by the hardware for subsequent rdmorei requests until the data buffer is exhausted and the next buffer is read. the picocode keeps track of the frame data?s location within the datapool. for more information, see rdmorei (read more quadword from ingress) command on page 217. leasetwin 8 lease twin buffer. returns the address of a free tw in buffer. use this command when creating new data in the egress data store. for more information, see 7.4.3 control access bus (cab) coprocessor on page 220 edirty 10 update dirty quadword egress data store. the copr ocessor keeps track of the quadwords within the current twin that have been modified in the datapool array. edirty enables the clp to write only the ?dirty? data back to the egress data store (in mult iples of quadwords only). this command is only valid within the datapool array and for the buffer repres ented by the scalar register current cell/twin address. for more information, see edirty (update egress dirty quadwords) command on page 218 idirty 12 update dirty quadword ingress data store. the c oprocessor keeps track of the quadwords within the current buffer that have been modified in the datapool array. idirty enables the clp to write only the ?dirty? data back to the ingress data store (in mult iples of quadword units only). this command is only valid within the datapool array and for the buffer re presented by the scalar register current cell/twin address. for more information, see idirty (update ingress dirty quadwords) command on page 219 command opcode description ibm powernp np2g network processor preliminary embedded processor complex page 212 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 wreds (write egress data store) command wreds writes to an absolute address in the egress data store. it can be specified if the quadwords are written to ds0, ds1, both ds0 and ds1, based on twin format when toggle mode is enabled, or if the deci- sion is made automatica lly by information in the dispatch dsu register. the data store address can be any address in the egress data store, but the picocode must ensure that no twin overflow occurs during writing. for example, it is not a good idea to make the lma point to the last quad- word in a 64-byte buffer and set nrofquadword to four. table 7-13. wreds input name size operand source description direct indirect nrofquadword 2 imm16(1..0) gpr(1..0) defines the number of quadwords to be written: 01 1 quadword 10 2 quadwords 11 3 quadwords 00 4 quadwords dscontrol 2 imm16(3..2) imm12(3..2) defines if the quadwords are written to ds0, ds1, or both when toggle mode is disabled: 00 writes to the default dsu 01 writes to ds0 10 writes to ds1 11 writes to ds0 and ds1 when toggle mode is enabled: 00 uses the twin format determined at dispatch and cap- tured in the disp_dsu 01 forces twin format 0 10 forces twin format 1 11 invalid disp_dsu 2 r the default dsu, initialized at dispatch. dsa 19 r data store address. the target twin address in the egress data stores. the starting qw destination within the twin is determined by the 3 low-order bits of the lma. 000 - 011 qw 0-3 of the first buffer of the twin. 100 - 111 qw 0-3 of the second buffer of the twin. lma 6 r local memory address. the quadword source address in the shared memory pool (see 7.2.4 shared memory pool on page 172). table 7-14. wreds output name size operand source description direct indirect lma 6 r local memory address. the lma will be the input value of the lma incremented by the number of quadword transfers com- pleted by the command. ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 213 of 539 rdeds (read egress data store) command rdeds reads from an absolute address in the egress data store. it can be specified if the quadwords are read from ds0 or ds1, based on twin format when toggle mode is enabled, or if this decision is made auto- matically by information in the dispatch dsu register. when dscontrol is set to 00, the quadwords are read from the default ds or the default twin format when toggle mode is enabled, which is determi ned based on the dispatch dsusel field. table 7-15. rdeds input name size operand source description direct indirect nrofquadword 2 imm16(1..0) gpr(1..0) defines the number of quadwords to be read: 01 1 quadword 10 2 quadwords 11 3 quadwords 00 4 quadwords dscontrol 2 imm16(3..2) imm12(3..2) defines if the quadwords are r ead from ds0 or ds1 when tog- gle mode is disabled: 00 reads from the default ds 01 reads from ds0 10 reads from ds1 11 reserved when toggle mode is enabled: 00 uses the twin format determined at dispatch and cap- tured in the disp_dsusel 01 forces twin format 0 10 forces twin format 1 11 invalid disp_dsusel 1 r indicates the default ds chosen at dispatch. when toggle mode is disabled: 0ds0 1ds1 when toggle mode is enabled (see section 13.2 toggle mode register on page 444), indicates the twin format: 0 twin format 0 1 twin format 1 dsa 19 r data store address. the source address in the egress data store. lma 6 r local memory address. the quadword target address in the shared memory pool (see 7.2.4 shared memory pool on page 172). ibm powernp np2g network processor preliminary embedded processor complex page 214 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 wrids (write ingress data store) command wrids writes to an absolute address in the ingress data store. the data store address (dsa) can be any address in the ingress data store but the picocode must ensure that no buffer overflow occurs during writing. for exampl e, it is not a good idea to make the dsa point to the last quadword in a 64-byte buffer and set nrofquadword to four. rdids (read ingress da ta store) command rdids reads from an absolute address in the ingress data store. table 7-16. rdeds output name size operand source description direct indirect ok/ko 1 flag ko - an error occurred when reading the fourth quadword of a twin buffer indicating the link pointer contained in the data had a parity error. ok - indicates that the link pointer had valid parity or that the link pointer wasn't read on this access. lma 6 r local memory address. the lma will be the input value of the lma incremented by the number of quadword transfers com- pleted by the command. table 7-17. wrids input name size operand source description direct indirect nrofquadword 2 imm16(1..0) gpr(1..0) defines the number of quadwords to be written: 01 1 quadword 10 2 quadwords 11 3 quadwords 00 4 quadwords dsa 19 r data store address. the target address in the ingress data store. the 11 lsbs of the dsa contain the address. the remaining eight msbs are not used. lma 6 r local memory address. the quadword source address in the shared memory pool (see 7.2.4 shared memory pool on page 172). table 7-18. wrids output name size operand source description direct indirect lma 6 r local memory address. the lma will be the input value of the lma incremented by the number of quadword transfers com- pleted by the command. ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 215 of 539 the data store address (dsa) can be any address in the ingress data store. the picocode must ensure that no buffer overflow occurs during reading. for example, it is not a good idea to make the dsa point to the last quadword in a 64-byte buffer and set nrofquadword to four. rdmoree (read more quadword from egress) command after an egress frame dispatch, the hardware stores the first n quadwords of the frame in the datapool. rdmoree is used to read more quadwords from the egress data store. it uses three internal registers that are maintained by the data store coprocessor hardware (dispatch dsusel, current cell/twin address, and next quadword address registers) to maintain the current position in the egress data store and the shared memory pool. during a rdmoree, the hardware automatically reads the link pointer to update the current/ cell twin register when a twin boundary is crossed. the rdmoree can be executed more than once if more quadwords are required. table 7-19. rdids input name size operand source description direct indirect nrofquadword 2 imm16(1..0) gpr(1..0) defines the number of quadwords to be read: 01 1 quadword 10 2 quadwords 11 3 quadwords 00 4 quadwords dsa 19 r data store address. the source address in the ingress data store lma 6 r local memory address. the quadword target address in the shared memory pool (see 7.2.4 shared memory pool on page 172). table 7-20. rdids output name size operand source description direct indirect lma 6 r local memory address. the lma will be the input value of the lma incremented by the number of quadword transfers com- pleted by the command. ibm powernp np2g network processor preliminary embedded processor complex page 216 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 table 7-21. rdmoree input name size operand source description direct indirect nrofquadword 2 imm16(1..0) gpr(1..0) defines the number of quadwords to be read. 01 1 quadword 10 2 quadwords 11 3 quadwords 00 4 quadwords dscontrol 2 imm16(3..2) imm12(3..2) defines if the quadwords are r ead from ds0 or ds1 when tog- gle mode is disabled: 00 reads from the default ds 01 reads from ds0 10 reads from ds1 11 reserved when toggle mode is enabled: 00 uses the twin format determined at dispatch and cap- tured in the disp_dsu 01 forces twin format 0 10 forces twin format 1 11 invalid disp_dsusel 1 r indicates the default ds chosen at dispatch when toggle mode is disabled: 0ds0 1ds1 when toggle mode is disabled (see section 13.2 toggle mode register on page 444), indicates the twin format: 0 twin format 0 1 twin format 1 ccta 19 r current cell/twin address. contains the twin source address in the egress data store. this regist er is initialized at dispatch to point to the current twin fetched at dispatch. nqwa 3 r next quadword address. the conten ts of this register indicates both the target quadword address in the datapool as well as the source quadword of the twin buffer. this register is initialized at dispatch to point to the next qw after the data fetched at dis- patch. table 7-22. rdmoree output name size operand source description direct indirect ok/ko 1 flag ko - an error occurred when reading the fourth quadword of a twin buffer indicating that the link pointer contained in the data had a parity error. ok - indicates that the link pointer had valid parity or that the link pointer wasn't read on this access. ccta 19 r current cell/twin address. th is register is updated by hard- ware. executing rdmoree again reads the next quadwords from egress data store. nqwa 3 r next quadword address. this re gister is updated by hardware. executing rdmoree again caus es the quadwords being read to be stored in the next locations in the datapool. ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 217 of 539 rdmorei (read more quadword from ingress) command after an ingress frame dispatch, the hardware stores the first n quadwords of the frame in the datapool. rdmorei is used to read more quadwords from the ingress data store. it uses two internal registers that are maintained by the data store coprocessor hardware (current cell/twin address and next quadword address registers) to maintain the current position in the ingress data store and the shared memory pool. during a rdmorei, the hardware automatically reads the bcb to update the current/cell twin register when a cell-boundary is crossed. rdmorei can be executed more than once if more quadwords are required. leasetwin command this command leases a 19-bit twin address from the egress pool of free twins. table 7-23. rdmorei input name size operand source description direct indirect nrofquadword 2 imm16(1..0) gpr(1..0) defines the number of quadwords to be read. 01 1 quadword 10 2 quadwords 11 3 quadwords 00 4 quadwords ccta 19 r current cell/twin address. cont ains the source ingress data buffer address in the ingress data st ore. this register is initial- ized at dispatch to point to the next data buffer after the data fetched at dispatch. nqwa 3 r next quadword address. the conten ts of this register indicates both the target quadword address in the datapool as well as the source quadword of the ingress data buffer. the low two bits indicate the qw in the ingress data buffer, while all three bits are used to indicate the qw in t he datapool. this register is ini- tialized at dispatch to point to the next qw after the data fetched at dispatch. table 7-24. rdmorei output name size operand source description direct indirect ccta 19 r current cell/twin address. this register is updated by hard- ware. executing rdmoree again reads the next quadwords from egress data store. nqwa 3 r next quadword address. this r egister is updated by hardware. executing rdmoree again causes the quadwords being read to be stored in the next locations in the datapool. ibm powernp np2g network processor preliminary embedded processor complex page 218 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 edirty (update egress dirty quadwords) command edirty writes a quadword from the datapool array to the egress data store if the quadword has been modi- fied since being loaded into the datapool by a dispatch or a rdmoree command. the data store copro- cessor maintains a register (dirty quadword) which indicates when a quadword within the datapool has been modified. the edirty command uses the dispatch dsu register to determine which egress data store (ds0, ds1, or both) must be updated. when the current cell/twin address is modified due to a rdmoree command, all dirty bits are cleared, indicating no quadwords need to be written back to the egress data store. table 7-25. leasetwin output name size operand source description direct indirect ok/ko 1 flag ko - no twins are currently available. ok - the command was successful. ccta 19 r current cell/twin address. contains the address of the newly leased twin. table 7-26. edirty inputs name size operand source description direct indirect ccta 19 r current cell/twin address. contains the twin target address in the egress data store. nqwa 3 r next quadword address. the contents of this register indicates which qws are considered for edirty processing. nqwa datapool qw target twin qw 07-0 7-0 10 0 21-0 1-0 32-0 2-0 43-0 3-0 54-0 4-0 65-0 5-0 76-0 6-0 ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 219 of 539 idirty (update ingress dirty quadwords) command idirty writes a quadword from the datapool array to the ingress data store if the quadword has been modi- fied since being loaded into the datapool by a dispatch or a rdmorei command. the data store copro- cessor maintains a register (dirty quadword) which indicates when a quadword within the datapool has been modified. the idirty command uses the next quad word address to determine which cell within the datapool is represented by the current cell/twin address. when the current cell/twin address is modified due to a rdmorei command, all dirty bits are cleared, indicating no quadwords need to be written back to the ingress data store. dirtyqw 8 r indicates which quadwords need to be updated dscontrol 2 imm16(3..2) imm12(3..2) defines if the quadwords are written to ds0, ds1, or both when toggle mode is disabled: 00 writes to the default dsu 01 writes to ds0 10 writes to ds1 11 writes to ds0 and ds1 when toggle mode is enabled: 00 uses the twin format determined at dispatch and cap- tured in the disp_dsu 01 forces twin format 0 10 forces twin format 1 11 invalid disp_dsu 2 r the default dsu, initialized at dispatch, when toggle mode is disabled: 00 invalid 01 ds0 10 ds1 11 both ds0 and ds1 when toggle mode is enabled: 00 invalid 01 twin format 0 10 twin format 1 11 invalid table 7-27. edirty output name size operand source description direct indirect dirtyqw 8 r dirty quadwords. bits which represent the data quadwords that were updated on this command will be reset to ?0?. table 7-26. edirty inputs name size operand source description direct indirect ibm powernp np2g network processor preliminary embedded processor complex page 220 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 7.4.3 control access bus (cab) coprocessor the cab coprocessor provides interfaces to the cab arbiter and the cab for a thread. a thread must load the operands for a cab access, such as cab address and data. the protocol to access the cab is then handled by the cab interface coprocessor. 7.4.3.1 cab coprocessor address map the cab coprocessor has three scalar registers that are accessible to a thread and are shown in table 7-30 : table 7-28. idirty inputs name size operand source description direct indirect ccta 19 r current cell/twin address. the source address in the ingress data store. initially, this r egister is set during a dispatch. nqwa 3 r next quadword address. the conten ts of this register indicates which qw are considered for action by the idirty command. nqwa datapool qw target ingress data buffer qw 07-4 3-0 10 0 21-0 1-0 32-0 2-0 43-0 3-0 54 0 65-4 1-0 76-4 2-0 dirtyqw 8 r indicates which quadwords need to be updated table 7-29. idirty output name size operand source description direct indirect dirtyqw 8 r dirty quadwords. bits which represent the data quadwords that were updated on this command will be reset to ?0?. table 7-30. cab coprocessor address map symbolic register name register nu mber size (bits) access description cabstatus x?00? 3 r status register bit 2 busy bit 1 0 = write access 1 = read access bit 0 arbitration granted cabdata x?01? 32 r/w data to be written to cab, or data read from cab cabaddress x?02? 32 w address used during last cab access ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 221 of 539 7.4.3.2 cab access to np2g structures the control address bus (cab) is the np2g's facility for accessing internal register s. the cab is assessable via picocode and is used for both configuration and operational functions. cab addresses consist of three fields and are defined as follows: the first field, which is comprised of the five most signi ficant bits of the address, selects one of 32 possible functional islands within the device. the correspondenc e between the encoded functional island value and the functional island name is shown in the cab address, functional island encoding table below. although some functional islands have island_id values, they are not accessed via the cab. these functional islands are the ingress data store, egress data store, and control store. structures in these functional islands are accessed via the data store coprocessor and the tse. table 7-31. cab address field definitions island id structure address element address word addr 5234 32 table 7-32. cab address, functional island encoding island_id functional island name notes ?00000? ingress data store 1 ?00001? ingress pmm ?00010? ingress eds ?00011? ingress sdm ?00100? embedded processor complex ?00101? spm ?00110? ingress flow control ?00111? embedded powerpc ?01000? control store 1 ?01111? reserved ?10000? egress data store 1 ?10001? egress pmm ?10010? egress eds ?10011? egress sdm ?10100? configuration registers ?10101? reserved ?10110? egress flow control ?10111-11111? reserved 1. these functional islands are not accessible via the cab ibm powernp np2g network processor preliminary embedded processor complex page 222 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 the second portion of the cab address consists of the ne xt most significant 23 bits. this address field is segmented into structure address and element address. the number of bits used for each segment can vary from functional island to functional island. some functio nal islands contain only a few large structures while others contain many small structures. the structure address addresses an array within the functional island while the element address addresses an element within the array. the data width of an element is variable and can exceed the 32-bit data width of the cab. the third portion of the cab address consists of a 4-bit word address for selecting 32-bit segments of the element addressed. this address is necessary for movi ng structure elements wider than 32-bits across the cab. 7.4.3.3 cab coprocessor commands the cab coprocessor provides the following commands: cabarb (cab arbitration) command cabarb requests to become a master on the cab interface or requests to release the cab after master status has been grante d. cabarb does not cause a stall in the clp even if run synchronously. the cab coprocessor a lways indicates that cabarb was ex ecuted immediately, even if the arbiter did not grant the cab interface to the coprocessor. the picocode must release ownership of the cab interface when it is finished accessing the cab or a lockout condition could occur for all non-preempt accesses. command opcode description cabarb 0 cab arbitration. used by a thre ad to gain access to the cab. once access is granted, that thread maintains control of the cab until it releases the cab. for more information, see cabarb (cab arbitration) command on page 222 cabaccess 1 access cab. moves data onto or from the cab and the attached cab accessible registers. the source and destination within the dppu are gprs. for more information, see cabaccess command on page 223 cabpreempt 3 preempt cab. used only by the gfh thread, it enables the gfh to gain control of the cab for a single read/write access, even if the cab has already been granted to another thread. for more information, see cabpreempt command on page 223 table 7-33. cabarb input name size operand source description direct indirect start_nend 1 imm16(0) 1 start arbitration 0 release arbitration ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 223 of 539 cabaccess command performs a read or write access on the cab. before a cab access can be performed, a cabarb command must have been issued to acquire ownership of the cab interface. cabpreempt command cabpreempt has the same in put and output paramete rs as cabaccess, except that a high-priority access to the cab is performed. no cabarb co mmand is required before cabpreempt. if any other coprocessor is cab bu s master (because it previously executed a cabarb) , cabpreempt takes control of the cab bus and executes the cab read or write. afte r command execution, control of the cab bus returns to the previous owner. use cabpreempt with care. for example, it might be used in debug mo de when the gfh is single stepping one or more other coprocessors. to give a single step command, a cab write must be executed using the cabreempt command because the c oprocessor being sing le stepped may be executing a cabaccess command and become cab bus master. if the gf h used the cabaccess command instead of cabpre- empt, a deadlock would occur. 7.4.4 enqueue coprocessor the enqueue coprocessor manages the interface between a thread and the completion unit and manages the use of the fcbpage that is maintained in the shared memory pool. each thread has three fcbpage locations in which enqueue information about a frame may be maintained. two of the pages improve the performance of the completion unit interface when t hey are alternated during consecutive enqueues. the picocode written for the thread does not differentia te between these two pages because hardware manages the swap. the thread uses the third page to allow the picocode to create new frames. when a thread issues an enqueue command, the first fc bpage is marked as in-use. if the other fcbpage is available, the coprocessor is not co nsidered ?busy? and will not stall the clp even if the command was issued synchronously. the completion unit fetches the fcbpage from the shared memory pool through the enqueue coprocessor and provides its information to the eds (either ingress or egress as indicated by the enqueue command). the fcbpage is then marked as free. if both fcbpages are marked in use, the enqueue coprocessor is considered busy and stalls the clp if a synchronous command initiated enqueue. to guarantee that fcbpage data is not corrupted , enqueue commands must always be synchronous. table 7-34. cabaccess input name size operand source description direct indirect read_nwrite 1 imm12(0) 1 perform a cab read 0 perform a cab write address 32 gpr(31..0) the cab address cabdata 32 r load for cab write command table 7-35. cabaccess output name size operand source description direct indirect cabdata 32 r set for cab read command ibm powernp np2g network processor preliminary embedded processor complex page 224 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 note: when an enqueue command is issued and the other location of the fcbpage becomes the ?active? page, the data is not transferred between the fcbpages and should be considered uninitialized. this is an important consideration for picocode written to handle egress multicast frames. 7.4.4.1 enqueue coprocessor address map fcbpage format the fcbpage contains dispatch and enqueue informati on (fields) and is stored in three fcbpage arrays (activefcbpage1, inactivefcbpage2, and fcbpage2). there are two fcbpage formats, ingress and egress. the fcbpage format defines fields on byte boundaries. information that is not an integral number of bytes is right-justified in a field sized to accommodate the information. since the fcbpage is stored in arrays within the shared memory pool, fields within the fcbpage can be accessed using all of the standard methods of accessing arrays. table 7-36. enqueue coprocessor address map name register address s ize access description disp_label x?00? 1 r/w indicates whether a label was di spatched to the completion unit for this frame. if the nolabel parameter is not passed during an enqi or enqe command, then this bit is used to determine if the enqueue will be done with or without a label. 0 indicates that a label was not passed to the completion unit for this frame. 1 indicates that a label was passed to the completion unit for this frame. activefcbpage1 x?fc? 384 r/w active fcb page for the current thread. this page is initialized at dispatch. inactivefcbpage1 x?fd? 384 r/w inactive fcb page for the current thread. this page is not ini- tialized at dispatch. this ar ray should never be written. fcbpage2 x?fe? 384 r/w alternate fcbpage ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 225 of 539 figure 7-15. ingress fcbpage format 01234567 sp (6) abort (1) gt (1) fcinfo (4) wbc (15) fcba (12) 8 9 10 11 12 13 14 15 currentbuffer (11) not used (8) not used (8) tdmu (2) l3stk/idsu (8/4) pib (6) tos (8) 16 17 18 19 20 21 22 23 reserved (16) iucnmc (1) priority_sf (2) lid / mid (21 / 17) 24 25 26 27 28 29 30 31 vlanhdr (16) ins_ovlvlan (2) fhf (4) fhe (32) 32 33 34 35 36 37 38 39 not used (8) not used (8) not used (8) not used (8) not used (8) not used (8) not used (8) not used (8) 40 41 42 43 44 45 46 47 countercontrol (14) counterdata (16) counterblockindex (20) table 7-37. ingress fcbpage description (page 1 of 3) field fcb page offset initialized by dispatch unit enqueue info size (bits) description sp x?00? y n 6 source port is the port ident ifier where this frame was received. abort x?01? y n 1 aborted frame indicates that the frame had been marked abort at the time of dispatch. gt x?02? y n 1 guided traffic indicator. this bit must be set to ?1? when the frame is guided traffic. fcinfo x?03? y y 4 flow control color and frame drop information. see table 7-89: flow control information values on page 269. setting this field to x?f? disables flow control. flow control must be disabled when enqueing to the gdq, gfq, or the discard queue. wbc x?04? y n 15 working byte count. this is the nu mber of bytes available in the ingress data store for this frame at the time it was dispatched. fcba x?06? y y 11 frame control block address for the frame dispatched currentbuffer x?08? y y 11 ingress data store buffer address of the frame dispatched tdmu x?0c? n y 2 egress target dmu. encode is tdmu(1:0) dmu 00 a 01 reserved 10 c 11 d ibm powernp np2g network processor preliminary embedded processor complex page 226 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 l3stk/idsu x?0d? n y 8/4 l3stk (8-bit field). when iucnmc = 0 (frame is multicast), this field contains the value of the d ll termination offset. the dll ter- mination offset is defined as the number of bytes starting at the beginning of the frame to the position one byte beyond the end of the data link layer. this val ue is based upon the encapsulation type. typically, this is the same as the start of the layer 3 protocol header, an exception would be for mpls. idsu (4-bit field). data store unit field in the frame header. indi- cates where the frame should be stored when entering the egress side when toggle mode is disabled. when iucnmc = 1 (frame is unicast). when set to 0, hardware determines the value of the data store unit field by using t he value of the tdmu field and con- tents of the ingress tdmu data storage map register (i_tdmu_dsu) (see 13.13 ingress target dmu data storage map register (i_tdmu_dsu) on page 459). pib x?0e? n y 6 point in buffer. prior to enqueue, indicates location of the first byte of the frame to be sent across the iew. tos x?0f? y y 8 if the frame is an ip frame these bi ts will be the tos field in the ip header, otherwise they will be initialized to 0?s. for differentiated services, the following subfields are defined: 7:5 af class. bits are used by the flow control hardware when addressing the trans mit probability table. 4:2 drop precedence 1:0 cu (currently unused). reserved x?10? n y 16 reserved. iucnmc x?12? n y 1 unicast/multicast indicator 0 multicast frame 1 unicast frame priority_sf x?13? n y 2 priority and special fiel d indicators defined as: bit description 0 special field. when set to ?1?, indicates enqueues to the discard queue, gdq, or i-gfq. this is normally set by hardware when the qclass is used in the enqi com- mand. flow control is disabled when this field is set to ?1?. 1 priority. ingress sc heduler priority indi cates the user pri- ority assigned to the frame. hi gh priority is indicated by a value of 0. lid/mid x?14? n y 21/17 lookup id (21-bit field). ingress pi cocode uses to pass information to the egress picocode. used when iucnmc = 1 (frame is uni- cast). multicast id (17-bit field). ingr ess picocode uses to pass informa- tion to the egress picocode. used when iucnmc = 0 (frame is multicast). vlanhdr x?18? n y 16 vlan header. this is the tag control information field defined in the ieee 802.3 standard. ins_ovlvlan x?1a? n y 2 insert or overlay vlan. indicates if the vlan header provided in the vlanhdr scalar register is in serted or overlays an existing vlan tag. bit description 0 overlay vlan 1 insert vlan table 7-37. ingress fcbpage description (page 2 of 3) field fcb page offset initialized by dispatch unit enqueue info size (bits) description ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 227 of 539 fhf x?1b? n y 4 frame header format. 4-bit field us ed by hardware and set up by picocode. hardware classifier us es this value on the egress side to determine the starting instruction address for the frame. fhe x?1c? n y 32 frame header extension. a 4-byte field whose contents are defined by picocode. countercontrol x?28? n y 14 passed to flow control for de layed counter manager functions. bits description 13 when set to 1 enables counter operation for this enqueue. counter updates on an enqueue work only when the target is the egress side. counter updates do not occur when enqueueing to the gdq, gfq, or the dis- card queue. 12 add/increment 11:8 counter number 7:0 counter definition table index counterdata x?2a? n y 16 data passed to ingress flow c ontrol for delayed counter manager add functions counterblockindex x?2c? n y 20 block index passed to ingress fl ow control for delayed counter manager functions table 7-37. ingress fcbpage description (page 3 of 3) field fcb page offset initialized by dispatch unit enqueue info size (bits) description ibm powernp np2g network processor preliminary embedded processor complex page 228 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 figure 7-16. egress fcbpage format 01234567 mpls_3 (8) eucmc (3) dsusel(1) mpls_4 (8) fcinfo (4) bci (20/24) 8 9 10 11 12 13 14 15 currtwin (20) type (3) mpls_5 (8) dsu (2) qhd (1) ow (7) 16 17 18 19 20 21 22 23 qid (20) etypeact (3) etypevalue (16) datafirsttwin (19) 24 25 26 27 28 29 30 31 saptr (10) da47_32 (16) da31_0 (32) daptr (6) saptr (6) mpls_6 (8) mpls_7 (6) mpls_8 (8) mpls_9 (8) mpls_10 (8) mpls_11 (8) 32 33 34 35 36 37 38 39 en_hwa (6) vlan_mpls _hwa (5) crcaction (2) dllstake (6) ttlassist (2) mpls_0 (8) mpls_1 (8) mpls_2 (8) 40 41 42 43 44 45 46 47 countercontrol (14) counterdata (16) counterblockindex (20) ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 229 of 539 table 7-38. egress fcbpage description (page 1 of 7) field fcb page offset initialized by dispatch unit size (bits) description mpls_3 x?00? n 8 mpls insert byte 3 of 11. enables insertion of an mpls label of up to 12 bytes. the data is inserted prior to t he byte in the received frame indicated by the dllstake. the number of bytes inserted (starting at mpls_0) is con- trolled by the expanded vlan_mpls_hwa. eucmc x?01? y 3 egress unicast/multicast bits 000 unicast the frame is enqueued a single time. the twins used to hold the data for this frame are re leased to the free pool after trans- mission. 001 first multicast the first enqueue for a frame that is enqueued multiple times. the frame data is not replicated; all in stances of the frame transmission use the same source in the data store, but frame alterations might be different. the last instance of the multicast frame to be transmit- ted releases the twins back to the free pool. 010 middle multicast the middle enqueues for a frame that is enqueued multiple times. there may not be a middle frame if the frame is not transmitted more than twice. 011 last multicast the last enqueue for a frame that is enqueued multiple times. 100 unicast static frame enqueue the frame is enqueued a single time. the twins used to hold the data are not released to the free pool after transmission. 101 first multicast static framesimil ar to '001', but the twins used to hold the data are not released to the free pool. 110 middle multicast static framesimilar to '010', but the twins used to hold the data are not released to the free pool. 111 last multicast static framesimilar to '011', but the twins used to hold the data are not released to the free pool. dsusel x?02? y 1 this field is initialized to indicate which dsu was used on dispatch but is not read back by hardware. to override the dsu, the picocode must use the disp_dsu or disp_dsusel registers. (see table 7-8 on page 204.) when toggle mode is disabled: 0 ds0 1 ds1 when toggle mode is enabled, fram e data is placed into ds0 and ds1 based on twin format: 0 twin format 0 1 twin format 1 mpls_4 x?02? n 8 mpls insert byte 4 of 11. enables insertion of an mpls label of up to 12 bytes. the data is inserted prior to t he byte in the received frame indicated by the dllstake. the number of bytes inserted (starting at mpls_0) is con- trolled by the expanded vlan_mpls_hwa. fcinfo x?03? y 4 flow control color information pulled from the frame header by the hardware classifier. see table 7-89: flow control information values on page 269. ibm powernp np2g network processor preliminary embedded processor complex page 230 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 bci x?04? y 24 byte count indicator passed from a queue (gr0, gr1, gb0, gb1, gpq, gtq, gfq) to the fcbpage. indicates starting byte location within the first twin, number of data buffers, and ending byte location within the last twin. the format of this field is contro lled by the bci format control (see section 13.3 bci format register on page 444). in earlier versions, the format of the bci is always the com pact format described below. bci_format_ctl description 0 compact format. bit description 19:14 starting byte (of us er data, not frame header) 13:6 number of data buffers (weight) 5:0 ending byte 1 expanded format. bit description 21:16 starting byte (of us er data, not frame header) 15:8 number of data buffers (weight) 7:6 reserved 5:0 ending byte byte numbering within the data buffers st arts at 0 and goes to 63. an invalid bci specification might result in unpr edictable behavior. an invalid bci is defined in one of the following ways: number of data buffers (weight) = 0 number of data buffers (weight) = 1 and ending byte < starting byte starting byte or ending byte < 6 currtwin x?08? y 20 at dispatch, indicates the first twin address of the frame type x?0c? y 3 type indicates frame type and data store used. type (2:1): 00 frame 01 reserved 10 reserved 11 abort type (0) for gtq, gpq when toggle mode is disabled: 0dsu0 1dsu1 type(0) for gr0, gb0 w hen toggle mode is disabled: 0 dsu0 1 both dsu0 and 1 type(0) gr1, gb1 when toggle mode is disabled: 0dsu1 1 both dsu0 and 1 type(0) for gr0, gr1, gb0, gb1, gfq, gtq, gpq when toggle is enabled: 0 twin format 0 1 twin format 1 mpls_5 x?0c? n 8 mpls insert byte 5 of 11. enables insertion of an mpls label of up to 12 bytes. the data is inserted prior to the byte in the received frame indicated by the dllstake. the number of bytes inserted (starting at mpls_0) is con- trolled by the expanded vlan_mpls_hwa. table 7-38. egress fcbpage description (page 2 of 7) field fcb page offset initialized by dispatch unit size (bits) description ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 231 of 539 dsu x?0d? y 2 indicates in which dsu(s) the data fo r this frame is stored. value is dsu(1:0). when toggle mode is disabled: value description 00 reserved 01 stored in dsu 0 10 stored in dsu 1 11 stored in both dsu 0 and 1 when toggle mode is enabled (see section 13.2 toggle mode register on page 444), data is placed into ds0 and ds1 based on twin format: 00 invalid 01 forces twin format 0 10 forces twin format 1 11 invalid qhd x?0e? n 1 twin header qualifier. indicates type of twin pointed to by currtwin. used for egress frame alteration. 0 the twin pointed to by the currtwin is a data twin 1 the twin pointed to by the currtwin is a header twin ow x?0f? n 7 orphan twin weight. number of twins orphaned by frame alteration actions. when this field is greater than 0, t he datafirsttwin scalar must be loaded with the location of the first data twin. when this field is 0, the etypeact and etypevalue scalar registers can be loaded for insert and overlay ethertype frame alterations. qid x?10? n 20 queue identifier. the format of the qi d is determined by qid(19:18) as fol- lows: qid(19:18) 00 and scheduler is active, the queue is a flow qcb qid(10:0) flow qcbaddress 00 and scheduler disabled, the queue is a indicates the target port where: qid (6) priority qid (5:0) target port id 11 g queue identifier, where qid(17:0) indicates the queue as: qid (17:0) queue 000 gr0 001 gr1 010 gb0 011 gb1 100 gfq 101 gtq 110 gpq 111 discard datafirsttwin ?14? n 19 address of frame?s fi rst data twin. valid when ow is not 0. table 7-38. egress fcbpage description (page 3 of 7) field fcb page offset initialized by dispatch unit size (bits) description ibm powernp np2g network processor preliminary embedded processor complex page 232 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 etypeact x?15? n 3 the field is defined as bits(2:0) definition 000 etype value is invalid 001 etype value is valid and is us ed when sa/da insert/overlay hard- ware assisted frame alteration is ac tive to insert or overlay the etype field of the frame being processed. 010 etypevalue is valid and is us ed when sa/da insert/overlay hard- ware assisted frame alteration is ac tive to insert or overlay the length/type field of the frame w hen the en_hwa(1:0) field is set to either ?01? (overlay) or ?10? (insert). a 3-byte ip sap, x?06 0603?, is inserted or overlaid following the length/type field. 011 etypevalue is valid and is us ed when sa/da insert/overlay hard- ware assisted frame alteration is ac tive to insert or overlay the length/type field of the frame w hen the en_hwa(1:0) field is set to either ?01? (overlay) or ?10? (insert). additional ly, an 8-byte ip snap, x?aaaa 0300 0000 0800?, is inserted or overlaid following the length/type field. 100 etypevalue is valid and is us ed when sa/da insert/overlay hard- ware assisted frame alteration is ac tive to insert or overlay the length/type field of the frame w hen the en_hwa(1:0) field is set to either ?01? (overlay) or ?10? (insert). additionally , an 8-byte mpls uc snap header, x'aaaa 0300 0000 8847', is inserted or overlaid following the length/type field. 101 etypevalue is valid and is us ed when sa/da insert/overlay hard- ware assisted frame alteration is ac tive to insert or overlay the length/type field of the frame w hen the en_hwa(1:0) field is set to either ?01? (overlay) or ?10? (i nsert). additionally, 8-byte mpls mc snap header, x'aaaa 0300 0000 8848', is inserted or overlaid fol- lowing the length/type field. 110 - 111 reserved. etypevalue x?16? n 16 ethertype value used in insert / overlay egr ess frame alteration daptr x?18? n 6 destination address pointer for egress frame alteration. th is field contains the index into the da_array. for this fi eld definition to be used to access the da_array, bit 2 of en_hwa must be set to ?1?. saptr x?19? n 6 source address pointer for egress fram e alteration. indicates the sa array address used by the e-pmm to locate the source address for egress frame alterations. valid ranges are 0 - 63. da47_32 x?1a? n 16 destination address bits (47:32) used fo r frame alteration sa/da insert or overlay actions. mpls_6 x?1a? n 8 mpls insert byte 6 of 11. enables insertion of an mpls label of up to 12 bytes. the data is inserted prior to the byte in the received frame indicated by the dllstake. the number of bytes inserted (starting at mpls_0) is con- trolled by the expanded vlan_mpls_hwa. mpls_7 x?1b? n 8 mpls insert byte 7 of 11. enables insertion of an mpls label of up to 12 bytes. the data is inserted prior to the byte in the received frame indicated by the dllstake. the number of bytes inserted (starting at mpls_0) is con- trolled by the expanded vlan_mpls_hwa. da31_0 x?1c? n 32 destination address bits (31:0) used fo r frame alteration sa/da insert or overlay actions. mpls_8 x?1c? n 8 mpls insert byte 8 of 11. enables insertion of an mpls label of up to 12 bytes. the data is inserted prior to the byte in the received frame indicated by the dllstake. the number of bytes inserted (starting at mpls_0) is con- trolled by the expanded vlan_mpls_hwa. table 7-38. egress fcbpage description (page 4 of 7) field fcb page offset initialized by dispatch unit size (bits) description ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 233 of 539 mpls_9 x?1d? n 8 mpls insert byte 9 of 11. enables insertion of an mpls label of up to 12 bytes. the data is inserted prior to t he byte in the received frame indicated by the dllstake. the number of bytes inserted (starting at mpls_0) is con- trolled by the expanded vlan_mpls_hwa. mpls_10 x?1e? n 8 mpls insert byte 10 of 11. enables insertion of an mpls label of up to 12 bytes. the data is inserted prior to t he byte in the received frame indicated by the dllstake. the number of bytes inserted (starting at mpls_0) is con- trolled by the expanded vlan_mpls_hwa. mpls_11 x?1f? n 8 mpls insert byte 11 of 11. enables insertion of an mpls label of up to 12 bytes. the data is inserted prior to t he byte in the received frame indicated by the dllstake. the number of bytes inserted (starting at mpls_0) is con- trolled by the expanded vlan_mpls_hwa. en_hwa x?20? n 6 enable hardware assist control. bits 1:0: 00 no hardware assist. 01 overlay sa/da. overlay etype as i ndicated by the etypeact field. sa data is found in the sa_array, as indexed by the saptr. da data is found either in the da field (da47_32 and da31_0) when en_hwa bit 2 is set to ?0?, or in the da_array, as indexed by the daptr, when en_hwa bit 2 is set to ?1?. 10 insert sa/da. insert etype as indicated by the etypeact field. sa data is found in the sa_array, as indexed by the saptr. da data is found either in the da field (da47_32 and da31_0) when en_hwa bit 2 is set to ?0?, or in the da_array, as indexed by the daptr, when en_hwa bit 2 is set to ?1?. 11 reserved. bit 2 controls use of the da_array. w hen this bit is set to ?1?, the fcbpage offset x'18' contains the daptr and o ffset x'19' contains the saptr (the important data for the saptr is always in offset x'19' due to the alignment of the data). bit 2: 0 fcbpage offsets x'1a? to x'1f? c ontain immediate da data and can be used for sa/da insert or ov erlay as controlled by en_hwa. 1 da data for sa/da insert, as determined by the value of en_hwa, is found in the da_array and is indexed by the value of daptr. fcbpage offsets x'1a? to x'1f' c an be used for mpls_n byte insert bit 3 disables har dware assisted padding: bit 3: 0 hardware assisted pad. when set to ?0?, enables the dmu to pad the frame to a configured number of bytes with a configured pad- ding byte. see section 13.25 frame pad configuration register (dmu_pad) on page 489) for more information. 1 no hardware assist. bits 5:4 control a two-byte overlay of the protocol field. the protocol field consists of the two bytes preceding t he dllstake byte; the dllstake must be greater than or equal to two. bits 5:4: 00 no overlay action. 01 overlay the protocol field with the ppp-ip protocol value x'0021' 10 overlay the protocol field wi th the ppp-mpls protocol value x'0281' (mpls unicast) 11 overlay the protocol field with t he protocol value held in the etype- value field. table 7-38. egress fcbpage description (page 5 of 7) field fcb page offset initialized by dispatch unit size (bits) description ibm powernp np2g network processor preliminary embedded processor complex page 234 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 vlan_mpls_hwa x?21? n 5 hardware assist for deleting vlan tags, deleting mpls labels and per- forming mpls label swap. the field is defined as follows: bits 1:0: 00 no action 01 mpls label delete. 10 vlan tag delete 11 mpls label swap the location of the vlan tag is fixed at offset 12. the location of the mpls label is determined by the value of the dll stake field. the mpls label swap function modifies t he label stack entry (4 bytes) as follows: - the 20-bit label field is replaced by the contents of the da(47:28) field - the stack entry exp and s fields are unchanged. - the stack entry ttl field is decremented. bits 4:2 define the mpls_n bytes to be inserted prior to the byte in the received frame indicated by the dllstake. bits 4:2: 000 no insert action. 001 mpls_0 through mpls_1. 010 mpls_0 through mpls_3. 011 mpls_0 through mpls_5. 100 mpls_0 through mpls_7. da immedi ate is not available for use, the daptr must be used if insert or overlay sa/da hardware assist is active. 101 mpls_0 through mpls_9. da immedi ate is not available for use, the daptr must be used if insert or overlay sa/da hardware assist is active. 110 mpls_0 through mpls_11. da immedi ate is not available for use, the daptr must be used if insert or overlay sa/da hardware assist is active. 111 mpls_8 through mpls_11. da immedi ate is not available for use, the daptr must be used if insert or overlay sa/da hardware assist is active. crcaction x?22? n 2 egress frame alteration controls for modifying the crc of a frame. value description 00 no operation 01 crc delete 10 append crc 11 overlay crc dllstake x?23? n 6 the value of the dll termination offset. the dll termination offset is defined as the number of bytes starting at the beginning of the frame to the position one byte beyond the end of the dat a link layer. this value is based upon the encapsulation type. typically, this is the same as the start of the layer 3 protocol header, an exc eption would be for mpls. ttlassist x?24? n 2 egress frame alteration controls for m odifying the time to live field in ip headers or the next hop field in ipx he aders. value is ttlassist(1:0) below: value description 00 disabled 01 ipv4, decrement ttl 10 ipx, increment hop count 11 reserved table 7-38. egress fcbpage description (page 6 of 7) field fcb page offset initialized by dispatch unit size (bits) description ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 235 of 539 fcbpage initializatio n during dispatch during a dispatch to a thread, the hardware classifier and the dispatch unit provide information about the frame being dispatched that is used to initialize some of the fields within the fcbpage. values initialized at the time of dispatch are indicated in table 7-37 and table 7-38 . values that are not indicated as initialized at dispatch are initialized to ?0? for the ?act ive? fcbpage. 7.4.4.2 enqueue coprocessor commands the following commands are supported by the enqueue coprocessor: mpls_0 x?25? n 8 mpls insert byte 0 of 11. enables insertion of an mpls label of up to 12 bytes. the data is inserted prior to t he byte in the received frame indicated by the dllstake. the number of bytes inserted (starting at mpls_0) is con- trolled by the expanded vlan_mpls_hwa. mpls_1 x?26? n 8 mpls insert byte 1 of 11. enables insertion of an mpls label of up to 12 bytes. the data is inserted prior to t he byte in the received frame indicated by the dllstake. the number of bytes inserted (starting at mpls_0) is con- trolled by the expanded vlan_mpls_hwa. mpls_2 x?27? n 8 mpls insert byte 2 of 11. enables insertion of an mpls label of up to 12 bytes. the data is inserted prior to t he byte in the received frame indicated by the dllstake. the number of bytes inserted (starting at mpls_0) is con- trolled by the expanded vlan_mpls_hwa. countercontrol x?28? n 14 passed to flow control for delayed counter manager functions bits description 13 when set to 1 enables counter operation for this enqueue. counter updates on an enqueue work only when the target is a target port or flow queue. counter updates do not occur when enqueing to the grx, gbx, gfq, gpq, gtq or e-gdq. counter updates are sup- ported for the discard port (portid = 41) and the wrap ports (portid = 40, 42) 12 add/increment 11:8 counter number 7:0 counter definition table index counterdata x?2a? n 16 data passed to egress flow contro l for delayed counter manager add func- tions. counterblockindex x?2c? n 20 block index passed to egress flow control for delayed counter manager functions command opcode description enqe 0 enqueue egress. enqueues to the egress eds via the completion unit. for more information, see enqe (enqueue egress) command on page 236. enqi 1 enqueue ingress. enqueues to the ingress eds via the completion unit. for more information, see enqi (enqueue ingress) command on page 238. enqclr 2 enqueue clear. clears (sets all fields to zero in ) the specified fcbpage. for more information, see enqclr (enqueue clear) command on page 240. release_label 3 release label. releases the label in the completion unit for this frame. for more information, see release_label command on page 240. table 7-38. egress fcbpage description (page 7 of 7) field fcb page offset initialized by dispatch unit size (bits) description ibm powernp np2g network processor preliminary embedded processor complex page 236 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 enqe (enqueue egress) command enqe enqueues frames to the egress target queues. the qid field in the fcbpage selects the egress target queue. table 7-40 shows the coding of the qid for this selection. enqe takes a queueclass as a parameter, and some values of queueclass automatically set some bits in the qid field to a predefined value. when a frame is enqueued, the parameters from the fcbpage parameters are extracted and passed to the egress target queue. table 7-39. enqe target queues enqe command enqueues a frame in one of these egress target queues target queue description note target port/flow queues if the scheduler is disabled, enqueued frames are transmitted on target ports 0-39, and logical ports 40-42. if the scheduler is enabled, enqueued frames are enqueued into the flow queues. gr0 enqueued frames are destined fo r any gdh (or the gfh when it is enabled for data frame processing). a unicast frame must be stored in ds0 when queue gr0 is used. a multicast frame must always be stored in both ds0 and ds1. 1 gr1 enqueued frames are destined fo r any gdh (or the gfh when it is enabled for data frame processing). a unicast frame must be stored in ds1 when queue gr1 is used. a multicast frame must always be stored in both ds0 and ds1. 1 gb0 same as gr0, but treated by the dispatch unit as lower priority 1 gb1 same as gr1, but treated by the dispatch unit as lower priority 1 gfq enqueued frames in this queue are destined for the gfh 1 gtq enqueued frames in this queue are destined for the gth 1 gpq enqueued frames in the queue are destined for the embedded powerpc 1 discard queue (e-gdq) enqueued frames in this queue are discarded, which involves freeing e-ds space (twins). frames are only discarded when the mcca (multicast counter address) enqueue parameter equals zero, or when the mult icast counter itself has the value 1. 1. when enqueuing to the gr0, gr1, gb0, gb1, gfq, gtq, or the gpq it is recommended to check the depth of the queue. a dead lock can occur if an attempt is made to enqueue to a full queue. when the queue is full, the enqueue should be re-directed to t he discard queue, an action performed by c ode, and the event reported either via a count or guided traffic. table 7-40. egress target queue selection coding scheduler enabled? qid(19-18) target queue class queue address priority target queue yes 00 flow queue qid(10..0) - flow queue no 00 target port queue qid(5..0) (tpqid) qid(6) (tppri) 0-39 40 41 42 ports wrap to ingress gfq discard (dpq) wrap to ingress gdq - 11 gqueue qid(2..0) (gqid) - 000 gr0 001 gr1 010 gb0 011 gb1 100 gfq 101 gtq 110 gpq 111 discard (e-gdq) ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 237 of 539 enqe takes three parameters: the queueclass, a nolabel flag, and the fcbpage. according to the queue class parameter, bits 19, 18, and 5..0 in the qid field of the fcbpage are changed by the coprocessor according to table 7-44 . like enqi, enqe does not modify the fcbpage. table 7-41. egress target queue parameters queue type queue select enqueue parameters target port/flow queue qid qid, bci, qhd, ow, datafirsttwin, sb, currtwin, mcca, mpls_vlandel, sainsovl, crcaction, l3stake, ttlassist, dsu, saptr, da, fcinfo, countercontrol, counterdata, counterblockindex gr0, gr1, gb0, gb1, gfq, gtq, gpq qid currtwin, type, bci, mcca, countercontrol, counterdata, counterblockindex discard (e-gdq) qid currtwin, type (see table 7-42 ), bci, mcca table 7-42. type field for discard queue type definition 001 discard ds0 010 discard ds1 others reserved table 7-43. enqe command input name size operand source description direct indirect queueclass 5 imm16(4..0) gpr(4..0) egr ess queue class as defined in table 7-44 . nolabel 1 imm16(5) imm12(5) 0 the cu will use a label if one was dispatched with this frame. this is determined by the status of the disp_label register. 1 the completion unit will not use a label for this enqueue. this enqueue is directly executed and is not part of the frame sequence maintenance. fcbpageid 2 imm16(7..6) imm12(7..6) 00 active fcbpage is enqueued. 10 fcbpage 2 is enqueued. ibm powernp np2g network processor preliminary embedded processor complex page 238 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 enqi (enqueue ingress) command enqi enqueues frames to the ingress target queues. ingress target queues are selected by means of three fields that are part of the fcbpage: iucnmc, priority_sf, and tdmu. table 7-46 shows the coding of this selection. table 7-44. egress queue class definitions queueclass qid19 qid18 qid2 qid1 qid0 target queue notes 0 - - - - - reserved 1 0 0 - - - port/flow queue 2 0 0 qid(5..0) = 40 wrap gfq queue 4 3 0 0 qid(5..0) = 41 discard queue (dpq) 4 0 0 qid(5..0) = 42 wrap frame queue 5 1 1 0 0 s grx queue 1 6 1 1 0 1 s gbx queue 1 7 11100 gfq 8 11101 gtq 9 11110 gpq 10 1 1 1 1 1 discard queue (gdq) 3 15 ----- any queue 2 1. the enqe instruction may automatically select the appr opriate data store or queue, depending on the dsusel bit. 2. queue class 15 does not modify any qid bits and al lows picocode full control of the target queue. 3. the type field is modified: bit 2 is set to 0 and the dsu bits are copied to bits 0 and 1 of the type field. 4. when using queue class 2, 3, or 4 and the scheduler is enabled, it is the responsibili ty of the picocode to insure that qcb 4 0, 41, and 42 are initialized for the wrap grq (40), the discard port (41), and wrap data queue (42). note: ?-? - the field is not modified by the enqueue instruction s - the value of the dsusel bit in the fcbpage table 7-45. enqi target queues target queue description ingress multicast queue priorities 0/1 enqueued frames are treated as multicast fram es. guided frames must be enqueued in a multi- cast queue, even when their destination is a single port. ingress tp queue priorities 0/1 enqueued frames are treated as unicast fram es. there are a total of 512 tdmu queues: 256 high priority (priority 0) and 256 low priority. ingress discard queue priorities 0/1 enqueued frames are discarded, which involves freeing ingress buffer space (bcbs and fcbs). discarding frames on ingress consumes ingress sc heduler slots. that is, frames are discarded at 58 bytes per slot. ingress gdq enqueued frames are destined for any g dh (or gfh when enabled for data frame processing). ingress gfq enqueued frames are destined for the gfh. ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 239 of 539 when a frame is enqueued the parameters from the fcbpage are extracted and passed to the ingress target queue. table 7-47 shows the parameters that are passed to the ingress eds. enqi takes three parameters: the queueclass, a nolabel flag, and a fcbpage. according to the queue- class parameter, the priority_sf and tdmu fields in the fcbpage are modified by the enqueue coprocessor according to table 7-49 when passed to the ingress eds. for example, to enqueue a unicast frame for trans- mission, the picocode prepares the fcbpage, including the priority and tp fields and invokes enqi with queueclass set to 5. table 7-46. ingress target queue selection coding iucnmc priority sf tdmu target queue 0 0 0 - ingress multicast queue - priority 0 0 1 0 - ingress multicast queue - priority 1 1 0 0 0 - 3 ingress tp queue - priority 0 1 1 0 0 - 3 ingress tp queue - priority 1 1 0 1 0 ingress discard queue - priority 0 1 1 1 0 ingress discard queue - priority 1 1 x 1 2 ingress gdq 1 x 1 3 ingress gfq table 7-47. ingress target queue fcbpage parameters frame type parameters uc ethernet fcba, countercontrol, counterdata, counterblockindex, tdmu, fcinfo, priority_sf, iucnmc, lid, idsu, fhf, fhe, vlanhdr, pib, ins_ovlvlan mc ethernet fcba, countercontrol, counterdata, counterblockindex, priority_sf, iucnmc, fcinfo, mid, l3stk, fhf, fhe, vlanhdr, pib, ins_ovlvlan table 7-48. enqi command input name size operand source description direct indirect queueclass 5 imm16(4..0) gpr(4..0) table 7-49: ingress-queue class definition on page 240 nolabel 1 imm16(5) imm12(5) 0 the cu will use a label if one was dispatched with this frame. this is determined by the status of the disp_label register. 1 the completion unit will not use a label for this enqueue. this enqueue is directly executed and is not part of the frame sequence maintenance. fcbpageid 2 imm16(7..6) imm12(7..6) 00 active fcbpage 1 is enqueued. 10 fcbpage 2 is enqueued. ibm powernp np2g network processor preliminary embedded processor complex page 240 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 enqi does not modify the fcbpage. for example, if the queueclass parameter is set to txq, the sf field is set to ?0?. this means that in the sf field received by the completion unit and passed to the ingress-eds is modified to ?0?. the sf field in the fcbpage is not modified. enqclr (enqueue clear) command enqclr takes one parameter, th e fcbpage, and fills the entire fcbpage register with zeros. release_label command this command releases the label in the completion unit for this frame. this command has no inputs. table 7-49. ingress-queue class definition queue class symbolic name iucnmc priority sf tdmu target queue 0dq1 - 1 0 discard queue. picocode must set the priority field. fcinfo field must be set to x?f?. 2i-gdq1112gdh q ueue. fcinfo field must be set to x?f?. 4gfq1113gfh queue. fcinfo field must be set to x?f?. 5txq - - 0 - multicast queue or tdmu qc b queues (transmission queues). picocode must set iucnmc and tp fields. 7anyq---- any queue. picocode must set iucnmc, priority, sf and tp fields. note: a ?-? means the fcbpage field is not modified by the enqi command when passed to the ingress-eds. table 7-50. enqclr command input name size operand source description direct indirect fcbpageid 2 imm16(7..6) imm12(7..6) indicates which fcb is to be cleared by the command. 00 active fcbpage is cleared. 10 fcbpage 2 is cleared. table 7-51. enqclr output name size operand source description direct indirect fcbpage 384 array the fcbpage array indicated by the input fcbpageid will be reset to all ?0?s. table 7-52. release_label output name size operand source description direct indirect disp_label 1 r the disp_label register is reset on the execution of the release label command. ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 241 of 539 7.4.5 checksum coprocessor the checksum coprocessor generates checksums using the algorithm found in the ietf network working group rfc 1071 ?computing the internet checksum? (available at http://www.ietf.org ). as such, it performs its checksum operation on halfword data with a halfword checksum result. 7.4.5.1 checksum coprocessor address map table 7-53. checksum coprocessor address map name register (array) number access size (bits) description chksum_stat x?00? r 2 status of checksum coprocessor bits description 1 insufficient indicator (if set to 1) 0 bad checksum (if set to 1) chksum_acc x?01? r/w 16 when writing this register, the va lue is a checksum. when reading this register, the value is a header checksum (the one?s comple- ment of a checksum). chksum_stake x?02? r/w 10 pointer into data store coproce ssor arrays where checksum is to be performed. bits description 9:8 data store coprocessor array number 7:0 byte offset into the array chksum_length x?03? r/w 8 working length remaining in the checksum calculation ibm powernp np2g network processor preliminary embedded processor complex page 242 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 7.4.5.2 checksum coprocessor commands data for the checksum coprocessor must be in one of the data store coprocessor?s arrays. the commands to the checksum coprocessor include: when an ip is indicated, the starting location (i.e., stake) for the layer 3 header is passed. the hardware determines the length of the ip header from the header length field and loads this value into the length scalar register. when generating the checksum, a value of zero is substituted for the halfword that contains the current checksum. when cell header skip is indicated, the cell header in the egress frame is skipped in checksum operations. see the datapool for egress frames on page 207 for more details of cell header skip. command opcode description gengen 0 generate checksum. generates a c hecksum over a data block with a specified length. options of this command include initiating a new checksum oper ation or continuing a checksum where a pre- vious checksum has left off. for more information, see gengen/gengenx commands on page 243. gengenx 4 generate checksum with cell header skip. for more information, see gengen/gengenx commands on page 243. genip 1 generate ip checksum. for more information, see genip/genipx commands on page 244. genipx 5 generate ip checksum with cell header skip. for more information, see genip/genipx commands on page 244. chkgen 2 check checksum. checks a checksum over a data bl ock with a specified length. options of this command include initiating a new checksum operation or continuing a checks um where a previous checksum has left off. for more information, see chkgen/chkgenx commands on page 244. chkgenx 6 check checksum with cell header skip. for more information, see chkgen/chkgenx commands on page 244. chkip 3 check ip checksum. for more information, see chkip/chkipx commands on page 245. chkipx 7 check ip checksum with cell header skip. for more information, see chkip/chkipx commands on page 245. ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 243 of 539 gengen/gengenx commands table 7-54. gengen/gengenx command inputs name size operand source description direct indirect load new stake 1 imm(6) imm(6) indicates: 1 stake value is passed in the command. 0 stake value is in chksum_stake. clear accumulation 1 imm(5) imm(5) chksum_acc contains the seed for the checksum operation. the value in this register indicates whether to use or clear the data in chksum_acc. 0 use data 1 clear chksum_acc stake argument 10 imm(1:0,15:8) imm(1:0) gpr(23:16) the new stake value to be used for the checksum operation if the load new stake argument is ?1?. the stake argument is comprised of two parts. the first (imm1:0) is the data store coprocessor array number. the second(imm(15:8) or gpr(23:16)) is the byte offset within the array. chksum_stake 10 r the stake value to be used for the checksum operation if the load new stake argument is ?0?. chksum_acc 16 r contains the seed for the next checksum operation if the ?clear accumulation? argument is a ?0?. (otherwise there is no data in chksum_acc). chksum_length 8 r the number of halfwords to read when calculating checksum table 7-55. gengen/gengenx/gen ip/genipx command outputs name size operand source description direct indirect return code 1 cpei signal 0 ko, operation failed bec ause there was not enough data in the datapool 1 ok, operation completed successfully. chksum_stat 2 r status of checksum coprocessor bits description 1 insufficient data in datapool 0 bad checksum chksum_stake 10 r stake register. points to the halfword of data following the last halfword used in the checksum command. chksum_acc 16 r the seed for the next checksum operation. contains the resulting checksum if the return code is ok. ibm powernp np2g network processor preliminary embedded processor complex page 244 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 genip/genipx commands for genip/genipx command outputs, see table 7-55: gengen/gengenx/genip/genipx command outputs on page 243. chkgen/chkgenx commands table 7-56. genip/genipx command inputs name size operand source description direct indirect load new stake 1 imm(6) imm(6) indicates: 1 stake value is passed in the command. 0 stake value is in chksum_stake. clear accumulation 1 imm(5) imm(5) chksum_acc contains the seed for the checksum operation. the value in this register indi cates whether or not to use or clear the data in chksum_acc. 0 use data 1 clear chksum_acc clear ip count 1 imm(4) imm(4) ip count clear control. 0 continue with current count in the checksum length register 1 clear counter and load with value in ip length field. stake argument 10 imm(1:0,15:8) imm(1:0) gpr(23:16) the new stake value to be used for the checksum operation if the load new stake argument is ?1?. the stake argument is comprised of two parts. the first (imm1:0) is the data store coprocessor array number. the second(imm(15:8) or gpr(23:16)) is the byte offset within the array. chksum_stake 10 r the stake value to be used for the checksum operation if the load new stake argument is ?0?. chksum_acc 16 r contains the seed for the next checksum operation if the ?clear accumulation? argument is a ?0? (otherwise there is no data in chksum_acc). table 7-57. chkgen/chkgenx command inputs name size operand source description direct indirect load new stake 1 imm(6) imm(6) indicates: 1 stake value is passed in the command. 0 stake value is in chksum_stake. stake argument 10 imm(1:0,15:8) imm(1:0) gpr(23:16) the new stake value to be used for the checksum operation if the load new stake argument is ?1?. the stake argument is comprised of two parts. the first (imm1:0) is the data store coprocessor array number. the second(imm(15:8) or gpr(23:16)) is the byte offset within the array. chksum_stake 10 r the stake value to be used for the checksum operation if the load new stake argument is ?0?. chksum_acc 16 r this is the checksum to be verified. chksum_length 8 r the number of halfwords to r ead when calculating the check- sum. ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 245 of 539 chkip/chkipx commands for chkip/chkipx co mmand outputs, see table 7-58: chkgen/chkgenx/chkip/chkipx command outputs on page 245. results of the commands are found in chksum_acc, chksum_stake, and the 1-bit return code to the clp. chksum_acc contains the result of the checksum calculation. chksum_stake contains the byte location following the last halfword included in the checksum. the return code indicates the operation completed successfully or was verified. the status register may need to be read to determine the status on a bad return code. table 7-58. chkgen/chkgenx/chkip/chkipx command outputs name size operand source description direct indirect return code 1 cpei signal 0 ko, operation failed. check status register for reason. 1 ok, operation completed successfully. chksum_stat 2 r status of checksum coprocessor bits description 1 insufficient data in datapool 0 bad checksum chksum_stake 10 r stake register. points to the halfword of data following the last halfword used in the checksum command. chksum_acc 16 r the seed for the next checksum operation. if equal to 0 the checksum was correct. table 7-59. chkip/chkipx command inputs name size operand source description direct indirect load new stake 1 imm(6) imm(6) indicates: 1 stake value is passed in the command. 0 stake value is in chksum_stake. clear accumulation 1 imm(5) imm(5) chksum_acc contains the seed for the checksum operation. the value in this register indi cates whether or not to use or clear the data in chksum_acc. 0 use data 1 clear chksum_acc clear ip count 1 imm(4) imm(4) ip count clear control. 0 continue with current count in the checksum length register. 1 clear counter and load with value in ip length field. stake argument 10 imm(1:0,15:8) imm(1:0) gpr(23:16) the new stake value to be used for the checksum operation if the load new stake argument is ?1?. the stake argument is comprised of two parts. the first (imm1:0) is the data store coprocessor array number. the second(imm(15:8) or gpr(23:16)) is the byte offset within the array. chksum_stake 10 r the stake value to be used for the checksum operation if the load new stake argument is ?0?. chksum_acc 16 r this is the checksum to be verified. ibm powernp np2g network processor preliminary embedded processor complex page 246 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 7.4.6 string copy coprocessor the string copy coprocessor extend s the dppu?s capabilities to move blocks of data without tying up the clp. the data is moved within the shared memory pool and can start and end on any byte boundary within a defined array. 7.4.6.1 string copy coprocessor address map 7.4.6.2 string copy coprocessor commands strcopy (string copy) command strcopy moves multiple bytes of data between arrays in the shared memory pool. the clp passes the starting byte locations of the source and destinat ion data blocks, and the number of bytes to move. table 7-60. string copy coprocessor address map name register number size (bits) access description strcpy_saddr x?00? 14 r/w the source address for the data to be copied: bit description 14 cell header skip access mode 13:10 coprocessor number 9:8 array number from coprocessor address maps 7:0 byte offset within the array strcpy_daddr x?01? 14 r/w the destination address for the data to be copied: bit description 14 cell header skip access mode 13:10 coprocessor number 9:8 array number from coprocessor address maps 7:0 byte offset within the array strcpy_bytecnt x?02? 8 r the number of bytes remaining to be moved. this is a working reg- ister. once the coprocessor starts, this register will no longer be valid (it will show the number of bytes remaining). command opcode description strcopy 0 for more information, see strcopy (string copy) command on page 246 table 7-61. strcopy command input name size operand source description direct indirect strcpy_saddr 14 r source address. see table 7-60: string copy coprocessor address map on page 246 strcpy_daddr 14 r destination address. see table 7-60: string copy coprocessor address map on page 246 numbytes 8 imm(7:0) gpr(7:0) number of bytes to transfer ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 247 of 539 7.4.7 policy coprocessor the policy coprocessor provides an interface to the policy manager for threads. a thread requests an update to the ?color? of a frame through this interface. frame color is part of the network processor's configurable flow control mechanism which determines what actions may be taken on the frame. a thread must wait until the policy manager, via the policy coprocessor, returns a result. 7.4.7.1 policy coprocessor address map 7.4.7.2 policy coprocessor commands polaccess (access policy manager) command polaccess requests that the policy manager accesses the policy control block for the flow that this frame is a member of. operands include the policy control block address, the length of the packet (usually the ip packet length), and the color currently assigned to the frame. the result returned is a new frame color. table 7-62. strcopy command output name size operand source description direct indirect strcpy_saddr 14 r source address. the offset fiel d of the source address will be incremented by the number of bytes transferred. strcpy_daddr 14 r destination address. the offset field of the destination address will be incremented by the num ber of bytes transferred. numbytes 8 r this field is 0. table 7-63. policy coprocessor address map name register number size (bits) access description polcolor x?00? 2 r/w both the color that is passed to the policy manager and the result color that is passed back from the policy manager. polpktlen x?01? 16 r/w the packet length sent to the policy manager. polcba x?02? 20 r a value of the policy control bl ock address that was found in a leaf after the frame has been classified and a s earch was per- formed. bit description 19:10 reserved. 9:0 policy control block address. command opcode description polaccess 0 for more information, see polaccess (access policy manager) command on page 247 ibm powernp np2g network processor preliminary embedded processor complex page 248 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 7.4.8 counter coprocessor the counter coprocessor provides an interface to the counter manager for threads. the counter copro- cessor has an eight-deep queue for holding counter access commands issued by any of the four threads running in each dppu. exce pt for counter reads, the counter coprocessor will not stall a th read on synchro- nous commands unless the queue is full. this allows for one thread to have multiple counter commands outstanding simultaneously. for example one of the threads may have all the outstanding commands in the queue or each thread may have two each. normal coprocessor operation would only allow one outstanding command per thread. 7.4.8.1 counter coprocessor address map table 7-64. polaccess input name size operand source description direct indirect policy cba 20 gpr(19:0) polcba address polcolor 2 r policy color polpktlen 16 r policy packet length table 7-65. polaccess output name size operand source description direct indirect polcolor 2 r returned policy color table 7-66. counter coprocessor address map name register number size (bits) access description ctrdatalo x?00? 32 r/w counter data low. this register hol ds the least signi ficant 32 bits of a counter on a read commands. on write or add commands the lower 16 bits serve as the dat a passed to the counter manager. (only bits 15..0 are write accessible). ctrdatahi x?01? 32 r counter data high. this register holds the most significant 32 bits of a counter on a read commands. ctrcontrol x?02? 12 r/w counter control. 11:8 counter number. defines which counter in the counter set should be updated. 7:0 counter definition table index. defines which counter definition would be used for this update. ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 249 of 539 7.4.8.2 counter coprocessor commands the counter coprocessor provides the following commands: ctrinc/ctrrinc (counter increment) commands ctrinc and ctrrinc perform an accesses to the central counter manager to increment a counter. this command does not cause synchronous commands to sta ll if the counter coprocessor queue is not full. command opcode description ctrinc 0 counter increment. initiates a modify and increment command to the counter manager. for more information, see ctrinc/ctrrinc (counter increment) commands on page 249. ctrrinc 2 reduced counter increment. initiates a modify and increment command to the counter manager using an immediate field instead of loading the ctrcontrol scalar register. for more information, see ctrinc/ctrrinc (counter increment) commands on page 249. ctradd 1 counter add. initiates a modify and add command to the counter manager. the coprocessor passes the counter manager a 16-bit value to add to the indicated counter. for more information, see ctradd/ctrradd (counter add) commands on page 250. ctrradd 3 reduced counter add. initiates a modify and a dd command to the counter manager. the coprocessor passes the counter manager a 16-bit value to add to the indicated counter. this command uses an immediate field instead of loading the ct rcontrol scalar register. for more information, see ctradd/ctrradd (counter add) commands on page 250 ctrrd 4 counter read. initiates a read and no clear command to the counter manager. the counter manager returns the counter value to the counter coprocessor and leaves the counter unmodified. for more information, see ctrrd (counter read) / ctrrdclr (counter read clear) command on page 251. ctrrdclr 5 counter read with counter clear. initiates a read and clear command to the counter manager. the counter manager returns the counter value to the counter coprocessor and resets the counter to zero. for more information, see ctrrd (counter read) / ctrrdclr (counter read clear) command on page 251. ctrwr15_0 6 counter write bits 15:0 of a counter. initiates a write command to the count er manager. the coprocessor passes a 16-bit value to be loaded into bits 15:0 of t he counter. uses lsb of c ounter data low register. for more information, see ctrwr15_0 (counter write 15:0) / ct rwr31_16 (counter write 31:16) command on page 251. ctrwr31_16 7 counter write bits 31:16 of a counter. initiates a write command to the counter manager. the coprocessor passes a 16-bit value to be loaded into bits 31:16 of t he counter. uses lsb of counter data low register. for more information, see ctrwr15_0 (counter write 15:0) / ct rwr31_16 (counter write 31:16) command on page 251. table 7-67. ctrinc input name size operand source description direct indirect setindex 20 gpr(19..0) selects which set of count ers to reference for this counter action. ctrcontrol 12 r(11..0) counter control. 11:8 counter number. defines which counter in the counter set should be updated. 7:0 counter definition table i ndex. defines which counter defi- nition should be used for this update. ibm powernp np2g network processor preliminary embedded processor complex page 250 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 ctradd/ctrradd (counter add) commands ctradd and ctrradd perform accesses to the central counter manager to add a 16-bit value to a counter. this command will not cause synchron ous commands to stall if the coun ter coprocessor queue is not full. table 7-68. ctrrinc input name size operand source description direct indirect setindex 20 gpr(19..0) selects which set of count ers to reference for this counter action. ctrcontrol 12 imm (11:0) counter control. 11:8 counter number. defines which counter in the counter set should be updated. 7:0 counter definition table i ndex. defines which counter defi- nition should be used for this update. table 7-69. ctradd input name size operand source description direct indirect setindex 20 gpr (19..0) selects which set of counters to reference for this counter action. ctrdatalo 16 r(15..0) the value to be added to the counter. ctrcontrol 12 r(11..0) counter control. 11:8 counter number. defines which counter in the counter set should be updated. 7:0 counter definition table index. defines which counter definition should be used for this update. table 7-70. ctrradd input name size operand source description direct indirect setindex 16 gpr (31:16) selects which set of counters to reference for this counter action. ctrdatalo 16 gpr (15:0) the value to be added to the counter. ctrcontrol 12 imm (11:0) counter control. 11:8 counter number. defines which counter in the counter set should be updated. 7:0 counter definition table index. defines which counter definition should be used for this update. ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 251 of 539 ctrrd (counter read) / ctrrdclr (counter read clear) command ctrrd / ctrrdclr performs an access to the central counter manager to read a counter. the ctrrdclr command also clears the counter after the read is performed. ctrwr15_0 (counter write 15:0) / ctrwr31_16 (counter write 31:16) command ctrwr15_0/ctrwr31_16 performs an access to the central counter manager to write a 16-bit value to a counter. the ctrwr15_0 writes the 16-bit data value to bits 15..0 of the counter and the ctrwr31_16 writes the value to bits 31..16 of the counter. this command does not cause synchronous commands to stall if the counter coprocessor queue is not full. table 7-71. ctrrd/ctrrdclr input name size operand source description direct indirect setindex 20 gpr(19..0) selects which set of counters to reference for this counter action. ctrcontrol 12 r(11..0) counter control. 11:8 counter number. defines wh ich counter in the counter set should be updated. 7:0 counter definition table index. defines which counter definition should be used for this update. table 7-72. ctrrd/ctrrdclr output name size operand source description direct indirect ctrdatalo 32 r for 32-bit counters this register contains the value of the counter once the read is perform ed. for 64-bit counters, this register contains the least signifi cant 32 bits of the counter once the read is performed. ctrdatahi 32 r for 32-bit counters this register is not valid. for 64-bit counters, this register contains the most significant 32 bits of the counter once the read is performed. table 7-73. ctrwr15_0/ctrwr31_16 input name size operand source description direct indirect setindex 20 gpr(19..0) selects which set of count ers to reference for this counter action. ctrdatalo 16 r(15..0) the value to be written to the counter ctrcontrol 12 r(11..0) counter control. 11:8 counter number. defines which counter in the counter set should be updated. 7:0 counter definition table index. defines which counter definition should be used for this update. ibm powernp np2g network processor preliminary embedded processor complex page 252 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 7.4.9 coprocessor response bus the coprocessor response bus (crb) is a bus interface and an internal coprocessor that enables an external coprocessor to write the crbresults register and reset the busy bit of the crb coprocessor. the 20-bit crbresults register is written by an external device via the 14-bit coprocessor response bus. the 20 bits written into the crbresults register by the external device are defined by the user. when the crbresults register is written, the busy bit of the corresponding th read is automatically reset to indicate that the external device is done. 7.4.9.1 coprocessor response bus address map 7.4.9.2 coprocessor response bus commands crbsetbusy command when the crbsetbusy command is executed, the busy bi t is set. the busy bit is reset when the crbresults register is written by an external device. the crb copr ocessor does not indicate to the external device that the busy bit has been set. the external device must re ceive its data or commands via some other method. table 7-74. coprocessor response bus coprocessor address map name register (array) number size (bits) access description crbresults x?00? 20 r coprocessor response bus results. this field contains the 20 bits of data written to this thr ead?s crbresults r egister from an external device. data is written into the register via the 14-bit coprocessor response bus. table 7-75. coprocessor response bus coprocessor command summary opcode command detail section 0 crbsetbusy see crbsetbusy command . table 7-76. crbsetbusy output name size (bits) operand source description direct indirect return code 1 cpei signal the operation always returns an ok ?1?. crbresults 20 r coprocessor response bus results. this field contains the 20 bits of data written to this thr ead?s crbresults r egister from an external device. data is written into the register via the 14-bit coprocessor response bus. ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 253 of 539 7.4.9.3 14-bit coprocessor response bus from the 14-bit coprocessor response bus, twenty-four 20-bit registers can be written. one register is associ- ated with each thread. these 20-bit registers are the crbresults registers. the 14-bit coprocessor response bus is a 14-bit input-only bus. these inputs are synchronous with the z0 lu_clk (see table 2-4: z0 zbt sram interface pins on page 42). that is, the setup and hold require- ments on these inputs are relative to the z0 lu_clk. to write one of the 20-bit crb0results scalar registers, two consecutive clock cycles are used. the bit defini- tions for each clock cycle are shown in table 7-77 . 7.4.10 semaphore coprocessor the semaphore coprocessor provides an interface for threads to the semaphore manager. the semaphore coprocessor supports one outstanding coprocessor command per thread, and indicates a busy status until the command has been serviced. 7.4.10.1 semaphore coprocessor commands the semaphore coprocessor provides the following commands: table 7-77. 14-bit response bus bit and cycle definition cycle response_bus bit description 0 13 bit 13 is set to ?1?. the first of two cons ecutive cycles is indicated by bit 13 being high. 12:7 thread number. the thread number indicates to whic h of the 24 crbresults scalar registers the 20 bits of data are written. the thread number is a binary encoded value from 000000 to 011111. 6:0 crbresults (6:0).this cycle also contains seven of the 20 bits of data to be loaded into a crbresults register. 1 13 don?t care. this cycle always follows a cycle 0 and bit 13 is set to ?don?t care.? 12:0 crbresults (19:7). this cycle cont ains the remaining 13 bits of data to be loaded into a crbresults register. idle 13 bit 13 is set to ?0?. when the external device does not have any data to write into any of the 24 crbresults registers, the exter nal device must hold bit 13 low. 12:0 don?t care. during an idle cycle, these bits are set to ?don?t care.? command opcode description semaphore lock 0 request to lock a semaphore. parameters includ e: thread semaphore number, orderid, semaphore value, and timeoutenable. this command is complete when the semaphore is locked. the minimum time to complete a lock is five cycles. this repres ents the amount of time busy signal is asserted: five cycles if the lock is granted imm ediately, more if it is blocked. semaphore unlock 1 request to unlock a semaphore. parameters include: thread semaphore number. this command is complete when the semaphore is unlocked. the time to complete an unlock is three cycles (the amount of time the busy signal is asserted). reservation release 2 request to remove a semaphore reservation from a queue. parameters include: orderid. this command is complete when the reservation is released. the ti me to complete a release is three cycles (the amount of time the busy signal is asserted). ibm powernp np2g network processor preliminary embedded processor complex page 254 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 note: the busy signal will not be asserted if a lock no-op, unlock no-op, or reserv ation release no-op is issued. the following tables show the details of what is included in the commands: table 7-78. semaphore lock input name size operand source description direct indirect semnr 1 imm16(0) imm12(0) selects one of the two semaphores that can be owned by a thread. timeoutenable 1 imm16(1) imm12(1) enables timeout of command after one try. if a lock is not granted, the command returns with a ko. if a lock is granted, the command returns with an ok. orderid 2 imm16(3..2) imm12(3..2) 00: use unordered semaphore 01: use ordered semaphore id = 0 10: use ordered semaphore id = 1 11: no-op 4msbaddressbits 4 imm16(7..4) imm12(7..4) these four bits are ored to the upper 4 bits of address. address 32 imm16(15..8) gpr(31..0) the semaphore value (in direct mode, the 8 address bits are right-justified, the 4 msbaddres s bits are ored with x?0? and left-justified, and the remaining bits are 0s) note: there are no restrictions about how orderid and semnr are used in conjunction with each other. fo r example, although perfectly legal, there is no requirement that a lock request wishing to use ordered semaphore id = 1 also request semnr = 1. it is accept able to request ordered semaphore id = 1 and semnr = 0, and vice versa. table 7-79. semaphore unlock input name size operand source description direct indirect semnr 2 imm16(1..0) gpr(1..0) selects the semaphores that can be owned by a thread. 00: no-op 01: unlock semaphore semnr 0 10: unlock semaphore semnr 1 11: unlock semaphore semnr 0 and 1 table 7-80. reservation release input name size operand source description direct indirect orderid 2 imm16(3..2) gpr(1..0) 00: no-op 01: release ordered semaphore id 0 10: release ordered semaphore id 1 11: release ordered semaphore id 0 and 1 note: when using the reservation release instructi on, the thread must wait for completion of this instruction before exiting. the res - ervation release command must be issued synchr onously, or it must be issued asynchrono usly followed by a wait command to the semaphore coprocessor. ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 255 of 539 7.4.10.2 error conditions these error conditions generate error interrupts on a per-thread basis: 1. exit and locked. if an exit instruction is execut ed and the thread still has a locked semaphore, the sema- phore manager will re ceive information from the dppu indicati ng that a thread ha s exited. the sema- phore manager unlocks the semaphore and then generates an error. if a thread issues an asynchronous lock request that goes pending and then exits before the request is completed, this error will be reported via the se maphore errors register. this might cause this thread to hang during a subsequent dispatch, or cause another thread requiring the requested semaphore to hang. 2. lock same sem value. if a thread tries to lock a second semaphore with the same value as the first one it already has locked, t he semaphore mana ger will not lock the semaphor e and an error will be reported via the semaphore errors register. 3. lock same sem number. if a thread tries to lock a semaphore number (0 or 1) that it already has locked (regardless of semaphore value), the semaphore man ager will not grant the lock. it will unlock the sema- phore that was in that pos ition and will generate an error. 4. queue not enabled. if a thread tries to lock an ordered semaphore, but the orderenable[threadnum] bit is not set, an error is g enerated. the semaphore ma nager will grant the lock an yway. the lock request will internally be made to look like an unordered lock request and will be processed as though it were an unordered lock request originally. 5. label released and reservation unused. when an enqueue with label or a release label instruction is executed and the thread still has an entry pending on the ordered semaphore queues id = 0 or id = 1 which it has not used, an error will be re ported via the semaphor e errors register. there is a precedence with regard to multiple erro rs present in one command (only errors 2, 3, and 4 described above can happen all in one request). the error precedence order for errors 2, 3, and 4 is as follows: 1. error 3 (lock same sem number) will be detected and will prevent erro rs 2 and 4 from being detected. 2. error 4 (queue not enable d) and error 2 (lock same sem val) will both be detected if error 3 is not present. for example, a thread in its initial state might have no orderid queues enabled and semnr 0 locked with a semaphore value x. if that thread sends in a request for an ordered lock of semnr 0 and semaphore value x, it results in error conditions 2, 3, and 4. however, the se maphore manager will detect one of the errors first (error 3), generate the error interrupt and complete the request before detecting any of the other errors. on the other hand, assuming the same initial state as above, if a thread sends in a request for an ordered lock of semnr 1 and semaphore value x, which results in errors 2 and 4, both er rors will be detect ed and reported. ibm powernp np2g network processor preliminary embedded processor complex page 256 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 7.4.10.3 software use models a few rules should be followed when writing software that will use semaphor es in order to prevent software lockups due to improper use of semaphores. these rules apply when the software is attempting to have two semaphores locked at the same time. 1. semnr 0 and semnr 1 should always be different ?families? of sem aphore values. in other words, a semaphore value locked in position semnr 0 should never be locked in position semnr 1. one way to accomplish this is to use the four most significant address bits to represent resources that are allowed to be locked in one of the two ?f amilies? of semaphore values. 2. semnr 0 should always be locked first, followed by semnr 1. 3. ordered semaphore operations (ordered lock requests or reservation releases) must be completed before the first enqueue and are not permitted after that. 4. np2g supports use of two semaphores when ordered semaphores are enabled. when using ordered semaphores, only one ordered semaphore should be used at a time and it should be locked first. a sec- ond semaphore can be locked at the same time if it is unordered. ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 257 of 539 7.5 interrupts and timers the np2g provides a set of hardware and software interrupts and timers for the management, control, and debug of the processor. when an interrupt event o ccurs or a timer expires a task is scheduled to be processed by the embedded processor complex. the interrupt or timer task does not preempt threads currently processing other tasks, but is scheduled to be dispatched to the next idle thread that is enabled to process the interrupt or timer. the starting address of the task is determined by the interrupt or timer class and read from table 7-84: port configuration memory content on page 262. 7.5.1 interrupts the interrupt mechanism within the np2g has several registers: the interrupt vector registers 0-3, interrupt mask register 0-3, interrupt target register 0-3. and the software interrupt registers. 7.5.1.1 interrupt vector registers the interrupt vector register is a collection of interrup ts that will share a comm on code entr y point upon dispatch to a thread in the epc. a bit representing the individual interrupt within the interrupt vector register is only set on the initial event of the interrupt. even if the interrupt vector register is cleared, an outstanding interrupt will not set the bi t in the register again until it is detected that the interrupt conditi on is going from an inactive to active state. picocode can access the inte rrupt vector registers either as scalar registers (see 7.2.1.1 core language processor address map on page 169) or through the cab interface to the master copy. the interrupt vector register is cleared when it is read from its master copy through the cab interface but not when read as a scalar register. 7.5.1.2 interrupt mask registers the interrupt mask registers have a bit to correspond with each bit in the interrupt vector registers. the interrupt mask registers indicate which interrupts in the interrupt vector registers cause an task to be scheduled for processing by the epc. the interrupt mask registers have no affect on the setting of the inter- rupt vector registers. 7.5.1.3 interrupt target registers the interrupt target register indicates which thread types in the epc are enabled to process the interrupt of a given class 0-3. 7.5.1.4 software interrupt registers the software interrupt registers provide 12 unique interrupts (three in each of the four classes) that can be defined by software and accessed through cab addresses. writing a software interrupt register sets the corresponding bit within the interrupt vector register 0-3 and has the same effect as a hardware-defined interrupt. ibm powernp np2g network processor preliminary embedded processor complex page 258 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 7.5.2 timers the np2g has four timer interrupt counters that can be used to generate delayed interrupts to the epc. 7.5.2.1 timer interrupt counters timer interrupt counters 0-2 are 24 bits in length and decrement at 1 ms intervals. timer interrupt counter 3 is 32 bits in length and decrements at 10 s intervals. the timer interrupt counters are activated by writing a non-zero value to the register. when the timer decrements to a zero value it will schedule a timer task to be processed by the epc ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 259 of 539 7.6 dispatch unit the dispatch unit tracks thread usage and fetches initial data of frames prior to assigning a thread to a task. it also handles timers and interrupts by dispatching the work for these to an available thread. the dispatch unit fetches frame data from the ingress and egress data stores for frame traffic work. the data is placed into the dispatch data buffer (ddb), an array maintained by the dispatch unit. there are 24 entries. each entry holds data for one frame dispatch. three of the locations are fixed in use. the remaining 21 entries are used for work from the remaining egress frame queues, gr0, gr1, gb0, and gb1, and the ingress gdq queues. the three fixed locations hold data for frame traffic from the ingress and egress guided frame handler (gfq) queues, the egress general table handler (gtq) queue, and the request and egress only general powerpc handler (gpq) queues. the dispatch unit selects work from interrupts, timers, and frame queues. there are nine frame queues, four timer interrupts, and four hardware interrupts. if a queue is not empty and there is room in the ddb for data for a queue type, then the dispatch unit's queue arbiter considers the queue a candidate for selection via a priority, ingress/egress driven, round-robin process. see table 7-81: priority assignments for the dispatch unit queue arbiter on page 260 for the queues and priority weights. the lower the priority number, the higher the priority selection weight. figure 7-17. dispatch unit gfq dispatch event controller thread status dispatch interface data and port configuration memory information port configuration memory ingress data store mover ingress data store interface to gfq gtq gpq ddb dcb data move status egress data store mover egress data store interface to egress eds data move status queue arbiter gdq i-gfq gtq e-gfq gpq gr0 gr1 gb0 gb1 gdq egress queues ingress queues ingress eds ibm powernp np2g network processor preliminary embedded processor complex page 260 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 selection toggles between the ingress groups and egress groups. if there are no candidates in one group, then the other group may be selected during consecutive opportunities. in order to keep either the ingress or the egress work from taking up the entire ddb and thus starving the opposite group, a threshold is main- tained for both. these thresholds are compared against the 21 entries in the ddb from the ingress and egress work groups. if a threshold is exceeded, then no further work for that group is allowed into the ddb. simulation has shown that a value of 16 for each gro up's threshold maximizes the dispatch unit throughput and does not allow either group to starve from lack of processor resources. once a frame has been selected by the queue arbiter, that frame?s data is fetched into the ddb. any relevant information about the frame?s queue entry is fetched into the dispatch control block (dcb). the amount of data fetched is dependent on the queue?s port configuration memory contents. the port configuration memory is an array used by the dispatch unit that contains entries for all ingress ports, interrupts, and egress work queues. the dispatch event controller (dec) schedules the dispatch of work to a thread. it monitors the status of all 24 threads in the epc, the status of data movement into the ddb, and the status of the four hardware inter- rupts and four timers. work from the gfq, gtq, and gpq may only be processed by the gfh, gth, and gph-req threads respectively. threads that are allowed to handle interrupts and timers are configurable; they can be restricted to a single thread type, or can be processed by any thread. the dec assures that there is a match between an available thread and the type of work to be performed. the dec load balances threads on the available dppus and clps, keeping the maximum number of threads running in parallel in the epc. when a thread is available for work, and there is a match between the thread and ready work unit, and all the data has been moved for the work unit, then the work unit is dispatched to the thread for processing. the dec provides the data fetched from the ddb and the contents of the port configuration memory corre- sponding to the entry. when multiple units of work are ready to go that match available threads, the dec toggles between ingress and egress work units. there is no data movement for timers and interrupts. only the contents of the port configuration memory entry are passed to the thread. table 7-81. priority assignments for the dispatch unit queue arbiter queue priority ingress group i-gfq 1 gdq 2 egress group e-gfq 1 gtq 2 gpq 3 gr0 4 gr1 4 gb0 5 gb1 5 ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 261 of 539 7.6.1 port configuration memory table 7-84: port configuration memory content on page 262 provides control, default, and software defined information on each dispatch and is passed to the thread to be stored in the configuration quadword array in the data store coprocessor. 7.6.1.1 port configuration memory index definition the port configuration memory index consists of 64 entries that are indexed based upon multiple parameters including ingress port, egress queues, timers, and interrupts as defined in table 7-82 . table 7-82. port configuration memory index port configuration memory index definition 0 .. 39 ingress sp (from gdq) 40 ingress wrap frame (i-gdq) 41 reserved 42 i-gfq 43 ingress wrap guided 44 reserved 45 gpq 46 egress gfq 47 gtq 48 egress frame in either ds0 or ds1 49 egress frame in ds0 and ds1 50 reserved 51 reserved 52 reserved 53 reserved 54 egress abort of frame in either ds0 or ds1 55 egress abort of frame in ds0 and ds1 56 interrupt 0 57 interrupt 1 58 interrupt 2 59 interrupt 3 60 timer 0 61 timer 1 62 timer 2 63 timer 3 ibm powernp np2g network processor preliminary embedded processor complex page 262 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 7.6.2 port configuration memory contents definition bits 127.. 24 are software defined and are for use by the picocode. the remaining bits are used by the hard- ware, as defined in table 7-84 . table 7-83. relationship between sp field, queue, and port configuration memory index sp field in fcb1 queue port configuration memory index 0, 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31, 34, 35, 38, 39 (denotes physical port) gdq 0, 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31, 34, 35, 38, 39 0, 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31, 34, 35, 38, 39 (denotes physical port) i-gfq 42 40 (denotes wrap port) gdq 40 40 (denotes wrap port) i-gfq 43 table 7-84. port configuration memory content field name bits description 127 .. 25 for software use ipv4 forwarding enabled 24 use of this bit is enabled by configuration of the enhanced clas sification enable register (see section 13.14.10 on page 467): 0 ipv4 forwarding disabled 1 ipv4 forwarding enabled pos_ac 23 0 ac not present 1 ac present ethernet/ppp 22 0 ppp port 1 ethernet port codeentrypoint 21 .. 6 the default code entry point. can be overwritten by the hardware classifier (if enabled). culabgenenabled 5 0 no label is generated 1 the hardware classifier generates a label that is used by the completion unit to main- tain frame sequence this field must be set to 0 for port configur ation memory entries 54, 55 (representing aborted frames on the egress), 56-59 (i nterrupts), and 60-63 (timers). hardwareassistenabled 4 0 hardware classifier is disabled 1 hardware classifier is enabled and the cl assifier may overwrite the codeentrypoint reserved 3 .. 2 reserved. set to ?00?. numberofquadwords 1 .. 0 defines the number of quadwords that the dispatch unit will read from the frame and store in the datapool: 00 four quadwords 01 one quadword 10 two quadwords 11 three quadwords for port configuration memory entries 56-63 (i nterrupts and timers), th is field is ignored and the dispatch unit will not write any quadword into the datapool. ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 263 of 539 7.6.3 completion unit the completion unit provides the interface between the epc and the ingress enqueuer/dequeuer/scheduler (ingress eds) and egress eds. during dispatch, the thread is identified and a label for the frame being dispatched is created. frames from the same communication flow receive the same label. using these labels and thread ids, the completion unit maintains frame order within communication flows. for example, the completion unit blocks completion of a thread until all threads with the same label dispatched before that thread have been enqueued and completed. frames dispatched without labels must be enqueued without labels. frames enqueued without labels are not blocked by other threads pending completion (that is, they are completed as soon as resources are avail- able). because of this, frames without labels are not guaranteed to stay in order. ibm powernp np2g network processor preliminary embedded processor complex page 264 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 7.7 hardware classifier the hardware classifier provides hardware assisted parsing of the ingress and egress frame data that is dispatched to a thread. the results are used to precondition the state of a thread by initializing the thread?s general purpose and coprocessor scalar registers along with the registers? resources and a starting instruc- tion address for the clp. parsing results indicate the type of layer 2 encapsulation, as well as some informa- tion about the layer 3 frame. reco gnizable layer 2 encapsulations include ppp, 802.3, dix v2, llc, snap header, and vlan tagging. reported layer 3 information includes ip and ipx network protocols, five programmable network protocols, the detection of option fields, and ip transport protocols (udp and tcp). if enabled, the hardware classifier also generates labels that are passed to the completion unit with a thread identifier. the cu uses them to maintain frame order within a flow. 7.7.1 ingress classification ingress classification, the parsing of frame data which originated in the ingress eds and is now being passed from the dispatch unit to the dppu, can be applied to ethernet/802.3 frames with the following layer 2 encapsulation: dix v2, 802.3 llc, snap header, and vlan tagging. classification can also be done on pos frames using the point-to-point protocol with or without the ac field present (pos_ac) field. 7.7.1.1 ingress classification input the hardware classifier needs the following information to classify an ingress frame: port configuration memory table entry ( table 7-84 on page 262). the hardware classifier uses the fol- lowing fields: - codeentrypoint - the default starting instruction address. - hardwareassistenabled - culabgenenabled - ethernet/ppp -pos ac frame data. four quadwords must be dispatched (per frame) for ingress classification. protocol identifiers: the hardware classifier compares the values in the protocol identifier registers with the values of the fields in the frame that correspond to those identifiers to determine if one of the config- ured protocols is encapsulated in the frame. the hardware classifier supports seven ethernet protocols (five of which are configurable) and eight point-to-point protocols (five of which are configurable). two registers need to be configured for each ethernet protocol, the ethernet type value and an 802.2 service access point value. the protocol identifiers are configured from the cab. ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 265 of 539 7.7.1.2 ingress classification output the outputs of the ingress hardware classification are: the starting instruction address that is stored in the hccia table. this address is only used when the hardware classification is enabled. when the hardware classification is disabled, or if a protocol match is not found, the code entry point from the port configuration memory table ( table 7-84: port configuration memory content on page 262) is used as the starting instruction address and is passed to the thread. if a protocol match does occur, the starting instruction address is retrieved from the last 24 entries of the hccia table. hccia values are configured from th e cab. the address into hccia are provided in ta b l e 7-86: hccia table on page 266. table 7-85. protocol identifiers cab address access bits description x?2500 0000? r/w 16 ethernet type for protocol 0 x?2500 0010? r/w 16 ethernet type for protocol 1 x?2500 0020? r/w 16 ethernet type for protocol 2 x?2500 0030? r/w 16 ethernet type for protocol 3 x?2500 0040? r/w 16 ethernet type for protocol 4 x?2500 0050? r 16 ethernet type for ipx (x?8137?) x?2500 0060? r 16 ethernet type for ip (x?0800?) x?2500 0070? 16 reserved x?2500 0080? r/w 16 point to point type for protocol 0 x?2500 0090? r/w 16 point to point type for protocol 1 x?2500 00a0? r/w 16 point to point type for protocol 2 x?2500 00b0? r/w 16 point to point type for protocol 3 x?2500 00c0? r/w 16 point to point type for protocol 4 x?2500 00d0? r 16 point to point type for ipx (x002b?) x?2500 00e0? r 16 point to point type for ip (x0021?) x?2500 00f0? r 16 point to point control ty pe frame (msbs of type field is ?1?) x?2500 0100? r/w 8 service access point for protocol 0 x?2500 0110? r/w 8 service access point type for protocol 1 x?2500 0120? r/w 8 service access point type for protocol 2 x?2500 0130? r/w 8 service access point type for protocol 3 x?2500 0140? r/w 8 service access point type for protocol 4 x?2500 0150? r 8 service access point type for ipx (x?e0?) x?2500 0160? r 8 service access point type for ip (x?06?) x?2500 0170? 8 reserved note: within each group of interface types (ethernet, point to point, or service access point), the prot ocol identifier values must b e unique. this restriction includes setting up a programmable protocol identifier to be equal to a fixed protocol identifier. the fixed protocol identifier for ppp cont rol frames (x?2500 00f00?) creates a conflic t with the programmable protocol identifi er. this conflict is resolved in the following ways: a complete (all bits) protocol match is selected over a ppp control match. ibm powernp np2g network processor preliminary embedded processor complex page 266 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 ta bl e 7 - 8 6 . h c c i a ta b l e (page 1 of 2) hccia cab address bits classification notes x?2500 0400? x?2500 05f0? 16 egress locations (see section 7.7.2.1 egress classification input on page 269) x?2500 0600? 16 ethernet protocol 0 classification with no 802.1q vlan 1 x?2500 0610? 16 ethernet protocol 1 classification with no 802.1q vlan x?2500 0620? 16 ethernet protocol 2 classification with no 802.1q vlan x?2500 0630? 16 ethernet protocol 3 classification with no 802.1q vlan x?2500 0640? 16 ethernet protocol 4 classification with no 802.1q vlan x?2500 0650? 16 ethernet ipx classifi cation with no 802.1q vlan x?2500 0660? 16 ethernet ip classification with no 802.1q vlan 1 x?2500 0670? 16 ingress aborted fr ame at time of dispatch x?2500 0680? 16 ethernet protocol 0 classification with 802.1q vlan x?2500 0690? 16 ethernet protocol 1 classification with 802.1q vlan x?2500 06a0? 16 ethernet protocol 2 cl assification with 802.1q vlan x?2500 06b0? 16 ethernet protocol 3 cl assification with 802.1q vlan x?2500 06c0? 16 ethernet protocol 4 classification with 802.1q vlan x?2500 06d0? 16 ethernet ipx classification with 802.1q vlan x?2500 06e0? 16 ethernet ip classification with 802.1q vlan 1 x?2500 06f0? 16 ethernet vlan frame with an erif x?2500 0700? 16 point to point protocol 0 classification x?2500 0710? 16 point to point protocol 1 classification x?2500 0720? 16 point to point protocol 2 classification x?2500 0730? 16 point to point protocol 3 classification x?2500 0740? 16 point to point protocol 4 classification x?2500 0750? 16 point to po int ipx classification x?2500 0760? 16 point to point ip classification 1 x?2500 0770? 16 point to point control frame x'2500 0780' 16 ethernet ipv4 multicast with no 802.1q vlan 2, 4 x'2500 0790' 16 ethernet ipv4 multicast with 802.1q vlan 2, 4 x'2500 07a0' 16 point to point ipv4 multicast 2, 4 notes: 1. in np2g, when enabled by configuration of the enhanced configuration register (see section 13.14.10 enhanced classification enable register (enh_hwc_ena) on page 467), this entry is used for ip4v exceptions . an exception entry is used in the following cir- cumstances: the pct entry for ipv4 forwarding (bit 24) is ?0?. the version and ip header length fields of the ipv4 header is not x?45?. the first four bits of the ip da is greater than x?e?. 2. ipv4 multicast is determined by ex amination of the ip da, where the firs t four bits of t he address are x?e?. 3. ipv4 unicast is determined by examinat ion of the ip da, where the first four bits of the address is less than x?e?. 4. available in np2g when enabled by configurat ion of the enhanced confi guration register (see section 13.14.10 enhanced classifi- cation enable register (enh_hwc_ena) on page 467). ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 267 of 539 ingress protocol type register contains the output of the ingress hardware classifier. this data store coprocessor register is loaded with the protocol identifier that identifies the frame for the given encapsulation type. the fields in the frame data that correspond to data store coprocessor register settings (see table 7- 87 ) are passed to the ingress protocol type regist er. if a vlan tagged frame with an e-rif field is present within the frame, or if the hardware classifier is disabled, this field is invalid. dll termination offset if the hardware classifier is enabled, the dll termination offset is loaded into gpr r0. the dll termina- tion offset is defined as the number of bytes, starting at the beginning of the frame, to the position one byte beyond the end of the data link layer. this value is based upon the encapsulation type. typically, this is the same as the start of the layer 3 protocol header, an exception would be for mpls. classification flags: if the hardware classifier is enab led, classification flags will be loaded into the th read?s gpr r1. x'2500 07b0' 16 reserved 4 x'2500 07c0' 16 ethernet ipv4 multicast with no 802.1q vlan 3, 4 x'2500 07d0' 16 ethernet ipv4 multicast with 802.1q vlan 3, 4 x'2500 07e0' 16 point to point ipv4 multicast 3, 4 x'2500 07f0' 16 reserved 4 table 7-87. protocol identifiers for frame encapsulation types frame encapsulation type data store coprocessor register setting snap ethernet type dix v2 ethernet type sap dsap/ssap point to point protocol point to point type ta bl e 7 - 8 6 . h c c i a ta b l e (page 2 of 2) hccia cab address bits classification notes notes: 1. in np2g, when enabled by configuration of the enhanced configuration register (see section 13.14.10 enhanced classification enable register (enh_hwc_ena) on page 467), this entry is used for ip4v exceptions . an exception entry is used in the following cir- cumstances: the pct entry for ipv4 forwarding (bit 24) is ?0?. the version and ip header length fields of the ipv4 header is not x?45?. the first four bits of the ip da is greater than x?e?. 2. ipv4 multicast is determined by ex amination of the ip da, where the firs t four bits of t he address are x?e?. 3. ipv4 unicast is determined by examinat ion of the ip da, where the first four bits of the address is less than x?e?. 4. available in np2g when enabled by configurat ion of the enhanced confi guration register (see section 13.14.10 enhanced classifi- cation enable register (enh_hwc_ena) on page 467). ibm powernp np2g network processor preliminary embedded processor complex page 268 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 table 7-88. general purpose register bit de finitions for ingress classification flags bit definition notes bit 15 protocol 7 detected 1 bit 14 protocol 6 detected 1 bit 13 protocol 5 detected 1 bit 12 protocol 4 detected 1 bit 11 protocol 3 detected 1 bit 10 protocol 2 detected 1 bit 9 protocol 1 detected 1 bit 8 protocol 0 detected 1 bit 7 ipv4 ttl check. this bit is set to ?1? when the value in the ttl field 1. 2 bit 6 indicates ip options field present bit 5 dix encapsulation bit 4 indicates sap encapsulation bit 3 indicates snap encapsulation bit 2 indicates 802.1q vlan frame bit 1 indicates the 802.1q vlan id was non-zero bit 0 indicates an erif present notes: 1. in most cases only one bit in the range 15:8 is set. the exc eption is for a ppp interface where there is a match on a unique protocol identifier and the ppp control type identifier. 2. available in np2g when enabled by configurat ion of the enhanced confi guration register (see section 13.14.10 enhanced classifi- cation enable register (enh_hwc_ena) on page 467). when not available or disabled by configuration, this bit is set to ?0?. ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 269 of 539 flow control information the hardware classifier initializes the fcbpage?s flow control information (fcinfo) field. the field?s value is based on ip frame information that includes the frame color indicated by bits 4:3 of the ip header?s tos field and the tcp header?s syn bit. the hardware classifier never sets fcinfo field to ?1111? but once the field is in the fcbpage it can be written by picocode to be a ?1111?. 7.7.2 egress classification egress classification, the parsing of frame that originated in the egress eds and is being transferred from the dispatcher to the dppu is limited to choosing a starting instruction address and generating a label to pass to the completion unit. 7.7.2.1 egress classification input for egress frames, the hardware classifier needs the following information to classify the frame: port configuration memory table entry ( table 7-84 on page 262). the hardware classifier uses the fol- lowing fields: - codeentrypoint- the default starting instruction address - hardwareassistenabled - culabgenenabled frame data. one quadword must be dispatched (per frame) for egress classification. table 7-89. flow control information values fcinfo definition 0000 tcp - green 0001 tcp - yellow 0010 tcp - red 0011 non-ip 0100 udp - green 0101 udp - yellow 0110 udp - red 0111 reserved 1000 tcpsyn- green 1001 tcpsyn - yellow 1010 tcpsyn - red 1011 reserved 1100 other ip - green 1101 other ip - yellow 1110 other ip - red 1111 disable flow control ibm powernp np2g network processor preliminary embedded processor complex page 270 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 7.7.2.2 egress classification output the outputs of the egress hardware classification are: starting instruction address. the starting instruction address stored in the hccia memory is only used when the hardware classifica- tion is enabled. when the hardware classification is di sabled, the code entry point from the port config- uration memory table ( table 7-84: port configuration memory content on page 262) is used as the starting instruction address and is passed to the thread. the address into hccia is given by the uc field and by the fhf field in the frame header: frame data offset gpr r0 is always (i.e. also when the hardware classification is disabled) set according to table 7-10: egress frames datapool quadword addresses on page 208 classification flags: if the hardware classifier is enab led, classification flags will be loaded into the thread?s gpr r1. table 7-90. hccia index definition 14 uc fhf table 7-91. general purpose register 1 bit de finitions for egress classification flags bit definition bit 15:1 reserved bit 0 a link pointer error was found during dispatch unit a ccess of the egress data store. recommended action is to discard the frame. ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 271 of 539 7.7.3 completion unit label generation if label generation is enabled for a given dispatch th e following table defines the construction of the 28-bit label to be passed to the completion unit. enabling label generation is programmable in the port configuration memory. if not enabled, the comple- tion unit will not assure frame orde ring for this frame. label generati on should not be used for guided frames, interrupts, and timers. when branchnr is used to form the label, it is initia lized to 0 by the hardware classifier. (it is incremented by the completion unit during multicast enqueues). table 7-92. completion unit label bit28 27..25 24..0 (bits) ingress ethernet frame 1 000 hashed (mac sa/da) sp 24..6 5..0 ppp ingress frame 1 001 0 protocol field sp 24..22 21..6 5..0 ingress unknown protocol 1 010 0 sp 24..6 5..0 egress uc frame 0 000 0 lid 24..21 20..0 egress mc frame 0 001 mid 0 branchnr 24..8 7 6..0 reserved 0 010 0 reserved 0 011 0 reserved 0 100 0 reserved 0 101 0 ibm powernp np2g network processor preliminary embedded processor complex page 272 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 7.8 policy manager the policy manager is a hardware assist of the embedded processor complex that performs policy manage- ment on up to 1 k ingress flows. it supports four ma nagement algorithms. one algorithm pair is ?single rate three color marker,? operated in color-blind or color-aware mode. the other is ?two rate three color marker,? operated again in color-blind or color-aware mode. the algorithms are specified in ietf rfcs 2697 and 2698 (available at http://www.ietf.org ). the policy manager maintains up to 1024 leaky bucket meters with selectable parameters and algorithms. the picocode sends the policy manager a policy manager control block address (polcba), a color, and a packet length for each incoming packet. according to the policy management control block (polcb), two token counters stored in internal memory are regularly incremented (subject to an upper limit) by a rate spec- ified in the polcb and, when a packet arrives, are decremented by one of four possible algorithms (depending upon the incoming packet length). after both actions are complete, the token counters generally have new values and a new color is returned to the picocode. in addition there are three 10-bit wide packet counters in the polcb (redcnt, yellowcnt, and greencnt) that use the output packet colors to count the number of bytes (with a resolution of 64 bytes) of each color. when these counters overflow, the policy manager invokes the counter manager with an increment instruction and counters maintained by the counter manager are used for the overflow count. counter definition 0 is reserved for the policy manager, and must be configured for these overflow counts. the polcb must be configured before use. configuration is accomplished via the cab. the contents of the polcb are illustrated in table 7-93: polcb field definitions on page 273. classification of a frame by the picocode must result in a polcba. the hardware classifier provides the color of the frame in the fcbpage. the frame length used must be parsed from the ip packet header by the pico- code. the policy manager receives the following inputs from the picocode: polcba (20 bits) figure 7-18. split between picocode and hardware for the policy manager polcb memory policy manager to counter manager cab access polcba (20) color (2) packetlength (16) newcolor (2) picocode hardware ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 273 of 539 color (2 bits), the color of the incoming packet. these are re-encoded as received in the ds byte as 00 = green, 01 = yellow, 10 = red. note that the encoding used does not conform to the rfc 2597. packet length (in bytes, 16 bits) the policy manager reads the polcb from the memory, exec utes the algorithm configured by the type field in the polcb, writes the updated polcb back to the memory and returns the new color to the picocode. the policy manager can perform these operations once every 15 core clock cycles. picocode might use this infor- mation as follows: perform no special action discard the packet change the ds byte (i.e., (re-)mark the frame) table 7-93. polcb field definitions (page 1 of 2) field size description type 4 algorithm type. this field mu st be initialized by picocode. 0000 color blind single rate three color marker 0001 color aware single rate three color marker 0010 color blind two rate three color marker 0011 color aware two rate three color marker 0100-1111 reserved pa_time 32 previous arrival time in ticks. this field must be initialized to 0 by the picocode. pa_time is com- pared to a running 32-bit counter which is increm ented every 165/150 ns. selection of the accuracy of the counter tick is controlled by the setti ng of the dram parameter register bit 22 (11/10 ). when set to 1 the tick rate is 165 ns when set to 0 the tick rate is 150 ns. c_token 26 token counter for committed rate accounting in bytes. this field must be initialized by picocode to contain the same value as c_ burstsize. (format is 17.9) ep_token 26 token counter for excess or peak rate accounting in bytes. this field must be initialized by pico- code to contain the same value as ep_burstsize. (format is 17.9) cir 12 committed information rate in bytes/tick used for two rate algorithms. cir uses an exponential notation x * 8 y-3 where 11:3 x 2:0 y; valid values of y are ?000? through ?011? a tick for the policy manager is defi ned to be either 165 or 150 ns. sele ction of the value for a tick is controlled by the setting of the dram parameter register bit 22 (11/10 ). when set to 1 the tick is 165 ns, when set to 0 the tick is 150 ns. this field must be initialized by picocode to meet the service level agreement. the pir must be equal to or greater than the cir. cir can be def ined in the range of 100 kbps through 3 gbps. pir 12 peak information rate in bytes/tick used for tw o rate algorithms. pir uses an exponential notation x * 8 y-3 where 11:3 x 2:0 y; valid values of y are ?000? through ?011? a tick for the policy manager is defi ned to be either 165 or 150 ns. sele ction of the value for a tick is controlled by the setting of the dram parameter register bit 22 (11/10 ). when set to 1 the tick is 165 ns, when set to 0 the tick is 150 ns. this field must be initialized by picocode to meet the service level agreement. the pir must be equal to or greater than the cir. pir can be def ined in the range of 100 kbps through 3 gbps. ibm powernp np2g network processor preliminary embedded processor complex page 274 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 c_burstsize 17 committed burst size in bytes. this field must be initialized by picocode to meet the service level agreement. for the single rate algorithms, either the c_bursts ize or the ep_burstsize must be larger than 0. it is recommended that when the value of c_burstsiz e or the ep_burstsize is larger than 0, it is larger than or equal to the size of the mtu for that stream. note: for the two rate algorithms, c_burstsize must be greater than 0. it is recommended that it be larger than 1.5 times the mtu size for that stream. ep_burstsize 17 excess or peak burs t size in bytes. definition depends on algor ithm selected. this field must be ini- tialized by picocode to meet the service level agreement. for the single rate algorithms, either the c_bursts ize or the ep_burstsize must be larger than 0. it is recommended that when the value of c_burstsiz e or the ep_burstsize is larger than 0, it is larger than or equal to the size of the mtu for that stream. when ep_burstsize is larger than 0, the value loaded must be the sum of the cbs and ebs parameters described in rfc 2697. note: for the two rate algorithms, ep_burstsize must be greater than 0. it is recommended that it be larger than 1.5 times the mtu size for that stream. greencnt 10 number of bytes (with 64-byte resolution) in packets flagged as ?green? by the policy manager. when this counter overflows, the policy manager us es the counter manager interface to increment an extended range counter. this field must be initialized to 0 by picocode. the counter control block for the policy manager must be configured at counter definition table entry 0. the green count is counter number 0. yellowcnt 10 number of bytes (with 64-byte resolution) in packets flagged as ?yellow? by the policy manager. when this counter overflows, the policy manager us es the counter manager interface to increment an extended range counter. this field must be initialized to 0 by picocode. the counter control block for the policy manager must be configured at counter definition table entry 0. the yellow count is counter number 1. redcnt 10 number of bytes (with 64-byte resolution) in packets flagged as ?red? by the policy manager. when this counter overflows, the po licy manager uses the counter manager interface to increment an extended range counter. this field must be initialized to 0 by picocode. the counter control block for the policy manager must be configured at counter definition tabl e entry 0. the red count is counter number 2. table 7-93. polcb field definitions (page 2 of 2) field size description ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 275 of 539 7.9 counter manager the counter manager is a hardware assist engine used by the epc to control various counts used by the picocode for statistics, flow control, and policy management. the counter manager is responsible for counter updates, reads, clears, and writes, and it allows the picocode to access these functions using single instruc- tions. the counter manager arbitrates between all requestors and acknowledges when the requested opera- tion is completed. the counter manager works in concert with the counter coprocessor logic to allow the picocode access to the various counters. the counter manager supports the following: 64-bit counters 32-bit counters 24/40-bit counters read, read/clear, write, increment, and add functions a maximum of 1 k 64-bit, 2 k 32-bit, or some mix of the two not to exceed a total size of 64 kb, of fast internal counters up to 4 m 64-bit or 32-bit external counters. two 32-bit counters are packed into a 64-bit dram line. selection of the counter is accomplished by the low-order address bit. counter definition table for defining counter groups and storage locations interfaces to all six dppus, the policy manager, ingress and egress flow control five independent counter storage locations ibm powernp np2g network processor preliminary embedded processor complex page 276 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 figure 7-19. counter manager block diagram ingress flow control internal counter dram bank cntrq4 cntrq0 cntrq1 address & update value counter definition table multiplexer / arbitration dppu5 counter coprocessor dppu0 cntrq2 cntrq3 read read read read read ... policy external dram - d2 a dram bank b dram bank c dram bank d manager counter manager counter coprocessor memory egress flow control ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 277 of 539 7.9.1 counter manager usage the counter manager manages various counters for the epc. the epc, policy manager, and the ingress and egress flow control have the ab ility to update these counters. the pi cocode accesses th ese counters for statistics, flow control actions, and policy decisions. before a counter can be used, its counter definition entry must be configured. this entry defines where the coun ter is stored, how many counters are associated with this set, and the counter?s size. the counter manager supports 256 different counter definition entries. the counter definition entry is wr itten to the counter definition table usin g the cab. the entry format in shown in table 7-97 on page 278. table 7-94. counter manager components component name description counter definition table contains definitions for each counter block (256 entri es). a counter block is made up of the counter?s memory storage location (bank a, bank b, bank c, b ank d, or internal), the base address within that memory, the number of counters within the set, and the counter size. multiplexing and arbitration multiplexing and arbitration logic selects the next coun ter action from all requestors according to prior- ity. flow control has the highest priority, policy manager the next, and the set of dppus the lowest pri- ority. multiplexing and arbitration logic uses tw o work conserving round-r obins: one between the two flow control requestors and one for the set of dppus. this logic returns the read data to the appropri- ate requestor during counter reads. address and update value address and update value logic uses information gat hered from the counter definition table and the parameters passed from the requestor to cr eate the final counter address and update value. cntrq0 - cntrq4 five counter queues used to temporarily hold t he counter request and allow the counter manager to access all five memory loca tions independently. the r equest is placed into the appropriate queue based on the memory storage location informat ion found in the counter definition table. read read logic gathers the read data from the appropriate memory location and returns it to the requestor. internal counter memory internal counter memory holds the ?fast? internal counters and can be configured to hold 64-bit, 24/40- bit, or 32-bit counters. the internal counter memory size is 1024 locations x 64 bits. table 7-95. counter types type name description 64-bit counter counter that holds up to a 64-bit value. 24/40-bit counter special 64-bit counter that has a standard 40-bit por tion and a special 24-bit increment portion. the 40- bit portion is acted upon by the command passed and th e 24-bit portion is incremented. this counter allows ?byte count? and ?frame count? counters to be in one location; the 40-bit portion is the byte count, and the 24-bit portion is the frame count. 32-bit counter counter that holds up to a 32-bit value. table 7-96. counter actions action name description read read counter and return value (either 64 or 32 bits) to the epc. read/clear read counter and return value (either 64 or 32 bits ) to the epc. hardware then writes counter to zero. write write 16 bits to the counter (either bits 31:16 or 15:0) and zero all other bits. increment add one to the counter va lue and store updated value in memory. add add 16 bits to the counter value and store updated value in memory. ibm powernp np2g network processor preliminary embedded processor complex page 278 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 the counter definition entry describes a set of counters that have similar characteristics and are referenced from the picocode as a single group. figure 7-20 on page 279 shows several counter definition examples. table 7-97. counter definition entry format field bits definition reserved 31:30 not used. 24/40 29 flag to indicate 24/40 counter (1 = 24/40). if set, 64 / 32 must also be set to 1. 64 / 32 28 flag to indicate a 64-bit counter (1 = 64) or a 32-bit counter (0 = 32). number of counters 27:23 number of counters within th is counter set. legal values: 1, 2, 4, 8, or 16 counter resource location 22:20 storage used for the counter block. 000 bank a 001 bank b 010 bank c 011 bank d 100 internal memory base address 19:0 base address within the memory where the counter block starts. counter addresses are based on a 64-bit word, however, all address bits are not used for all counter resource loca tions and when a 32-bit counter is indi- cated (bit 28 is set to 0), address bit 0 indicates the counter location within the 64-bit word (0 = bits 31:0, 1 = bits 63: 32). the following illus trates the use of the base address bits. 32-bit counter resource 64-bit word counter location address ---------- ------------------------- -------------- yes '000' - '011' 19:1 yes '100? 11:1 no '000' - '011' 19:0 no '100? 10:0 ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 279 of 539 each counter definition entry can be used for a block of counter sets. the definition describes one counter set and the picocode can reference several consecutive counter sets using the same definition. for example, a counter set is defined as four counters: one for frames less than 500 bytes, one for frames between 500 and 1000 bytes, one for frames between 1001 and 1518 bytes, and the last one for frames greater than 1518. one counter definition entry describes the counters, and picocode can use the definition to reference 40 similar sets of these counters, that is, one for each source port. counter set 0 is located at the base address defined by the entry, counter set 1 is located at the next available address, and so on. figure 7-21 on page 280 shows an example of counter blocks and sets. figure 7-20. counter definition entry counter definition entry 3 counter definition entry 8 counter definition entry 45 number of counters in set = 4 counter resource = bank a base address = x?0 1004? number of counters in set = 8 counter resource = bank c base address = x?0 1608? number of counters in set = 2 counter resource = internal base address = x?0 0044? ibm powernp np2g network processor preliminary embedded processor complex page 280 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 to reference the correct counter, the requestor must pass the counter manager several parameters. these parameters are described in table 7-98 on page 281. figure 7-21. counter blocks and sets counter definition entry 3 number of counters in set = 4 counter resource = bank a base address = x?0 1004? counter set 0 counter set 1 counter set 39 < 500 500 - 1000 1001 - 1518 > 1518 counter block 3 ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 281 of 539 the counter manager builds the actual counter address using the following algorithm: address = base address + (counter set index * number of counters) + counter number this address is used to access the counter within the appropriate memory (bank a, bank b, bank c, bank d, or internal). when a 32-bit counter is accessed, the lo w order bit of the address selects which 32 bits of the 64-bit memory word are being used: 0 = bits 31:0, 1 = bits 63:32. the location of the counter and its size determine how many address bits are used by the counter manager as seen in table 7-99 . table 7-98. counter manager passed parameters parameter bits definition counter definition table index 8 counter de finition entry to use for this action counter set index 20 set of counters to reference counter number 4 counter within the set to reference action 3 action to perform on the counter modify 000 increment by 1 001 add 16 bits to counter read 100 standard read 101 read then clear value write 110 write bits 15:0 of counter; all other counter bits are set to zero 111 write bits 31:16 of counter; al l other counter bits are set to zero all other code points are reserved. add/write value 16 value to add to counter when modify/add selected value to write to counter when write selected flow control action (counter definition table index offset) 2 only used by flow control interfaces 00 standard enqueue 01 discard (resulting from the transmit probability table) 10 tail drop discard 11 reserved table 7-99. counter manager use of address bits memory location counter size number of counters stored at single memory address number of address bits used total counters possible internal 32 2 11 (10:0) where bit 0 selects upper or lower 32 bits 1k loc * 2 per = 2k 64, 24/40 1 10 (9:0) 1k loc * 1 per = 1k dram banks (a, b, c, or d) 32 2 20 (19:0) where bit 0 selects upper or lower 32 bits 512k loc * 2 per * 4 banks = 4m 64, 24/40 1 20 (19:0) 1m loc * 1 per * 4 banks = 4m ibm powernp np2g network processor preliminary embedded processor complex page 282 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 the counter manager supports a special mode of operation when used by the ingress or egress flow control. this mode allows ?delayed increments? to occur based on flow control information. both flow controls pass an additional parameter, flow control action, that causes the counter manager to modify which counter definition entry is used. a standard enqueue sent by either flow control logic causes the counter manager to use the counter definition index that is passed with the request. a discard resulting from the transmit probability table causes the counter manag er to access the counter definition entry that is located at index+1. a tail drop discard causes the counter manager to access the counter definition entry located at index+2. each type of flow contro l action uses a different counter definition. when the policy manager requests use of the counter ma nager, it always uses a counter definition table index of 0. this location is reserved for use by the policy manager. the counter manager arbitrates for a new counter action at a rate of one each 15 ns. when accessing the internal memory, the counter manager can update these counters at a rate of one every 15 ns. the external dram rates are once each 150 ns or each 165 ns d epending on dram cycle config uration (10- or 11-cycle windows), and one to four c ounters (one per bank) will be updated during this time . if the counter manager is updating some (but not all) dram banks, the banks not being updated by the counter manager will have their last location (address = all 1's) written during the dram write window. therefore, the last location of each dram bank must be reserved for this use and cannot be assigned as a counter location. the counter manager supports the following actions: read, read/clear, write/lower, write/upper, increment and add. the dppus can read any counter in the counter manager. the flow control and policy manager logic do not perform counter reads. when a counter is read, the counter manager returns the read data (either 32 or 64 bits) with the acknowledge signal. the picocode can also clear the counter (set to zero) after the read is performed by passing the read/clear action. counter writes of 16 bits are supported and either bits 15:0 or bits 31:16 of the selected counter are set to the write value with all other bits set to zero (this feature is provided to assist in chaining unused counters into a free list). the counter manager also supports incrementing or adding to the selected counter. the add value can be up to 16 bits in size and will be added to the counter (eit her 32, 40, or 64 bits). wh en a 24/40 counter is incre- mented or added, the 24-bit portion of the counter is incremented and the 40-bit portion receives the incre- ment/add action. the counter manager supports the following maximum numb ers of counters (actual number depends on size of dram used and the counter definition table information): up to 1 k 64-bit, or 2 k 32-bit internal counters, or some mix of 64 and 32-bit counters not to exceed 64 kb total size. up to 1 m 64-bit, or 1 m 32-bit external counters per dram bank, or some mix of 64- and 32-bit counters not to exceed 1 m total counters per bank. ibm powernp np2g preliminary network processor np2_ds_sec07_epc.fm.01 february 12, 2003 embedded processor complex page 283 of 539 7.10 semaphore manager the semaphore manager is located within the epc and is controlled by a thread through a semaphore copro- cessor. a semaphore is a mechanism for acquiring ownership or ?locking down? an entity. a semaphore is a 32-bit value. once a thread has exclusive ownership of a semaphore, it is guaranteed that there are no other threads that own a semaphore with the same value (though there may be other threads owning semaphores with different values). thus, other threads that also want ownership of a semaphore with the same value are blocked until the semaphore is unlocked. it is upon the programmer to attach a meaning to a semaphore. that is, the semaphore manager does not know what a semaphore represents - it is just a string of 32 bits. semaphores can be seen as having a 32-bit address space and the programmer can map this to anything, for example, the tree search memory, the data store, or the embedded powerpc. for example, a tree search memory can have the upper four bits of the semaphore value set to ?0000?, an ingress data store address can have the upper four bits of the sema- phore value set to ?0001?, and the embedded powerpc mailbox may have the upper four bits set to ?1111?. when configured for ordered semaphores, a thread can have two semaphores locked at a time, but only one of them can be ordered. unordered semaphor es - when multiple thre ads request a semaphore, the semaphore manager will grant the request through a round-robin fairness algorithm. a thread can lock-and-unlock an unordered semaphore as often as it wants. for example, it can lock-and-unlock, execute some code, lock again, exe- cute more code, unlock, etc. ordered semaphores - when mult iple threads request a semaphore, the semap hore manager will grant the request in the order of frame dispatch for a given flow. in other words, when a thread is processing a frame of a certain flow that has been dispatched before any other frames of the same flow, then it is guar- anteed by the semaphore manager that this thread will get a certain semaph ore value befo re any other threads that are pr ocessing frames of the same flow. the disp atch order will be main tained by placing a ?reservation? into a queue. only semaphore requests in which their reservation is on the top of the queue will be serviced. it will be the re sponsibility of the picocode to release a reservation if it isn?t needed or a deadlock situation will occur. to use ordered semaphores, they must be enabled. this is done by writing the ordered semaphore enable register in the hardware classifier. there is one bit for the semaphore 0 id queue, and one bit for the sema- phore 1 id queue. at dispatch time, the hardware classi fier may assign a completion unit label to a frame as per the port configuration table. 1 if a completion unit label is assigne d, the hardware classifier will examine the ordered semaphore enable register to see if ordered semaphores are enabled as well. if completion unit label generation is not e nabled, ordered semaphores will not be en abled for this dispatch. the completion unit and the semaphore ordering queues use the same label. if a completion unit label is released (via an enqueue with label or release label command), the semaphore order label must first have either been used or released, otherwise an error will occur. a thread can lock-and-unlock an ordered semaphore up to two times. during a request, the thread must specify the orderid, which is 0 or 1. an order queue can only be used once, with two order queues imple- mented for a total of two ordered semaphores per thread. in other words, a thread can only lock orderid 0 once, and orderid 1 once. 1. when the culabgenenabled field of the port configuration table (see table 7-82 on page 261) is set to ?1?. ibm powernp np2g network processor preliminary embedded processor complex page 284 of 539 np2_ds_sec07_epc.fm.01 february 12, 2003 each thread can have ownership of up to two semaphores simultaneously. when using two semaphores, the programmer must take great care to avoid deadlock situations (semaphores can only be requested one by one). for example, a semaphore lock must be followed at some point by a semaphore unlock or a deadlock will occur. the semaphore manager employs a pending concept to ordered semaphore lock requests, which enables it to look past the head of the completion unit queues. the basic idea is if a thread is requesting an ordered lock for a particular semaphore value that is already locked, it will be moved into a pending state, and it?s request will not be considered complete. at th is point, the threads that are behind it in the flow queues can now be considered for locking as long as their semaphore values are different. once the original semaphore value that was locked is unlocked, then the pending th read?s semaphore value will lock and that thread?s request will be completed. it is important to note that only one thread per sema phore value will go into the pending state. the semaphore m anager will process the thre e semaphore coprocessor co mmand types in parallel: lock commands for ordered semaphores at the head of the queue and lock commands for unordered semaphores will be eval uated at the same priority level and a winner will be chosen using a round-robin fairness algorithm. - lock commands will be evaluat ed in parallel with unlock an d reservation release commands. unlock commands - unlock commands will be evaluate d in parallel with lock and reservation release commands. reservation release commands - reservation release command s will be evaluated in parallel with lock and unlock commands. ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 285 of 539 8. tree search engine 8.1 overview the tree search engine (tse) is a hardware assist that performs table searches. tables in the network processor are maintained as patricia trees, with the termination of a search resulting in the address of a leaf page. the format of a leaf page or object is defined by the picocode; the object is placed into a control store, either internal (h0, h1) or external (z0, d0, d2, and d3). 8.1.1 addressing control store (cs) references to the control store use a 26-bit address as shown in table 8-1 . each address contains a memory id, a bank number, and address offset. table 8-2 provides addressing information and recommended uses for each memory that is supported by the csa and that is accessible via the tse. the memory type provides access width and memory size informa- tion. selection for d0 as either single or double wide is by configuration ( 13.1.2 dram parameter register (dram_parm) on page 434). table 8-1. control store address mapping for tse references 26-bit address used to reference the control store 4 bits 2 bits 20 bits memory id bank number offset virtual bank address table 8-2. cs address map and use (page 1 of 2) memory id bank no. memory name type offset width (bits) recommended use 0000 00 null 20 01-11 reserved 0001 00 z0 external zbt sram 1m x 36 20 fast pscb 01-11 reserved 0010 00 h0 internal sram 2k x 128 11 fast leaf pages 01 h1 internal sram 2k x 36 11 fast internal sram 10 reserved 11 reserved 0011 00-11 reserved 0100?0111 00-11 reserved ibm powernp np2g network processor preliminary tree search engine page 286 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 8.1.2 d6 control store. the np2g supports the following ddr dram types for the d6 control store: the d6 control store can be accessed either via the tse or by the embedded powerpc's processor local bus (plb) (see 10.2 processor local bus and device control register buses on page 362). 8.1.3 logical memory views of d6 using the plb, the embedded powerpc or a pci atta ched host views a flat, contiguous address space addressable on byte boundaries. access via the tse uses the control store address mapping described in 8.1.1 addressing control store (cs) on page 285, and is composed of a memory id, bank number and offset. the offset limits addressing capability to 8-byte boundaries within the ddr dram. table 8-3 illustrates the plb to d6 contro l store address translation. the pl b address is shown within the body of the table and the d6 control store address is formed using the memory id, bank number, and offset. 1000 00-11 d0 banks a-d ddr dram d0_width = 0 8 mb 16 mb 32 mb d0_width = 1 16 mb 32 mb 64mb 18-20 single (d0_width = 0) or double wide (d0_width = 1) configuration. leaf pages 1001 ddr dram 8 mb 16 mb 32 mb 18-20 reserved 1010 00-11 d2 banks a-d leaf or counter pages 1011 00-11 d3 banks a-d dt entries and pscb entries 1100 00-11 d6 banks a-d ddr dram 8 mb 16 mb 32 mb 64mb 128 mb 20 powerpc external memory 1101 1110 1111 note: ddr dram is specified as: number of banks number of entries burst access width (in bits). ddr dram total memory space (mb) 4 x 1m x 16 1chip 8 4 x 2m x 16 1chip 16 4x4mx4 4 chips 32 4 x 4m x 16 1chip 32 4x8mx4 4 chips 64 4 x 16m x 4 4 chips 128 table 8-2. cs address map and use (page 2 of 2) memory id bank no. memory name type offset width (bits) recommended use ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 287 of 539 d6 control stores implemented in ddr dram of up to 32 mb in size are accessed by the tse using only memory id '1100'. larger d6 control stores require memory ids of '1101' (up to 64 mb), '1110' (up to 96 mb) and '1111' (up to 128 mb). a method to share memory objects between the embedded powerpc or attached pci host using the plb, and picocode running on the np2g using tse instructions is to specify the object (as viewed by the tse) with a height of one and a width of four. this allows the tse access to all of the d6 control store, on 32-byte boundaries, and is consistent with the plb's flat co ntiguous address space view. successive objects with a height of one and a width of four are accessed by incrementing the tse address until a 32mb boundary is reached. at the boundary it is necessary to increment the memory id to address the next succe ssive object. 8.1.4 control store use restrictions the following restrictions apply: when d2 is used by the counter manager, the last location (highest address) in each bank must not be assigned for any use. dt entries can be stored only in h1, z0, or d3. pscbs can be stored only in h1, z0, or d3. leaf pages can be stored only in h0, d0, and d2. table 8-3. plb and d6 control store addressing memory id (4 bits) bank a (?00?) bank b (?01?) bank c (?10?) bank c (?11?) offset (20 bits) ?1100? 0-7 8-x?f x?10-x?17 x?18 - x?1f x?00 0000? x?20-x?27 x?28-x?2f x?30-x?37 x?38-x?3f x?00 0001? x?07f ffe0 - x?07f ffe7 x?07f ffe8 - x?07f ffef x?07f fff0 - x?07f fff7 x?07f fff8 - x?07f ffff (8mb-1) x?03 ffff? x?0ff ffe0 - x?0ff ffe7 x?0ff ffe8 - x?0ff ffef x?0ff fff0 - x?0ff fff7 x?0ff fff8 - x?0ff ffff (16mb-1) x?07 ffff? x?1ff ffe0 - x?1ff ffe7 x?1ff ffe8 - x?1ff ffef x?1ff fff0 - x?1ff fff7 x?1ff fff8 - x?1ff ffff (32mb-1) x?0f ffff? '1101' x?200 0000 - x?200 0007 x?200 0008 - x?200 000f x?200 0010 - x?200 0017 x?200 0018 - x?200 001f x?00 0000? x?3ff ffe0 - x?3ff ffe7 x?3ff ffe8 - x?3ff ffef x?2ff fff0 - x?2ff fff7 x?3ff fff8 - x?3ff ffff (64mb-1) x?0f ffff? x?400 0000 - x?400 0007 x?400 0008 - x?400 000f x?400 0010 - x?400 0017 x?400 0018 - x?400 001f x?00 0000? x?5ff ffe0 - x?5ff ffe7 x?5ff ffe8 - x?5ff ffef x?5ff fff0 - x?5ff fff7 x?5ff fff8 - x?5ff ffff (96mb-1) x?0f ffff? '1111' x?600 0000 - x?600 0007 x?600 0008 - x?600 000f x?600 0010 - x?600 0017 x?600 0018 - x?600 001f x?00 0000? x?7ff ffe0 - x?7ff ffe7 x?7ff ffe8 - x?7ff ffef x?7ff fff0 - x?7ff fff7 x?7ff fff8 - x?7ff ffff (128mb-1) x?0f ffff? ibm powernp np2g network processor preliminary tree search engine page 288 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 8.1.5 object shapes object shapes specify how the control store stores an object such as a leaf or pattern search control block (pscb). a leaf is a control block that contains the reference key as a reference pattern. the pattern uniquely identifies the leaf in a tree and contains the data needed by the application initiating a tree search. the data is application-dependent, and its size or memory requirements are defined by the ludeftable entry for the tree. see table 8-5: height, width, and offset restrictions for tse objects on page 290 and table 8-17. ludeftable entry definitions on page 307 for details. shape is defined by two parameters, height and width. objects small enough to fit within a single memory or bank location are defined as having a height and width of 1 (denoted by 1,1), and therefore do not require shaping. for example, both a 32-bit and a 48-bit object stored in a ddr sdram bank would have a shape of (1,1). when objects do not fit into a single memory or bank location, they have heights and/or widths > 1: height denotes the number of consecutive address locations in which an object is stored. for example, if the height of an object = 4 and the control store address = a, the object is stored in locations a, a+1, a+2, and a+3. width denotes the number of consecutive banks in which the object is stored. width always = 1 for objects stored in zbt sram, and could be > 1 for obje cts in ddr sdram. for example, if the width of an object = 3, and its height = 1, the object is stored in three consecutive banks (the virtual bank address is incremented by 1). an offset increment can carry out into the bank address bits. this is not a supported use of the cs mem- ory, and table allocation algorithms must be defined to avoid this condition. for height and width, the hardware automatically reads the appropriate number of locations. from a pico- code point of view, an object is an atomic unit of access. for the accesses with height or width of more one, other requesters are not blocked. restrictions to height, width, and offset are given in table 8-5: height, width, and offset restrictions for tse objects on page 290 . table 8-17: ludeftable entry defini- tions on page 307 specifies the leaf and pscb shapes. figure 8-1. example shaping dimensions on page 289 illustrates some exam ple placement of objects with different shapes in control store. an object cannot span more than one memory: table 8-4. dtentry, pscb, and leaf shaping object shape fm dtentry/pscb always has a shape of height = 1, width = 1. smt dtentry/pscb always has a shape of height = 1, width = 1. lpm dtentry/pscb has a shape of height = 1, width = 1 or height = 2, width = 1 depending on the memory in which the pscb resides. a memory with a line width of at least 64 bits should be used with height = 1 and a memory of 36 bits should be used with height = 2. leaf can have any shape that is allowed by the memory in which the leaf is located - maximum of 512 bits. ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 289 of 539 figure 8-1. example shaping dimensions (2,1) 128 h0 h = 1, w = 1 h = 5, w = 1 (note: 4 bits unused) 32 z0 h = 1, w = 1 36 (height = 1,width = 3) 64 (1,2) (3,1) 64 64 64 h = 3, w = 1 example (a) example (b) example (c) (3,1) d2 (3,1) (1,1) abcd 64 64 64 64 (height = 1,width = 4) d2 abcd ibm powernp np2g network processor preliminary tree search engine page 290 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 8.1.6 illegal memory access when the tse uses an undef ined memoryid (that is, reserved) or an illegal memory shape, the tse aborts the current command, returns a ko status, and sets an exception flag at bit 2 in interrupt class 3 (tsm_illegal_memory_access). the exception flag can be set to cause an interrupt by setting bit 2 of inter- rupt mask 3 to ?1? (tsm_illegal_memory_access). for debugging purposes, an exception can switch a programmable set of threads into single-step mode. table 8-5. height, width, and offset restrictions for tse objects memory height width total object size (bits) control store address offset must be divisible by h0 1 2 3 4 1 1 1 1 128 256 384 512 1 2 4 4 h1 1 2 3 4 5 6 7 8 1 1 1 1 1 1 1 1 36 64 96 128 160 192 224 256 1 2 4 4 8 8 8 8 z0 1 2 3 4 5 6 7 8 1 1 1 1 1 1 1 1 36 64 96 128 160 192 224 256 1 2 4 4 8 8 8 8 d0 (d0_width = 1; double wide configuration) 1 2 3 4 1 2 1 1 1 1 1 1 2 2 3 4 128 256 384 512 256 512 384 512 1 2 4 4 1 2 1 1 d0-d2-d3-d6 (d0_width = 0; single wide configuration) 1 2 3 4 5 6 7 8 1 2 3 4 1 2 1 2 1 1 1 1 1 1 1 1 2 2 2 2 3 3 4 4 64 128 192 256 320 384 448 512 128 256 384 512 192 384 256 512 1 2 4 4 8 8 8 8 1 2 4 4 1 2 1 2 ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 291 of 539 8.1.7 memory range checking (address bounds check) memory range checking can flag access to a programmable range within min_addr_bounds and max_addr_bounds for read, write or both using a ddr_bounds_cntl. min_addr_bounds. memory range checking can be performed for any tse control store accesses only. when memory range checking is enabled, any control st ore read, write, or read/write address fa lling within or at the b oundary of the defined range, generates an exception (an exception does not stop tse operation) and sets an exception flag at bit 1 in interrupt class 3 (tsm_addr_range_violation). the exception flag can be set to cause an interrupt by setting bit 1 of interrupt mask 3 to ?1? (tsm_addr_range_violation). for debug purpose, bounds violation register (bounds_vio), indicates which gxh has caused an address bounds exception. ibm powernp np2g network processor preliminary tree search engine page 292 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 8.2 trees and tree searches the tse uses trees to store and retrieve information. tree searches, retrievals, inserts and deletes are performed according to a key that is similar to a mac source address or a concatenation of an ip source and destination address. information is stored in one or more leaves that contain the key as a reference pattern and, typically, contain aging and user information for forwarding purposes such as target port numbers. to locate a leaf, a search algorithm processes input parameters that include the key and hashes the key. the algorithm then accesses a direct table (dt) and walks the tree through the pscbs. there are three types of trees, each with its own search algorithm and tree-walk rules: full match (fm); longest prefix match (lpm); and software managed (smt). the data structure of fm and lpm trees is the patricia tr ee. when a leaf is found, the leaf is the only candi- date that can match the input key. a ?compare-at-end? operation compares the input key with a reference pattern stored in the leaf to verify a match. search results are ?ok? when a match is found and ?ko? in all other cases. the data structure of smt trees is similar to that of fm trees, but smt trees can have multiple leaves that can be chained in a linked list. all leaves in the chain are checked against the input key until a match is found or the chain is exhausted. search results are ?ok? when a match is found and ?ko? in all other cases. table 8-6. fm and lpm tree fixed leaf formats field name byte length description nlarope 4 leaf chaining pointer, aging, and direct leaf information prefix_len 1 length of the pattern (in bits) for lpm only. not used by tse for fm trees and can be used by picocode. pattern 2-24 pattern to be compared with hashedkey. always present. length given by p1p2_max_size from table 8-17: ludeftable entry definitions on page 307. for fm: unused bit between (p1p2_max_siz e - hashedkey_length) must be ini- tialize to zero. for lpm: unused bits between (p1p2_max _size - prefix_len), do not have to be initialized and can be used by user data since these bits do not take part in comparsion. userdata variable under picocode c ontrol. for example, field can include one or more counters. table 8-7. smt tree fixed leaf formats field name byte length description nlasmt 4 leaf chaining pointer to chain leaves for smt. in cludes shape of chained leaf. comp_table_index 1 defines index in compdeftable that defines compare between pattern1, pattern2, and hashedkey. pattern1 and pattern2 4-48 contains pattern1 and pattern2 bitwise in terleaved (even bits represent pattern1 and odd bits represent pattern2). that is, bit 0 of the field contains bit 0 of pattern1, bit 1 contains bit 0 of pattern 2, etc. length given by 2*p1p2_max_size from table 8-17: ludeftable entry defini- tions on page 307. for smt: unused bit between (2 * p1p2_max_size - 2 * hashedkey_length) must be initialized to zero. userdata variable under picocode control. for exam ple, field can include one or more counters. ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 293 of 539 8.2.1 input key and color register for fm and lpm trees for fm and lpm trees, the input key is hashed into a hashedkey according to the hash algorithm specified by the hash_type field in the ludeftable. to minimize the depth of the tree that begins after the direct table, the hash function output is always a 192-bit number with a one-to-one correspondence to the original input key. maximum output entropy is contained in the hash fu nction?s most significant bits. the n highest bits of the hashedkey register are used to calculate an index into the direct table, where n is determined by the defi- nition of the dt (direct table) entry for the tree. when colors are enabled for a tree, the 16-bit color register is inserted after the input key has been hashed. this occurs immediately after the direct table. if the direct table contains 2 n entries, the 16-bit color value is inserted at bit position n. the hash function output and the inserted color value (when enabled) are stored in the hashedkey register. when colors are disabl ed, the 192-bit hash function is unmodified. colors can be used to share a single direct table among multiple independent trees. for example, color could indicate a vlanid in a mac source address table. the input key would be the mac sa and the color the vlanid (vlanid is 12 bits and 4 bits of the color would be unused, that is, set to 0). after the hash function, the pattern would be 48 + 16, or 64 bits. the color would be part of the pattern to distinguish mac addresses of different vlans. 8.2.2 input key and color register for smt trees for smt trees, the input key is a 192-bit pattern and the color register is ignored. no hashing is performed. table 8-8. search input parameters parameter bit length description key 192 key must be stored in the shared memory pool. all 192 bits must be set cor- rectly (for key length shorter than 192, remaining bits in shared memory pool must be set to 0). key length 8 contains key length minus 1 in bits. ludefindex 8 index into ludeftable that points to an entry containing a full definition of the tree in which the search occurs. see section 8.2.5.1 the ludeftable on page 307. tsedpa 4 tse thread shared memory pool address - stores location of key, keylength, and color and determines leaf destination. the tsedpa is the high order 4 bits of the thread's shar ed memory pool address (see 7.2.4 shared memory pool on page 172) and is constrained to be on a four-qw boundary. use only values of x?8?, x?a?, x?c?, and x?e?. lcbanr 1 search results can be stored in either tsrx, as specified by tsedpa. leaf addresses are stored in lcba0 or lcba1 as specified by lcbanr. during a tse search, picocode can access the other tsr to analyze the results of previ- ous searches. color 16 for trees with color enabled, as specif ied in the ludeftable, the contents of the color register are inserted into the key during hash operation. see section 8.2.1 input key and color register for fm and lpm trees on page 293 for an explanation of the process. ibm powernp np2g network processor preliminary tree search engine page 294 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 8.2.3 direct table a search starts when a dtentry is read from the dire ct table. the read address is calculated from the n highest bits of the hashedkey and from the tree properties defined in the ludeftable. the dtentry can be represented as the root of a tree, with the actual tree data structure depending upon tree type. a patricia tree data structure is used with fm trees. extensions to the patricia tree are used with lpms and smts. using a dt can reduce search time (pscb access time). increasing dt size is a trade-off between memory usage and search performance. when a single leaf is attached to a dtentry, the read data includes a pointer to the leaf. when more than one leaf is attached, the read data defines the root of a tree. when the dtentry is empty, no leaf information is attached. 8.2.3.1 pattern search control blocks (pscb) a search begins when a dtentry has been read if the dtentry is neither empty nor contains a direct leaf. a tree walk search starts at the dtentry and passes one or more pscbs until a leaf is found. for an fm tree, the pscb represents a node in the tree, or the starting point of two branches, ?0? and ?1?. each pscb is associated with a bit position ?p? in the hashedkey. bit p is the next bit to test (nbt) value stored in the previous pscb or in the dtentry. leaves reachable from a pscb through the 0 branch have a ?0? in bit p, and leaves reachable through the 1 branch have a ?1?. leaves reachable through either branch have patterns where bits 0..p-1 are identical, beca use pattern differences begin at bit p. when an fm tree search encounters a pscb, the tse continues the tree walk on the 0 or 1 branch depending on the value of bit p. thus, pscbs are only in serted in the tree at positions where leaf patterns differ. this allows efficient search operations since the number of pscbs, and thus the search performance, depends on the number of leaves in a tree, not on the length of the patterns. figure 8-2. effects of using a direct table direct table (dt) data structure without a direct table data structure with a direct table leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf leaf ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 295 of 539 8.2.3.2 leaves and compare-at-end operation the entire hashedkey is stored in the leaf as a reference pattern, not as the original input key. during a tree walk, only the hashedkey bits for which a pscb exists are tested. when an fm leaf is found, its reference pattern must be compared to the full hashedkey to make sure all the bits match. for smt, if the leaf contains a chain pointer or nla field to another leaf, the new leaf?s reference pattern is compared to the hashedkey. lacking a match or another nla field, the search ends and the failure is indicated by a ko status. if the pattern matches, the original input key is checked. if that matches, the whole leaf page is returned to the network processor. if there is no match, the leaf page is returned with a no-match message. 8.2.3.3 cascade/cache the direct table can be used as a cache to increase tr ee search performance since these trees are generally small and contain most likely entries. during a search, the tse first determines whether the dt contains a pointer to a leaf matching the hashedkey. if so, the leaf is returned, eliminating the need for a search. to the tse, a cache lookup is identical to a normal search, that is, the input key is hashed into a hashedkey and the dt is accessed. cascades/caches are enabled in the ludeftable on a per-tree basis. if a cache search uses ludeftable entry i and the search ends with ko, another search using ludeftable entry i+1 starts automatically. this allows multiple search chaining, although the full tree should be stored under ludeftable entry i+1. cascading/caching of more than one ludeftable entry is supported but the last ludef-table entry must have the cache enable bit set to ?0? (disabled). 8.2.3.4 cache flag and nrpscbs registers picocode initiates insert and delete operations to and from the cache. each search result stores information about the cache in the cacheflag and nrpscbs registers as shown in table 8-9 . each register is divided into two sections, one for searches using tse 0 coprocessor and the other for searches using tse 1 copro- cessor. there are two copies of these registers for each tse 0 and tse 1 resource. cacheflags represents the results for the first cached ludef entry when multiple search chaining is used. 8.2.3.5 cache management cache management is performed using picocode. cache inserts are controlled by inspecting the cacheflag and nrpscbs registers after each tree search. inserts are treated like normal fm tree inserts, allowing the association of multiple leaves with a single dtentry, because normal fm inserts create pscbs to handle multiple leaves. inserts can also be done by writing di rectly to a dtentry, although only using single leaves. cache deletes use the tree aging mechanism whereby every n seconds all entries in the cache are deleted. table 8-9. cache status registers register bit length description cacheflag(0) 1 cacheempty bit. set when cache s earch finds an empty dtentry in cache dt. cacheflag(1) 1 cacheleaffound bit. set when cache search finds a leaf and cache search returns ok. when leaf found bit has been set, full search has not been performed. cacheflag(2) 1 cacheko bit. set when cache search returns ko. when cache is empty, this bit is also set. nrpscbs 8 after any search, contains the number of pscbs read during a tree walk. when a cache search finds no leaf and a full search starts, contains the number of pscbs read during the search. ibm powernp np2g network processor preliminary tree search engine page 296 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 8.2.3.6 search output the output of a search operation consists of the parameters listed in table 8-10 . 8.2.4 tree search algorithms the tse provides hardware search operations for fm, lpm, and smt trees. software initializes and main- tains trees. leaves can be inserted into and removed from fm and lpm trees without control point function (cpf) intervention, permitting scalable configurations with cpf control when needed. 8.2.4.1 fm trees full match (fm) trees provide a mechanism to search ta bles with fixed size patterns, such as a layer 2 ethernet unicast mac tables which use fixed six-byte address patterns. searches of fm trees are efficient because fm trees benefit from hash functions. the tse of fers multiple fixed hash functions that provide very low collision rates. each dtentry is 36 bits wide and contains the formats listed in table 8-11 . pscbs have the same structure as dtentrys except they contain two pscblines, each of which can have one of the two pointer formats listed in this table : next pointer address (npa) or leaf control block address (lcba) . the two pscblines are allocated consecutively in memory and are used as walking branches in the tree. the nbt value signifies which of the two pscblines is used. table 8-10. search output parameters parameter description ok/ko flag 0 ko: unsuccessful operation 1 ok: successful operation that is, leaf pattern matches hashedkey tsrx shared memory pool leaf contents are stored at tsedpa address of t he shared memory pool, s pecified by the tree search command operand. lcba0 / 1 scalar registers leaf address is stored in lcba0 / 1 based on lcbanr input value. cacheflags(2) cacheempty bit cacheflags(1) cacheleaffound bit cacheflags(0) cacheko bit nrpscbs number of pscbs read during last search. c an be used as a criterion to insert fm cache entry. table 8-11. dtentry and pscbline formats format conditions valid in dtentry? valid in pscb? format (2 bits) npa/lcba (26 bits) nbt (8 bits) empty dtentry no leaves yes no 00 0 0 pointer to next pscb dtentry contains pointer yes yes 00 npa nbt pointer to leaf with dynamic_leaf_shape_en disabled single leaf associated with dtentry; lcba field contains pointer yes yes 01 lcba 0 pointer to leaf with dynamic_leaf_shape_en enabled single leaf associated with dtentry; lcba field contains pointer nbt contains the lcba shape and leaf shape from ludeftable is ignored yes yes 01 lcba bits (4..0) = lcba leaf shape bits (7..5) = reserved ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 297 of 539 8.2.4.2 lpm trees longest prefix match (lpm) trees provide a mechanism to search tables with variable length patterns or prefixes, such as a layer 3 ip forwarding table where ip addresses can be full match host addresses or prefixes for network addresses. the cpf manages lpm trees with assistance from picocode running on the gth (and optionally the gdh) for inserting and removing leaf entries. lpm dtentrys, each of which can contain a node address, an npa, and an lcba, differ from fm dtentrys which cannot contain both a node and leaf address. each dtentry is 64 bits wide and contains the formats listed in table 8-12: lpm dtentry and pscbline formats on page 297. pscbs have the same structure as dtentrys except pscbs contain two pscblines, each of which can have one of the three lcba formats listed in the table. the two pscblines are allocated consecutively in memory and are used as walking branches in the tree. one of the pscb lines may be empty, which is not allowed in fm pscbs. 8.2.4.3 lpm pscb structure in memory figure 8-3 on page 298 describes the layout of the lpm pscb in the 64-bit or wider memory and the 36-bit memory (z0). table 8-12. lpm dtentry and pscbline formats format conditions valid in dtentry? valid in pscb? format (2 bits) npa (26 bits) nbt (8 bits) lcba (26 bits) spare (2 bits) empty dtentry no leaves yes yes 00 0 0 0 0 lcba not valid dtentry contains pointer to pscb yes yes 00 npa nbt 0 0 lcba valid; npa/ nbt not valid single leaf associated with dtentry; lcba contains pointer to leaf; no pointer to next pscb yes yes 01 0 0 lcba 0 lcba valid; npa/ nbt valid single leaf associated with dtentry; lcba contains pointer to leaf; pointer to next pscb yes yes 01 npa nbt lcba 0 ibm powernp np2g network processor preliminary tree search engine page 298 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 8.2.4.4 lpm compact pscb support lpm compact pscb support is added to enhance memory usage for lpm pscbs when stored in z0 or h1 memories that have 36-bit wide data storage in each location. see figure 8-4 on page 300. lpm pscbs are in pairs and require a total of 64 bits to store a complete entry. when an lpm pscb pair is stored in 64 bits or wider memory, it requires two consecutive locations and each pscb part uses (1x1) shape in memory. when an lpm pscb pair is stored in the 36-bit wide memory, it needs four sequential addresses to store complete pscb pairs and each pscb part uses (1x2) shape in the memory (that is, a complete pscb entry will span to two addresses and a pscb pair will span to four addresses. also, a pscb address must follow shape rules. if lpm pscbs are stored in a 36-bit wide memory, the fo rmat bits (npa and nbt par ts of the pscb) will be stored in the first address (a0/a0+2) and lcba is stored in the next address (a0+1/a0+3). if any intermediate lpm pscbs do not have a valid lcba (prefix), the lcba part of the pscb (a0+1) does not need to be stored. using the lpm compact pscb technique, one ca n make use of this (a0+1/a0+3) unused memory location. this requires software to manage two types of pscb shapes: figure 8-3. example of lpm pscb detail layout in memory example (a) lpm regular pscb in the 64-bit or wider memory 32 bits 36 bits a0 a0+1 a0+2 a0+3 pscb part0 pscb part1 pscb pair # n pscb part0 pscb part1 pscb pair # n+ a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 note: a normal lpm pscb pair is always a multiple of two addresses when stored in the 64-bit memory and a multiple scb_cntl npa nbt lcba reserved (2 bits) (26 bits) (8 bi ts) (26 bits) (2 bits) 0 1 2 27 35 61 63 example (b) regular lpm pscb in the 36-bit memory (z0) scb_cntl npa nbt(7..0) (2 bits) (8 bits) 7 33 35 0 nbt(3..0) lcba reserved (4 bits) (26 bits) (6 bits) 0 5 31 35 a0 a0+1 3 36 bits 32 bits of four addresses when stored in the 36-bit memory. (26 bits) ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 299 of 539 1. compact pscbs, for intermediate pscbs nodes with no prefix/lcba 2. full pscb, for end node or intermediate pscbs with prefix/lcba the compact pscb uses address a+0 to store 0 part of pscb (that is, format, nbt0 , npa0) and a+2 to store 1 part of pscb (that is, format, nbt1, npa1). another independent pscb pair can use a+1 for 0 part and a+3 for 1 part of pscb. ibm powernp np2g network processor preliminary tree search engine page 300 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 8.2.4.5 lpm trees with multibit compare as described earlier in section 8.2, during a search, one bit is tested at every pscb node. except in the case of dense trees, it is possible to compare more than one consecutive bit (multibit mode) to reduce the number of pscb nodes to be walked or compared. to enable the multibit compare mode, the dynamic_multibit_ nbt_en bit defined in table 8-17: ludeftable entry definitions on page 307 must be set to ?1?. figure 8-5 on page 302 describes various formats and their layout in memory. also, the following assumptions apply to np2g multibit lpm trees: figure 8-4. example of lpm pscb and compact lpm pscb layout in memory example (a) lpm regular pscbs in the 64-bit or wider memory pscb part0 pscb part1 pscb part0 pscb part1 64 (ddr-dram) 64 bits pscb pair # 1 pscb pair # n 32 36 bits a0 a0+1 a0+2 a0+3 a0 a0+1 a0+2 a0+3 a0+4 a0+5 pscb part0 pscb part1 pscb pair # n pscb part0 pscb part1 pscb pair # n+ compact pscb pair y pscby part0 pscby part1 compact pscb pair x compact pscb pair z pscbx part0 pscbz part1 pscbz part0 pscby part1 pscbx part1 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 unused compact pscb pair note: in the 36-bit memory, a normal lpm pscb pair is always a multiple of four addresses, and an lpm compact pscb pair note: in the 64-bit or wider memory, a pscb pair is always a multiple of two addresses. example (b) lpm regular pscbs and lp m compact pscbs in the 36-bit memory 62 bits is always allocated in a pair: an and an+2 or an and an+3. ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 301 of 539 lpm multibit direct table can be stored in d3a or d3b only. lpm multibit pscbs are stored in z0 sram 36-bit wide memory only. lpm multibit prefix block (intermediate leaf address) is stored in d3c or d3d (64-bit wide memory). for each entry in the pscb block, lcba (prefix address) is stored in a corresponding prefix block. each prefix_block address contains two lcbas. this addres s is derived using the set global prefix block off- set register and npa, and bits at the nbt offset. - prefix_block_address_base = npa(19..0) + global_prefix_block_offset (19..0) - prefix_block_address = ?10111? and prefix_block_address_base(1) and (prefix_block_address_base/4) - lcba = prefix_block_data(57.32) when prefix_block_address_base(0) = 0 and prefix_block_data(25..0) when prefix_block_address_base(0) = 1 maximum pscb depth: 31. all search keys should be equal to the longest prefix length. ibm powernp np2g network processor preliminary tree search engine page 302 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 figure 8-5. lpm multibit nbt pscb detail layout example (a) lpm multibit pscb format assumptions: pscbs: z0 sram only prefix blocks: d3 (c & d) bank multibit mode bit: when set to 0 = 1-bit test mode; when set to 1 = 4-bit test mode trail end flag: when set to 1 = trail end; when set to 0 = continue reserved (5 bits) npa(19..0) 20 least significant bits nbt = 8 bits = lcba dt pscb format (d3a or d3b): next bits to test 26 bits sram z0 = memid & bank id = 000100 multibit mode bit: when set to 0 = 1-bit test mode; when set to 1 = 4-bit test mode trail end flag = 0 = continue reserved (5 bits) npa(19..0) 20 least significant bits nbt = 8 bits = pscb format : the intermediate leaf (pre fix) is stor ed separately. next bits to test sram z0 = memid & bank id = 000100 multibit mode bit = not used by hardware trail end flag = 1 lcba(25..20) last / end pscb format: lcba(19..0) 20 bits from the global prefix blo ck offset register and previous nbt, pref ix_block_address is calculated to determine reserved (2 bits) 0 5 7 27 28 35 34 0 7 27 28 35 34 0 36 35 56 57 63 62 1 2 27 61 prefix_present_flag = not used = reserved prefix_present_flag = 1 whenev er prefix is present prefix_present_flag = not used by hardware 33 33 maximum pscb depth: 31 all the search keys must equal the maximum prefix length. reserved (5 bits) dt: d3 (a & b) memory only the final lcba. prefix block format: lcba1(25..0) lcba0(25..0) 0 25 31 32 57 58 63 reserved (2 bits) software-defined software-defined ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 303 of 539 8.2.4.6 smt trees software-managed (smt) trees provide a mechanism to create trees that follow a control point function (cpf)-defined search algorithm such as an ip quintuple filtering table containing ipsa, ipda, source port, destination port, and protocol. smt trees use the same ps cbs as fm trees, but only the first leaf following a pscb is shaped by the table 8-17: ludeftable entry definitions on page 307. the following leaves in a leaf chain are shaped according to the five bits in the chaining pointer contained in the nlasmt leaf field (see table 8-13 ). unlike fm and lpm, smt trees allow leaves to specify ranges, for instance, that a source port must be in the range of 100..110. smt trees always contain two patterns of the same length in a leaf to define a comparison range. when the first leaf is found after a pscb, a compare-at-end operation is performed. if ok, the search stops. if the comparison returns ko and the nlasmt field is non-zero, the next leaf is read and another compare-at-end operation is performed. this process continues until an ?ok? is returned or until the nlasmt field is zero, which returns a ko. figure 8-6. example multibit lpm tree layout example (a) multibit lpm tree assumptions: dt: d3 (a & b) memory only 1l0 x 1p0n0 global_prefix_block_offset p1 nbt01 (n1) 1l1 x 0p1n1 (n1) nbt1 p1 p1 nbt1a (n1) (n1) nbt1a 0l3 x 0p3n3 p3 p3 nbt3a (n1) d3a d3b d3c d3d z0 d3a/b direct table pscb prefix block global_prefix_block_offset global_prefix_block_offset ibm powernp np2g network processor preliminary tree search engine page 304 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 8.2.4.7 compare-at-end operation the input key and the two reference patterns stored in each leaf can be logically divided into multiple fields (see figure 8-7 on page 304). one of two comparisons can be performed on each field: 1. compare under mask. the input key bits are compared to pattern0 bits under a mask specified in pattern1. a ?1? in the mask means the corresponding bit in the input key must equal the corresponding bit in pattern0. a ?0? means the corresponding bit in the input key has no influence on the comparison. the entire field matches only when all bits match, in which case the tse returns ok. 2. compare under range. the input key bits are treated as an integer and checked to determine whether the integer is within the range specified by min and max, inclusive. if so, the tse returns ok, otherwise the tse returns ko. when all fields return ok, the entire compare-at-end returns ok. otherwise, ko returns. this operation uses comptabledef for definition and type of compare indication. logical field definitions are specified in the compare definition table compdeftable. table 8-14 shows the entry format for the compdeftable. fields are compare-under-mask unless specified by the compdeftable. each entry specifies one or two range comparisons, although multiple entries can specify more than two range comparisons. each range comparison is defined by offset and length parameters. the offset, which is the position of the first bit in the field, must be at a 16-bit boundary and have a value of 0, 16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 174, or 192. the length of the field must be 8, 16, 24, or 32 bits. table 8-13. nlasmt field format 1 bit 2 bits 3 bits 26 bits reserved width of next leaf height of next leaf nla (next leaf address) figure 8-7. example input key and leaf pattern fields ipsa (32 bits) ipda (32 bits) srcport (16 bits) dstport (16 bits) prot (8 bits) input key value value min min value leaf pattern0 mask mask max max mask leaf pattern1 minmax field1 offset field1 offset field0 length minmax field0 length ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 305 of 539 in the input key shown in figure 8-7: example input key and leaf pattern fields on page 304, the compare- under-range for the source port (srcport) field would have offset0 set to 64 and minmaxlength0 set to 16. the compare-under-range for the destination (dstport) field would have offset1 set to 80 and minmaxlength1 set to 16. if more than two range comparisons are required, the continue bit would be set to 1 so the next compdeftable entry could be used for additional compare-under-range definitions. the compdeftable index used for tree comparisons is specified in the leaf comp_table_index field (see table 8-7: smt tree fixed leaf formats on page 292). each compare-under-range operation takes one clock cycle, so use as few compare-un der-range operations as possible. if a range is a power of two, or 128-255, no compare-under-range is required since this range can be compared using compare-under-mask. when a compare-at-end fails and the smtnla leaf field is not 0, the tse reads the next leaf and performs additional compare-at-end operations until t he compare returns ok or until the smtnla is 0. 8.2.4.8 ropes as shown in the following figure, leaves in a tree can be linked together in a circular list called a rope. the first field in a leaf is the chaining pointer, or the nlarope. picocode can ?walk the rope,? or sequentially inspect all leaves in a rope. ropes can be created by setting the nlarope_en bit to ?1? in the ludeftable. see table 8- 15: ludeftable rope parameters on page 306. table 8-14. compdeftable entry format field range bit length value range 1 offset (r1_offset) 1 8 starting bit position for first range compare. it is defined by compare_table(35 to 28) bits but only 4 upper bits are used to define the offset i.e (bits 35 to 32) and bits (31 to 28) are ignored. therefore, this field must be in 16 bit boundary range 1 length (r1_len) 1 8 length and number of bits to be used as a part of range compare starting/begin- ning from r1_offset.this field is specified as the number of bits multiplied by 4. it is defined by compare_table( 27 to 20) bits, but only 3 msbs are used to define the length (i.e. bits 27,26 & 25) and bits 24 to 20 are ignored. range 2 offset (r2_offset) 2 8 starting bit position for second range compare. it is defined by compare_table(19 to 12) bits but only 4 upper bits are used to define the offset; i.e bits 19 to 16 and bits 15 to 12 are ignor ed. therefore, this field must be in 16- bit bound. range 2 length (r2_len) 2 8 length and number of bits to be used as a part of range compare starting/begin- ning from r2_offset. this field is specifie d as the number of bits multiplied by 4. it is defined by compare_table(11 to 4) bi ts but only 3 msbs are used to define the length (i.e. bits 11 to 9) and bits (8 to 4) are ignored. range 2 valid (r2_valid) -- 1 range 2 valid value. this field indicates whether or not the range 2 offset and length fields are valid. 0 range 1 offset and length valid, but range 2 offset and length not valid. 1 range 1 and range 2 offset and length all valid. it is defined by compare_table(3) bit. continue (cont) -- 1 continue indicator value. this field i ndicates whether the compare operation is continued in the next sequential entry of the table. 0 comparison not continued 1 comparison continued it is defined by compare_table(2) bit. ibm powernp np2g network processor preliminary tree search engine page 306 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 leaf insertion is always done between a ropecla and ropepla. after insertion, the ropepla is unchanged and the ropecla points to the newly inserted leaf. leaf deletion is done two ways: 1. when the rope is not being walked, the rope is a single-chained linked list without a previous pointer. leaves cannot be deleted without breaking the linked list. setting the deletepending bit postpones the deletion until the rope is walked again. a leaf is deleted by setting the deletepending bit of the nlarope field. in this case, leaves ar e completely deleted and leaf pa ttern searches will return a ko. 2. when the rope is being walked and the deletepending bit is set, the tse deletes the leaf automatically. 8.2.4.9 aging aging is enabled whenever a rope is created. the nlarope field contains one aging bit that is set to ?1? when a leaf is created. when a leaf that matches the leaf pattern is found during a tree search, the tse sets the aging bit to ?1? if it has not previously done so, and then writes this information to the control store. an aging function controlled by a timer or other device can walk the rope to delete leaves with aging bits set to ?0? and then write the leaves to the control store with aging bits set to ?0?. when no aging is desired, picocode should not alter the aging bit, since bits set to ?1? cannot be changed. figure 8-8. rope structure table 8-15. ludeftable rope parameters parameter description ropecla current leaf address in the rope. all tse instructions re lated to the rope such as rclr, ardl and tlir (see section 8.2.8 gth hardware assist instructions on page 333) relate to the leaf addressed by ropecla. ropepla previous leaf address in the rope. al ways the previous leaf if the rope is related to ropecla unless the rope contains no leaf or one leaf. the following conditi on is always true for trees with two or more leaves: ropepla -> nlarope == ropecla. leafcnt leaf count - number of leaves in the tree leafth leaf threshold causes an exception to be generated when the leafcnt exceeds the threshold. leaf1 ropecla th leaf2 leaf3 leaf4 leaf0 ropepla leafcnt part of ludeftable ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 307 of 539 8.2.5 tree configuration and initialization 8.2.5.1 the ludeftable the lookup definition table (ludeftable), an internal memory structure that contains 128 entries to define 128 trees, is the main structure that manages the control store. the table indicates in which memory (ddr- sdram, sram, or internal ram) trees exist, whether caching is enabled, key and leaf sizes, and the search type to be performed. each dtentry contains two indexes to the pattern search and leaf free queue (pscb_leaf_fq). the first index defines which memory to use to create tree nodes, that is, where pscbs are located. the second defines which memory to use to create leaves within a tree. when an entry is added to a tree, the memory required for the insert comes from the pscb_leaf_fq and is returned when the entry is deleted. for smt trees, an lu_def_tbl can be defined to match a value into a given range, but an index to an internal compare type index must be given for the compare table (cmp_tbl). table 8-16. nlarope field format 2 bits 1 bit 2 bits 1 bit 26 bits reserved aging counter reserved delete pending nla (next leaf address) table 8-17. ludeftable entry definitions (page 1 of 4) field bit length description cascade_entry/ cache_entry 1 0 normal tree entry (not a cache entry) 1 a cascade/cache entry. when a search returns with ko, and cache_entry = 1, ts instruc- tions will restart using the next entry in the ludeftable (that is, ludefindex + 1). the last ludefindex in the search chain entry mu st have this bit set to ?0? (disabled) when more than 1 table is cascaded. cascading of more than 1 table is allowed. search_type 2 search type value. this field indica tes the type of search to be performed. 00 full match (fm). 01 longest prefix match (lpm). 10 software managed tree (smt). 11 reserved. hash_type 4 hash type 0000 no hash 0001 192-bit ip hash 0010 192-bit mac hash 0011 192-bit network dispatch hash 0100 no hash 0101 48-bit mac swap 0110 60-bit mac swap 0111 reserved 1000 8-bit hash 1001 12-bit hash 1010 16-bit hash note: when using hash_type 1000, 1001, and 1010, hashedkey and hashedkey_length will be extended by 8, 12, or 16 bits, respectively. color_en 1 color enable control value. this field controls whether the co lor value is used to form the hashed key value. 0 color register not used. 1 color register is used ibm powernp np2g network processor preliminary tree search engine page 308 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 p1p2_max_size 5 maximum size of pattern1 and pattern2 in leaf - indicates size in half words (that is, 16 bits) reserved for the ?pattern? as a part of leaf in by tes. the maximum pattern size is 12, which repre- sents 192 bits. p1p2_max_size mapping: 00000 0 byte (no pattern) 00001 2 byte 00010 4 bytes 00011 6 bytes 00100 8 bytes 00101 10 bytes 00110 12 bytes 00111 14 bytes 01000 16 bytes 01001 18 bytes 01010 20 bytes 01011 22 bytes 01100 24 bytes others 0 byte (reserved) notes: for fm: unused bits between p1p2_max_size - hkey_length must be initialized to zero. for lpm: unused bits between (p1p2_max_size - pr efix_length) do not have to be initialized and can be used by user data since these bits do not take part in the comparison. for smt: unused bit between (2 * p1p2_max_size - 2 * hashedkey_length) must be initialized to zero. nlarope_en 1 nla rope enable control value. this field indicates whether or not the leaf contains a next leaf a ddress rope (nla rope) field. 0 leaf does not contain nlarope field 1 leaf contains nlarope field (enables aging) pscb_fq_index 6 pattern search control block free queue index value. this is the index of the pscb free list. reserved 1 reserved. dynamic_multibit_nbt_ en 1 when set to ?1?, multibit nbt pscb format is used during the search, enabl ing 1- or 4-bit com- parison at each pscb node. when set to ?0?, single-bit pscb format (legacy) is used and only one bit will be tested at each pscb node. this mode bit is available in np2g dt_base_addr 26 direct table base address value. note: this field stores flat memory base_addr ess for the mrd and mwr commands with shape_cntl = 01 (flat memory read/write). this base address and leaf_height are used to com- pute the final address. table 8-17. ludeftable entry definitions (page 2 of 4) field bit length description ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 309 of 539 dt_size 4 direct table size value - defines the num ber of dt entries within a memory bank. 0001 4 entries (2 bits) 0010 16 entries (4 bits) 0011 64 entries (6 bits) 0100 256 entries (8 bits) 0101 1 k entries (10 bits) 0110 4 k entries (12 bits) 0111 16 k entries (14 bits) 1000 32 k entries (15 bits) 1001 64 k entries (16 bits) 1010 128 k entries (17 bits) 1011 256 k entries (18 bits) 1100 512 k entries (19 bits) 1101 1 m (20 bits) others reserved leaf_fq_index 6 defines index of leaf free list leaf_width 2 leaf width leaf_height 3 leaf height dynamic_leaf_shape_en 1 this option is valid for the ts_smt and ts_fm commands. when this mode is enabled, each primary leaf can hav e independent shape (size). when this option is set to ?0?, for the fm a nd smt search commands, the leaf shape is defined as per the ludef leaf_width and leaf_height param eters. therefore, each primary leaf has the same shape. when this option is set to ?1?, the five least significant bits of t he nbt field are used to define the shape for that leaf. nbt bits 2:0 define the leaf_height parameter and bits 4:3 define the leaf_width. also, the leaf_height and leaf_width parameters of the ludef table are ignored. this mode bit is available in np2g . leaf_read_disable 1 this option is valid for the ts_lpm command. when this option is set to ?1?, the lpm search al gorithm (at the end of a successful search) will not write the leaf contents to the shared memo ry pool, and only the leaf address is returned. a separate picocode memory read instruction is required to read the leaf content. when this option is set to ?0?, the lpm search al gorithm (at the end of the search) writes the leaf contents back to the shared memory pool and returns the leaf address. this mode bit is available in np2g . ludef_state 2 ludef state - used by product software/user code to indicate current status of the entry. these bits do not affect tree search operation. ludef_invalid 1 indicates whether or not this entry is valid for normal tree s earch command or not. this bit blocks any tree search while the tree is being built or swapped. 0 valid 1invalid when the ludef read request initiated by the tree search command finds this bit set to ?1?, it will re-read this ludefentry every 16 cycles until it is set to valid. this halts the tree search for this particular thread. following fields are valid for gth only ropecla 26 current leaf address for rope. table 8-17. ludeftable entry definitions (page 3 of 4) field bit length description ibm powernp np2g network processor preliminary tree search engine page 310 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 8.2.5.2 tse free lists (tse_fl) the gth has access to a set of 64 tse free list control blocks, each defining a free list using the format shown in table 8-18 . free lists typically chain unused pscbs and leaves into a linked list, but can also be used by picocode to manage memory. the link pointer is stored in the control store at the address of the previous list object. objects stored in different memori es and with different shapes should be placed in different free lists. for example, a list of 64-bit psc bs stored in both zbt sram and internal ram should have different entries. the gth thread executes the tsenqfl and tsdqfl commands to enqueue and dequeue addresses on a free list. see section 8.2.8.3 tree search enqueue free list (tsenqfl) on page 335 and section 8.2.8.4 tree search dequeue free list (tsdqfl) on page 336. a free list of n objects, each with shape of width = w, height = h and a start address of ?a?, is created by enqueueing address a, a+h, a+2h, a+3h, ? a+(n-1)h in the free list. to prevent memory bottlenecks, free lists can also be created in a ?sprayed? manner for objects contained in sdram. for example, when searching a large lpm tree with five pscbs in a single bank, the bank must be accessed five times before reaching a leaf. when the pscbs are sprayed among multiple banks, the number of accesses remains iden- tical but accesses are to multiple banks, thus eliminating bottlenecks. ropepla 26 previous leaf address for rope leafcnt 26 number of leaves in tree leafth 10 threshold for the number of leaves in a tree. if the leafcnt is greater than or equal to this assigned threshold, then a class 0 interrupt is gener ated (bit 9 of the class 0 interrupt vector). checking of the threshold is perform ed only for the tlir rope command. the threshold is formed by the generation of two 26- bit numbers that are bit-wise ored resulting in a threshold value that is compared to the leafcnt: threshold(25:0) = 2**(leafth(9:5))or 2**(leafth(4:0)) table 8-18. free list entry definition field bit length description head 26 free list head address in the control store. tail 26 free list tail address in the control store. qcnt 26 number of entries in the free list. threshold 5 threshold value for the free list control block entry. this field is initialized to 0. the threshold is determined as 2**threshold. w hen the qcnt is less than or equal to the threshold, a class 0 in terrupt (bit 8) is generated. table 8-17. ludeftable entry definitions (page 4 of 4) field bit length description ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 311 of 539 8.2.6 tse registers and register map table 8-19. tse scalar registers for gth only (page 1 of 2) name read/ write hex address bit length description color r/w 00 16 color - see section 8.2.1 input key and color register for fm and lpm trees on page 293 and section 8.2.2 input key and color register for smt trees on page 293. lcba0 r/w 02 26 leaf control block address 0 - typically contains the control store address of the leaf in tsr0, but is also used as an address register for various tse commands. lcba1 r/w 03 26 leaf control block address 1 - typically contains the control store address of the leaf in tsr1, but is also used as an address register for various tse commands. dta_addr r/w 04 26 dtentry address - valid after a hash has been performed. dta_shape r/w 05 5 shape of a dtentry - always (1,1) when di rect leaves are disabled. equals the leaf shape as defined in ludeftable when direct leaves are enabled. always set to ?00000?. hashedkeylen r/w 06 8 pattern length minus 1 in hashedkey. cacheflags r 07 3 see section 8.2.3.3 cascade/cache on page 295. nrpscbs r 08 8 see section 8.2.3.3 cascade/cache on page 295. global_prefix_block_ offset r/w 09 26 see section 8.2.4.5 lpm trees with multibit compare on page 300. hashedkey r/w 0a-0f 192 contains hashedkey hashedkey 191_160 r/w 0a 32 bits 191..160 of hashedkey hashedkey 159_128 r/w 0b 32 bits 159..128 of hashedkey hashedkey 127_96 r/w 0c 32 bits 127..96 of hashedkey hashedkey 95_64 r/w 0d 32 bits 95..64 of hashedkey hashedkey 63_32 r/w 0e 32 bits 63..32 of hashedkey hashedkey 31_0 r/w 0f 32 bits 31..0 of hashedkey ibm powernp np2g network processor preliminary tree search engine page 312 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 ludefcopy r 10-12 96 contains lu_def_table index in use an d a copy of the following lu_def_table fields: field bits definition reserved 95:88 x?00? reserved lu_def_index 87:80 index of the location from where the content was read. for remaining field definitions, see table 8-17: ludeftable entry definitions on page 307, with exceptions noted. lu_def_invalid 79 lu_def_state 78:77 lpm_leaf_read_disable 76 dynamic_leaf_shape_en 75 leaf_height 74:72 leaf_width 71:70 leaf_fq_index 69:64 dt_size 61:58 dt_base_addr 57:32 reserved 31:24 dynamic_multibit_nbt_en 23 reserved 22 pscb_fq_index 21:16 reserved 15:14 reserved nla_rope_ena 13 p1p2_max_size 12:8 color_ena 7 hash_type 6:3 search_type 2:1 cascade/cache entry 0 ludefcopy 95_64 r 10 32 bits 95:64 of the ludefcopy register ludefcopy 63_32 r 11 32 bits 63..32 of ludefcopy ludefcopy 31_0 r 12 32 bits 31..0 of ludefcopy setpatbit_gdh_4bit r/w 1c 4 contains 4 bits from the pattern stor ed in tsrx. set by the setpatbit_gdh command. setpatbit_gdh r/w 1b 1 contains one bit from the pattern stored in tsrx. set by setpatbit_gdh command. distposreg_gdh r 1a 8 contains result of distpos command from distpos_gdh ludefcopy_gdh r 19 26 contains ludeftable index in use and a copy of the following ludeftable fields: dynamic_leaf_shape_en ludefcopy_gdh(25) reserved ludefcopy_gdh(24, 23) reserved ludefcopy_gdh(22, 21) p1p2_max_size ludefcopy_gdh(20 to 16) dt_size ludefcopy_gdh(15 to 12) nlarope_en ludefcopy_gdh(11) color_en ludefcopy_gdh(10) tree_type ludefcopy_gdh(9,8) ludeftable_index ludefcopy_gdh(7 to 0) ludefcopy_gdh 31_0 r 19 26 bit 31..0 of ludefcopy_gdh table 8-19. tse scalar registers for gth only (page 2 of 2) name read/ write hex address bit length description ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 313 of 539 table 8-20. tse array registers for all gxh name read/ write starting hex address ending hex address bit length description tsr0 r/w 32 47 2048 tree search result area 0 note: portion of the data overlaps with tsr1 tsr1 r/w 40 47 1024 tree search result area 1 note: portion of the data overlaps with tsr0 tsr2 r/w 48 63 2048 tree search result area 2 note: portion of the data overlaps with tsr3 tsr3 r/w 56 63 1024 tree search result area 3 note: portion of the data overlaps with tsr2 note: in this table, starting and ending address r epresents the offset for a given thread's starting address in the shared memory poo l. table 8-21. tse registers for gth (tree management) name read/ write hex address bit length description patbit_tsr0 r/w 1e 1 contains one bit from the pattern stored in tsr0. set by trs0pat command. distposreg r 1f 8 contains result of distpos command luropecopyth r 13 10 contains copy of leafth field of ludeftable luropecopyqcnt r 14 26 contains copy of leafcnt field of ludeftable luropecopyprev r 15 26 contains copy of ropepla field of ludeftable luropecopycurr r 16 26 contains copy of ropecla field of ludeftable table 8-22. tse scalar registers for gdh and gth name read/ write hex address bit length description lcba0 r/w 02 31 leaf control block address 0 - typically contains the control store address of the leaf in tsrx, but is also used as an add ress register for various tse commands. bits 30:26 the leaf control block a ddress shape which is used by cmpend instruction only bits 25:0 leaf control block address lcba1 r/w 03 31 leaf control block address 1 - typically contains the control store address of the leaf in tsrx, but is also used as an add ress register for various tse commands. bits 30:26 the leaf control block a ddress shape which is used by cmpend instruction only bits 25:0 leaf control block address cacheflags r 07 3 see section 8.2.3.3 cascade/cache on page 295 nrpscbs r 08 8 see section 8.2.3.3 cascade/cache on page 295. setpatbit_gdh r 1b 1 contains one bit from the pattern stored in tsrx. set by setpatbit_gdh command. global_prefix_block_ offset r/w 09 26 see section 8.2.4.5 lpm trees with multibit compare on page 300. ibm powernp np2g network processor preliminary tree search engine page 314 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 setpatbit_gdh_4bit r 1c 4 contains four bits from the pattern st ored in tsrx. set by the setpatbit_gdh command. distposreg_gdh r 1a 8 contains result of distpos command from distpos_gdh ludefcopy_gdh r 19 26 contains ludeftable index in use and a copy of the followi ng ludeftable fields: dynamic_leaf_shape_en ludefcopy_gdh(25) reserved ludefcopy_gdh(24,23) reserved ludefcopy_gdh(22,21) p1p2_max_size ludefcopy_gdh(20 to 16) dt_size ludefcopy_gdh(15 to 12) nlarope_en ludefcopy_gdh(11) color_en ludefcopy_gdh(10) tree_type ludefcopy_gdh(9,8) ludeftable_index ludefcopy_gdh(7 to 0) table 8-23. pscb register format field bit length control store address for pscb npa0 26 next pscb address - pointer to next pscb in tree for pscb part 0 nbt0 8 next bit to test for pscb part 0 lcba0 26 leaf control block address: pointer to leaf for pscb part 0 npa1 26 next pscb address - pointer to next pscb in tree for pscb part 1 nbt1 8 next bit to test for pscb part 1 lcba1 26 leaf control block address - pointer to leaf for pscb part 1 index 8 index of current pscb physi cally stored in previous pscb patbit 1 value of hashedkey[index] based on va lue of index field in pscb register table 8-24. tse gth indirect registers (page 1 of 2) indirect register bit length description notes pscbx.npa_hk 26 selects either the npa0 field from pscbx or the npa1 field depending on value of register pscbx.index 1, 2, 3 pscbx.npa_tsr0 26 selects either the npa0 field from pscbx or the npa1 field depending on value of register patbit_tsr0. (register patbit_t sr0 must have been initialized previously using tsr0pat command) 1, 2, 4 pscbx.nbt_hk 8 selects either the nbt0 field from pscb x or the nbt1 field depending on value of register pscbx.index 1, 2, 3 pscbx.nbt_tsr0 8 selects either the nbt0 field from pscb x or the nbt1 field depending on value of register patbit_tsr0 1, 2, 4 pscbx.lcba_hk 26 selects either the lcba0 field from psc bx or the lcba1 field depending on value of register pscbx.index 1, 2, 3 pscbx.lcba_tsr0 26 selects either the lcba0 field from psc bx or the lcba1 field, depending on value of register patbit_tsr0 1, 2, 4 pscbx.notnpa_hk 26 selects either the npa0 field from pscbx or the npa1 field depending on inverse value of register pscbx.index 1, 2, 3 table 8-22. tse scalar registers for gdh and gth name read/ write hex address bit length description ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 315 of 539 pscbx.notnpa_tsr0 26 selects either the npa0 field from pscbx or the npa1 field depending on inverse value of register patbit_tsr0 1, 2, 4 pscbx.notnbt_hk 8 selects either the nbt0 field from ps cbx or the nbt1 field depending on inverse value of register pscbx.index 1, 2, 3 pscbx.notnbt_tsr0 8 selects either the nbt0 field from ps cbx or the nbt1 field depending on inverse value of register patbit_tsr0 1, 2, 4 pscbx.notlcba_hk 26 selects either the lcba0 field from pscbx or the lcba1 field depending on inverse value of register pscbx.index 1, 2, 3 pscbx.notlcba_tsr0 26 selects either the lcba0 field from pscbx or the lcba1 field depending on inverse value of register patbit_tsr0 1, 2, 4 1. x must equal 0, 1, or 2. 2. the indirect registers of the tse se lect, via dedicated hardware assist, one of the tse registers listed in section 8.2.6 tse regis- ters and register map on page 311. the indirect registers appear in the t se register map with a unique register number. 3. pscbx.index points to a specific bit in t he hashedkey. the bit?s value determines w hether the 0 or 1 part of pscbx will be re ad or written. 4. value of patbit_tsr0 determines whether the 0 or 1 part of pscbx will be read or written. table 8-25. address map for pscb0-2 registers in gth pscbx read/write pscb0 pscb1 pscb2 size npa0 r/w 80 a0 c0 26 nbt0 r/w 81 a1 c1 8 lcba0 r/w 82 a2 c2 26 npa1 r/w 84 a4 c4 26 nbt1 r/w 85 a5 c5 8 lcba1 r/w 86 a6 c6 26 addr r/w 88 a8 c8 26 index r/w 89 a9 c9 8 patbit r 8b ab cb 1 npa_hk r/w 90 b0 d0 26 nbt_hk r/w 91 b1 d1 8 lcba_hk r/w 92 b2 d2 26 notnpa_hk r/w 94 b4 d4 26 notnbt_hk r/w 95 b5 d5 8 notlcba_hk r/w 96 b6 d6 26 npa_tsr0 r/w 98 b8 d8 26 nbt_tsr0 r/w 99 b9 d9 8 lcba_tsr0 r/w 9a ba da 26 notnpa_tsr0 r/w 9c bc dc 26 notnbt_tsr0 r/w 9d bd dd 8 notlcba_tsr0 r/w 9e be de 26 table 8-24. tse gth indirect registers (page 2 of 2) indirect register bit length description notes ibm powernp np2g network processor preliminary tree search engine page 316 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 8.2.7 tse instructions the tree search engine (tse) provid es facilities for conducting and managing tree searches. two tse coprocessor interfaces are provided for each thread: tse0 and tse1. therefore, each thread can issue instructions to each of these tse0 and tse1 resources. general tse instructions can be executed by both tse0 and ts1 in any thread. table 8-26. general tse instructions opcode command detail section 0null 1ts_fm 8.2.7.1 fm tree search (ts_fm) on page 317 2 ts_lpm 8.2.7.2 lpm tree search (ts_lpm) on page 318 3 ts_smt 8.2.7.3 smt tree search (ts_smt) on page 320 4mrd 8.2.7.4 memory read (mrd) on page 321 5mwr 8.2.7.5 memory write (mwr) on page 322 6hk 8.2.7.6 hash key (hk) on page 323 7 rdludef 8.2.7.7 read ludeftable (rdludef) on page 324 8 compend 8.2.7.8 compare-at-end (compend) on page 326 9 distpos_gdh 8.2.7.9 distinguish position for fast table update (distpos_gdh) on page 327 10 rdpscb_gdh 8.2.7.10 read pscb for fast table update (rdpscb_gdh) on page 328 11 wrpscb_gdh 8.2.7.11 write pscb for fast table update (wrpscb_gdh) on page 330 12 setpatbit_gdh 8.2.7.12 setpatbit_gdh on page 331 13 to 15 reserved note: commands can be executed by all gxhs with threads. figure 8-9. general layout of tse fields in shared memory pool leaf userdata pattern (103..0) from leaf leaf userdata pattern (191..104) from leaf prefix nla rope reserved dta shape dta (26 bits) hashedkey(191..104) reserved hashedkey(103..0) hkeylen reserved reserved keylen color key(191..96) key (95..0) 127 119 111 95 31 0 31 87 23 70 tsedpa tsedpa+1 tsedpa+2 tsedpa+3 tsedpa+4 tsedpa+5 63 127 96 121 (5 bits) tsedpa+6 tsedpa+7 ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 317 of 539 8.2.7.1 fm tree search (ts_fm) table 8-27. fm tree search input operands operand bit length operand source description direct indirect ludefindex 8 imm16(12..5) gpr(7..0) defines entry in ludeftable that controls the search. lcbanr 1 imm16(0) imm12(0) 0 search results are stored in tsrx/lcba0. 1 search results are stored in tsrx/lcba1. tsedpa 4 imm16(4..1) imm12(4..1) tse thread shared memory pool address. stores location of key, key- length, and color and determines leaf destination. the tsedpa is the high order 4 bits of the thread' s shared memory pool address (see 7.2.4 shared memory pool on page 172) and is constrained to be on a four-qw boundary. use only values of x?8?, x?a?, x?c?, and x?e?. key 192 shared memory pool pattern to be searched, located in shared memory pool. the key must be initialized only in the byte boundary of the key length. keylength 8 shared memory pool length of pattern minus 1 in key. must be initialized before search. located in shared memory pool. color 16 shared memory pool used only when enabled in ludeftable. must be initialized before search. located in shared memory pool. following is available for gth only. useludefcopyreg 1 imm16(13) imm12(5) enables tse read of ludefcopy regi ster. can save clock cycles, espe- cially when rdludef is executed as ynchronously with the picocode that sets the key. 0 tse reads ludeftable. 1 tse does not read the ludeftable and uses information con- tained in ludefcopy register. assumes ludeftable was read pre- viously using rdludef. ludefcopy 96 register input only when useludefcopyreg is ?1?. table 8-28. fm tree search results (tsr) output (page 1 of 2) result bit length source description ok/ko 1 flag 0 ko: unsuccessful operation. 1 ok: successful operation. tsrx 512 shared memory pool when ok/ko is ?1?, leaf is read and stored in tsrx. tsrx is mapped into the shared memory pool, at an offset of 4 qw past the starting qw indicated by the input tsedpa parameter. that is, the shared memory pool qw location = tsedpa*4 + 4 lcba0 / 1 26 register when ok/ko is ?1?, leaf address is stored in lcba0 / 1. cacheflags 3 register see section 8.2.3.3 cascade/cache on page 295. nrpscbs 8 register see section 8.2.3.3 cascade/cache on page 295. ibm powernp np2g network processor preliminary tree search engine page 318 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 8.2.7.2 lpm tree search (ts_lpm) ludefcopy_gdh 26 register contains ludeftable index in us e and a copy of the following ludeftablefields: dynamic_leaf_shape_en ludefcopy_gdh(25) reserved ludefcopy_gdh(24,23) reserved ludefcopy_gdh(22,21) p1p2_max_size ludefcopy_gdh(20 to 16) dt_size ludefcopy_gdh(15 to 12) nlarope_en ludefcopy_gdh(11) color_en ludefcopy_gdh(10) tree_type ludefcopy_gdh(9,8) ludeftable_index ludefcopy_gdh(7 to 0) will be stored in scalar register and its address in register address map is ?019?. following is available for gth only. ludefcopy 96 register output only when useludefcopyreg is ?0?. set to contents of ludeftable at entry pointed to by ludefindex. table 8-29. lpm tree search input operands (page 1 of 2) operand bit length operand source description direct indirect ludefindex 8 imm16(12..5) gpr(7..0) defines entry in ludeftable used to control the search lcbanr 1 imm16(0) imm12(0) 0 search results are stored in tsrx/lcba0 1 search results are stored in tsrx/lcba1 tsedpa 4 imm16(4..1) imm12(4..1) tse thread shared memory pool addres s. stores location of key, key- length, and color and determines leaf destination. the tsedpa is the high order 4 bits of the thread' s shared memory pool address (see 7.2.4 shared memory pool on page 172) and is constrained to be on a four-qw boundary. use only values of x?8?, x?a?, x?c?, and x?e?. key 192 shared memory pool pattern to be searched, located in shared memory pool. the key must be initialized only in the byte boundary of the key length. keylength 8 shared memory pool length of pattern minus 1 in key. must be initialized before search. located in shared memory pool. color 16 shared memory pool used only when enabled in ludeftable. must be initialized before search. located in shared memory pool. global_prefix_block_ offset 20 register contains global prefix offset used by multibit lpm trees. required when dynamic_mul tibit_nbt_en is enabled. will be stored in scalar register, and its address in the register address map is x?009?. table 8-28. fm tree search results (tsr) output (page 2 of 2) result bit length source description ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 319 of 539 following is available for gth only. useludefcopyreg 1 imm16(13) imm12(5) enables tse read of ludefcopy register can save clock cycles, especiall y when rdludef is executed asyn- chronously with the picocode that sets the key. 0 tse reads ludeftable 1 tse does not read the ludeftabl e and uses information con- tained in ludefcopy register. assumes ludeftable was read pre- viously using rdludef. note: useludefcopyreg = ?1? is not supported for ludefentry with cache_enable. ludefcopy 96 register input only when useludefcopyreg is ?1?. set to contents of ludeftable at entry given by ludefindex. table 8-30. lpm tree search results output result bits source description ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation tsrx 512 shared memory pool when ok/ko is ?1?, leaf is read and stored in tsrx tsrx is mapped into the shared memory pool, at an offset of 4 qw past the starting qw indicated by the input tsedpa parameter. that is, shared memory pool qw location = tsedpa*4 + 4 lcba0 / 1 26 register when ok/ko is ?1?, leaf address is stored in lcba0 / 1 cacheflags 3 register see section 8.2.3.3 cascade/cache on page 295 nrpscbs 8 register see section 8.2.3.3 cascade/cache on page 295 ludefcopy_gdh 26 register contains ludeftable index in us e and a copy of the following ludeftablefields: dynamic_leaf_shape_en ludefcopy_gdh(25) reserved ludefcopy_gdh(24,23) reserved ludefcopy_gdh(22,21) lp1p2_max_size ludefcopy_gdh(20 to 16) dt_size ludefcopy_gdh(15 to 12) nlarope_en ludefcopy_gdh(11) color_en ludefcopy_gdh(10) tree_type ludefcopy_gdh(9,8) ludeftable_index ludefcopy_gdh(7 to 0) will be stored in scalar register, and its address in the register address map is ?019?. the following is av ailable for gth only. ludefcopy 96 register output only when useludefcopyreg is ?0?. set to contents of ludeftable at entry given by ludefindex. table 8-29. lpm tree search input operands (page 2 of 2) operand bit length operand source description direct indirect ibm powernp np2g network processor preliminary tree search engine page 320 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 8.2.7.3 smt tree search (ts_smt) table 8-31. smt tree search input operands operand bit length operand source description direct indirect ludefindex 8 imm16(12..5) gpr(7..0) defines entry in ludeftable used to control the search lcbanr 1 imm16(0) imm12(0) 0 search results are stored in tsrx/lcba0 1 search results are stored in tsrx/lcba1 tsedpa 4 imm16(4..1) imm12(4..1) tse thread shared memory pool addr ess - stores location of key, keylength, and color and determines leaf destination. the tsedpa is the high order 4 bits of the thr ead's shared memory pool address (see 7.2.4 shared memory pool on page 172) and is constrained to be on a four-qw boundary. use only values of x?8?, x?a?, x?c?, and x?e?. key 192 shared memory pool pattern to be searched, located in shared memory pool. the key must be initialized only in the byte boundary of the key length. keylength 8 shared memory pool length of pattern minus 1 in key. must be initialized before search. located in shared memory pool. color 16 shared memory pool used only when enabled in ludeftable. must be initialized before search. located in shared memory pool. following is available for gth only. useludefcopyreg 1 imm16(13) imm12(5) enables tse read of ludefcopy register can save clock cycles, especially when rdludef is executed asyn- chronously with the picocode that sets the key. 0 tse reads ludeftable 1 tse does not read the ludeftable and uses information con- tained in ludefcopy register. assumes ludeftable was read previ- ously using rdludef. note: useludefcopyreg = ?1? is not supported for ludefentry with cache enable. ludefcopy 96 register input only when useludefcopyreg is ?1?. set to contents of ludeftable at entry given by ludefindex. table 8-32. smt tree search results output (page 1 of 2) result bit length source description ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation tsrx 512 shared memory pool when ok is ?1?, leaf is read and stored in tsrx. tsrx is mapped into the shared memory pool, at an offset of 4 qw past the starting qw indicated by the input tsedpa parameter. that is, shared memory pool qw location = tsedpa*4 + 4 lcba0 / 1 26 register when ok is ?1?, leaf address is stored in lcba0 / 1 cacheflags 3 register see section 8.2.3.3 cascade/cache on page 295 nrpscbs 8 register see section 8.2.3.3 cascade/cache on page 295 ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 321 of 539 8.2.7.4 memory read (mrd) the memory read command provides di rect read capability from any location in the co ntrol store. lcba0 / 1 provide the full read address. shape is provided by the ludeftable (for leaf or pscb) or directly as part of the command field for the object. the content to be read is stored in tsrx. when flat memory mode (shape_cntl = 01) is selected, the 20 least significant bits in lcba0/1 contain the offset that is used with leaf shape and dt_base_addr from the ludeftable to compute the final address to be read. in flat memory mode, the following rules are applied: the 20 least significant bits in lcba0/1 can be used as an offset; the remaining bits are ignored. valid leaf shape heights are 1, 2, and 4; no other heights are supported. during final address computation, address spanning is not allowed. flat memory mode is valid for np2g. ludefcopy_gdh 26 register contains ludeftable index in us e and a copy of the following ludeftablefields: dynamic_leaf_shape_en ludefcopy_gdh(25) reserved ludefcopy_gdh(24,23) reserved ludefcopy_gdh(22,21) p1p2_max_size ludefcopy_gdh(20 to 16) dt_size ludefcopy_gdh(15 to 12) nlarope_en ludefcopy_gdh(11) color_en ludefcopy_gdh(10) tree_type ludefcopy_gdh(9,8) ludeftable_index ludefcopy_gdh(7 to 0) will be stored in scalar register, and its address in register address map is ?019?. following are available for gth only. ludefcopy 96 register an output only when useludefcopyreg is ?0?. set to contents of ludeftable at entry given by ludefindex. table 8-33. memory read input operands (page 1 of 2) operand bit length operand source description direct indirect shapectrl 2 imm16(14..13) gpr(9..8) 00 direct shape. 01 flat mode. leaf_shape_height and dt_base_addr from ludeftable are used with the lcba0/1 field to compute the address to be read. leaf shape from ludeftable is used as a shape. when this mode is select ed, the final address to be read = dt_base_addr + (lcba0/1 * leaf_shape_height). 10 pscb shape is based on addr ess and tree type from ludeft- able. that is, lpm tree type and zbt or h1 address shape will be set to (1x2), and for any other case, shape will be set to (1x1). 11 leaf shape from ludeftable ludefindex 8 imm16(12..5) gpr(7..0) ludeftable entry used to read shape information. valid only when shapectrl is ?01?, ?10? or ?11?. width 2 imm16(9..8) gpr(4..3) width of object to be read. valid only when shapectrl is ?00?. table 8-32. smt tree search results output (page 2 of 2) result bit length source description ibm powernp np2g network processor preliminary tree search engine page 322 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 8.2.7.5 memory write (mwr) the memory write command pr ovides direct write capability to any lo cation in the contro l store. lcba0 / 1 provide the full write address. shape is provided by the ludeftable (for leaf or pscb) or directly as part of the command field for the object. the content to be written is stored in tsrx. when flat memory mode (shape_cntl = 01) is selected, the 20 least significant bits in lcba0/1 contain the offset that is used with leaf shape and dt_base_addr from the ludeftable to compute the final address to be read. in flat memory mode, the following rules are applied: the 20 least significant bits in lcba0/1 can be used as an offset; the remaining bits are ignored. valid leaf shape heights are 1, 2, and 4; no other heights are supported. during final address computation, address spanning is not allowed. flat memory mode is valid for np2g. height 3 imm16(7..5) gpr(2..0) height of object to be read. valid only when shapectrl is ?00?. tsedpa 4 imm16(4..1) imm12(4..1) tse thread shared memory pool address determines the destina- tion location for the data to be read. the tsedpa is the high order 4 bits of the thread's shared memory pool address (see 7.2.4 shared memory pool on page 172) and is constrained to be on a four-qw boundary. lcbanr 1 imm16(0) imm12(0) 0 address to be read is lcba0 1 address to be read is lcba1 lcba0 / 1 26 register address to be read when shapectrl is set to ?00?, ?10?, or ?11?. this operand contains the offset used for address computation when shapectrl is set to ?01?. table 8-34. memory read output results result bit length source description tsrx 512 shared mem- ory pool tsrx is mapped into the shared memory pool , starting at the qw indicated by the input tsedpa parameter for a length of 4 qw. ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation table 8-33. memory read input operands (page 2 of 2) operand bit length operand source description direct indirect ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 323 of 539 8.2.7.6 hash key (hk) table 8-35. memory write input operands operand bit length operand source description direct indirect shapectrl 2 imm16(14..13) gpr(9..8) 00 direct shape 01 flat mode. leaf_shape_height and dt_base_addr from ludeftable are used with lcba0/1 field to compute the address to be written. leaf shape from ludeftable is used as a shape. when this mode is selected, final address to be written = dt_base_addr + (lcba0/1 * leaf_shape_height). 10 pscb shape is based on address and tree type from ludeftable. that is, lpm tree type and zbt or h1 address shape will be set to (1x2), and for any other case, shape will be set to (1x1). 11 leaf shape from ludeftable ludefindex 8 imm16(12..5) gpr(7..0) ludeftable entry used to read shape information. valid only when shapectrl is ?01?, ?10? or ?11?. width 2 imm16(9..8) gpr(4..3) width of object to be written. valid only when shapectrl is ?00?. height 3 imm16(7..5) gpr(2..0) height of object to be written. valid only w hen shapectrl is ?00?. tsedpa 4 imm16(4..1) imm12(4..1) tse thread shared memory pool addr ess determines the source location for the data to be written. the tsedpa is the high order 4 bits of the thread's shared memo ry pool address (see 7.2.4 shared memory pool on page 172) and is constrained to be on a four-qw boundary. lcbanr 1 imm16(0) imm12(0) 0 address to be written is lcba0 1 address to be written is lcba1 lcba0 / 1 26 register address to be read when shapectrl is set to ?00?, ?10?, or ?11?. this operand contains the offset us ed for address computation when shapectrl is set to ?01?. tsrx 512 shared memory pool data to be written. tsrx is mapped into the shared memory pool, starting at the qw indicated by the input tsedpa parameter for a length of 4 qw. table 8-36. hash key input operands operand bit length operand source description direct indirect ludefindex 8 imm16(12..5) gpr(7..0) defines entry in ludeftable containing hash type tsedpa 4 imm16(4..1) imm12(4..1) tse thread shared memory pool addres s - stores location of key, key- length, and color and determines hash key destination. the tsedpa is the high order 4 bits of the thread's shared memory pool address (see 7.2.4 shared memory pool on page 172) and is constrained to be on a four- qw boundary. use only values of x?8?, x?a?, x?c?, and x?e?. direct_ hashtype_en 1 imm16(0) imm12(0) enable direct hashtype definition 0 hashtype defined by ludefentry 1 hashtype defined via command direct_ hashtype 4 imm16(8..5) gpr(3..0) use defined hash type for hashing. valid when direct_hashtype_en = 1 ibm powernp np2g network processor preliminary tree search engine page 324 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 8.2.7.7 read ludeftable (rdludef) rdludef reads ludeftable at a specified entry and stores the result in the ludefcopy register field in the shared memory pool.the tse can read ludeftable while picocode builds a key because rdludef is executed asynchronously. key 192 shared memory pool pattern to be searched, located in shared memory pool. the key must be initialized only in the byte boundary of the key length. keylen 8 shared memory pool defines length of pattern minus 1 in key. must be initialized before search. located in the shared memory pool. color 16 shared memory pool must be initialized before search - used only when enabled in ludeftable. located in the shared memory pool. invalid when direct_hashtype_en is set to value ?1?. table 8-37. hash key output results result bit length source description hashedkeyreg 192 shared memory pool hashed key register - cont ains the hashedkey (incl uding color when enabled in ludeftable) according to section 8.2.1 input key and color register for fm and lpm trees on page 293 and section 8.2.2 input key and color register for smt trees on page 293. hash function is defined in the ludeftable. stored in the shared memory pool qw location = tsedpa*4 + 2 & 3. hashedkeylen 8 shared memory pool hashed key length contains the length of pa ttern minus 1 in hashedkeyreg. stored in the shared memory pool qw location = tsedpa*4 + 3 bit (7:0). dta 26 shared memory pool dtentry address. stored in shared memory pool qw location = tsedpa*4 + 2, bits (121:96). note: not valid when direct_hashtype_en is set to value ?1?. ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation ludefcopy_gdh 26 register contains ludeftable index in use and a copy of the following ludeftablefields: dynamic_leaf_shape_en ludefcopy_gdh(25) reserved ludefcopy_gdh(24,23) reserved ludefcopy_gdh(22,21) p1p2_max_size ludefcopy_gdh(20 to 16) dt_size ludefcopy_gdh(15 to 12) nlarope_en ludefcopy_gdh(11) color_en ludefcopy_gdh(10) tree_type ludefcopy_gdh(9,8) ludeftable_index ludefcopy_gdh(7 to 0) will be stored in scalar register, and its address in register address map is ?019?. the following is available for gth only. ludefcopy 96 register set to contents of ludeftable at entry given by ludefindex. table 8-36. hash key input operands operand bit length operand source description direct indirect ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 325 of 539 figure 8-10. general layout of tse rdludef in shared memory pool table 8-38. rdludef input operands operand bit length operand source description direct indirect ludefindex 8 imm16(12..5) gpr(7..0) defines entry in ludeftable tsedpa 4 imm16(4..1) imm12(4..1) tse thread shared memory pool address determines the destination location for the ludeftable entry data to be read. the tsedpa is the high order 4 bits of the thread' s shared memory pool address (see 7.2.4 shared memory pool on page 172) and is constrained to be on a four-qw boundary. table 8-39. rdludef output results result bit length source description ludefcopy 88 shared memory pool set to contents of ludeftable at entry given by ludefindex and stored in shared memory pool. the entry is placed into two qw starting at the qw indicated by the tsedpa. the entry is right-j ustified with the most signi ficant bits padded with 0. various fields of ludefentry are at t he same bit position as in the ludeftable memory. (111 to 32) bits represent t he ludefentry contents and bits (119 to 112) represents the corresponding ludefindex. they are left-justified. note: tsedpa address and tsedpa + 1 will be overwritten during this command. contents of ludefcopy will be returned at tsedpa and contents of ludefcopy_rope will be returned in the next address. ludefc opy_rope content will be valid for the gth thread. ludefcopy_gdh 26 register contains ludeftable index in use and a copy of the following ludeftablefields: dynamic_leaf_shape_en ludefcopy_gdh(25) reserved ludefcopy_gdh(24, 23) reserved ludefcopy_gdh(22, 21) p1p2_max_size ludefcopy_gdh(20 to 16) dt_size ludefcopy_gdh(15 to 12) nlarope_en ludefcopy_gdh(11) color_en ludefcopy_gdh(10) tree_type ludefcopy_gdh(9,8) ludeftable_index ludefcopy_gdh(7 to 0) will be stored in scalar register and its addr ess in register address map is ?019?. ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation ludefindex ludeftable entry (111..32) ludeftable_rope entry (95 ..0) (gth only) 127 120 119 112 0 tsedpa tsedpa+1 111 reserved 95 reserved reserved 32 31 ibm powernp np2g network processor preliminary tree search engine page 326 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 8.2.7.8 compare-at-end (compend) compend performs a compare-at-end operation for smt trees. after a tree search command has performed a full search including a compend, picocode can obtain a pointer to another leaf chain from the leaf and start another compend on the leaf chain. the first leaf chain could contain leaves with filtering information, and the second could contain leaves with quality of service informat ion. compend should be used only after a tree search command. the compend command uses key instead of hashedkey during operation, since it is assumed that hashing is not needed for smt. hence, the key field is read by the command, not the hashedkey field. for np2g, it is not necessary to initialize the unused key bits to zero. table 8-40. compend input operands operand bit length operand source description direct indirect ludefindex 8 imm16(12:5) gpr(7:0) define s the entry in the ludeftable. lcbnanr 1 imm16(0) imm12(0) 0 search results are stored in tsrx/lcba0 1 search results are stored in tsrx/lcba1 tsedpa 4 imm16(4..1) imm12(4..1) tse thread shared memory pool ad dress - stores location of key, keylength, and color and determines leaf destination. the tsedpa is the high order 4 bits of the thread?s shared memory pool address (see 7.2.4 shared memory pool on page 172) and is constrained to be on a four-qw boundary. use only val ues of x?8?, x?a? , x?c?, and x?e?. lcba0 / 1 31 register start address of leaf chain and its shape. bits: 30:29 leaf width 28:26 leaf height 25:0 leaf address note: a valid leaf width and leaf height must be provided with the leaf address. key 192 shared memory pool input of previous tree search command located in the shared memory pool at an offset of 0 and 1qw from the qw indicated by the tsedpa. keylen 8 shared memory pool input of previous tree search command located in the shared memory pool at the qw indicated by the tsedpa table 8-41. compend output results result bit length source description ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation tsrx 512 shared mem- ory pool when ok is ?1?, leaf is read and stored in tsrx when ok is ?0?, last leaf of chain is stored in tsrx tsrx is mapped into the shared memory pool , starting at an offset of 4 qw past the qw indicated by the input tsedpa parameter for a length of 4 qw. lcba0 / 1 26 register when ok is ?1?, leaf address is stored in lcba0 / 1 when ok is ?0?, leaf address of last leaf in chain is stored in lcba0 / 1 note: shape for the corresponding leaf will not be valid when lcaba0/1 is read. ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 327 of 539 8.2.7.9 distinguish position for fast table update (distpos_gdh) distpos_gdh performs a pattern compare between the pattern stored in hashedkey of the shared memory pool and a pattern from the leaf specified in tsrx. the result is stored in the distposreg_gdh register. the ok flag is set when a full match has been detected. figure 8-11. shared memory pool wit h distpos_gdh co mmand subfields table 8-42. distpos_gdh input operands operand bit length operand source description direct indirect tsedpa_leaf 4 imm16(4..1) imm12(4..1) indicates the leaf storage location in the thread shared memory pool. the tsedpa_leaf is the hi gh order 4 bits of the thread?s shared memory pool address (see 7.2.4 shared memory pool on page 172) and is constrained to be on a four-qw boundary. use only values of x ?8?, x ?a?, x ?c?, and x ?e?. tsedpa_hk 4 imm16(8..5) imm12(8..5) indicates the hashedkey storage location in the thread shared memory pool. the tsedpa is the high order 4 bits of the thread?s shared memory pool address (see 7.2.10 shared memory pool) and is constrained to be on a four-qw boundary. use only values of x ?8?, x ?a?, x ?c?, and x ?e?. hashedkey is assumed to be stored at tsedpa +2 location in shared memory pool. hashedkey 192 shared memory pool contains the hashed pattern and it will be stored at tsedpa_hk +2 (7..0) quad word location. the structure of the hashed key in shared memory pool is shown in figure 8-11 . hashedkeylen 8 shared memory pool contains length of hashed pattern minus 1. stored at tsedpa_hk +2 quad word location. structure of hashed key in shared memory pool is shown in figure 8-11 . tsrx 512 shared memory pool contains second pattern with pattern length (for lpm & fm only). tsrx is mapped into the shared memory pool, starting at an offset of 4 qw past the qw indicated by the input tsedpa_leaf parameter for a length of 4 qw. leaf userdata pattern (103..0) from leaf leaf userdata pattern (191..104) from leaf prefix nla rope reserved dta shape dta (26 bits) hashedkey (191..104) reserved hashedkey (103..0) hkeylen reserved reserved keylen color key (191..96) key (95..0) 127 119 111 95 31 0 31 87 23 70 tsedpa_hk tsedpa_hk+1 tsedpa_hk+2 tsedpa_hk+3 tsedpa_leaf tsedpa_leaf+1 63 127 96 121 (5 bits) ibm powernp np2g network processor preliminary tree search engine page 328 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 distpos_gdh applies to lpm and fm only. it needs p1p2_max_size value as a part of the computation. the value is assumed to be valid prior to this command. this value is stored as a scalar register, and is inde- pendent for each thread. 8.2.7.10 read pscb for fast table update (rdpscb_gdh) rdpscb_gdh reads a pscb from the control store and stores it in one of the pscbx locations in the shared memory pool. for lpm, the entire pscb is read from memory at the address given by pscb.addr and stored in pscb. for fm, the entire pscb is read from memory and converted into a lpm pscb format and either npa0/1 or lcba0/1 will be set to all zero, sinc e only one of the fields w ill be valid. this command is not supported for smt. structure for pscb register shared memory pool is as follows: table 8-43. distpos_g dh output results result bit length source description ok/ko 1 flag 0 pattern does not match 1 pattern in hashedkey matches pattern in tsrx distposreg_gdh 8 scalar register smallest bit position where pattern in ha shedkey differs from pattern in tsrx. will be stored in scalar register and its addr ess in the register address map is ?01a?. ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation figure 8-12. shared memory pool with pscb subfields lcba1 address reserved index npa0 reserved 127 87 95 31 0 pscbx dpa 63 dpa+1 reserved 79 patbit 72 71 lcba0 npa1 np1 np0 rdwrpscb_lpm_compact_pscb_en reserved (5 bits) (26 bits) ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 329 of 539 table 8-44. rdpscb_gdh input operands operand bit length operand source description direct indirect dpa_pscb 6 imm16(5..0) imm12(5..0) the dpa_pscb is a full address of the shared memory pool (see section 7.2.4 shared memory pool on page 172). this indicates work- ing address of the pscb register. full pscb will occupy 2 quadwords from shared memory pool. this address must start at an even address. rdwrpscb_cntl 2 imm16(7..6) imm12(7..6) 00 result is based on patbit value in the shared memory pool as shown in above diagram. patbit = 0 branch 0 entry of the pscb is read patbit = 1 branch 1 entry of the pscb is read 01 branch 0 entry of the pscb is read 10 branch 1 entry of the pscb is read 11 branch 0 and branch 1 entry of the pscb is read reserved 1 imm16(8) imm12(8) reserved. pscb.addr 26 shared memory pool (121..96) address to be read in control store of the pscb. this is stored in shared memory pool. pscb.rdwrps_lpm_ compact_pscb_en 1 shared memory pool (127) this optional argument for lpm reduces memory read bandwidth. when not used, it must be set to ?0?. this option enables use of the lpm compact pscb. it indicates the lpm dt/pscb entry has no valid leaf address and is stored in memory that is 36 bits wi de or less than 64 bits wide (that is, z0 and h1 sram memories). it is not used by fm or smt. 0 for fm pscb/dt and when lpm dt /pscb is stored in 64-bit or wider memory for width = 1 and height = 1 (ddr dram memory). 1 when lpm dt/pscb is stored in memory that is narrower than 64 bits for width = 1 and height = 1 (36-bit z0 and h1 sram memories). when this argument is set to ?1?, pscb.addr+0 and pscb.addr+2 are treated as one pscb pair. pscb.addr+1 and pscb.addr+3 are treated as separate pscb pair. addresses are interleaved for a given pair. when this argument is set to ?1?, the tse reads only the pscb.addr location for 0 branch and the pscb.addr+2 location for 1 branch. it is assumed that pscb.addr+1 and pscb.addr+3 are used as a pscb pair by some other pscb node. pscb.addr.lcba is ignored and addres s will is read in the control store using a 1x1 shape. the contents of the pscb.lcba in the shared memory pool are set to zero. this argument is stored in the shared memory pool. this argument is valid for np2g. note: this command needs the value of the search_type field for pscb shape computation. sinc e the ludeftable entry is not read during this command, it uses the content fr om the local copy of the ludefcopy_gdh r egister. the values in the ludefcopy_gdh register are assumed to be valid prior to this command. this value is stored as a scalar register and is independent for each t hread coprocessor. ibm powernp np2g network processor preliminary tree search engine page 330 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 8.2.7.11 write pscb for fast table update (wrpscb_gdh) wrpscb_gdh writes a pscb stored in pscbx (in shared memory pool) to the control store. for lpm, the entire pscb is written to memory to the address given by pscb.addr. for fm, the pscb is written to memory in fmpscb format. in both cases, wrpscb_gdh generates the pscb?s two format bits. when the pscb represents a dtentry, only half of pscb is written to memory. that is, the entire dtentry is written by picocode. this command is not supported for smt. psc b_cntl/format bits (which defines end node or valid presence of leaf) for the dt/pscb entry will be computed based on the content of pscb.lcba0/1 and no checking/validation is pe rformed, based on the pscb.npa0/1 or pscb.nbt0/1, theref ore pscb.nbt0/1 will be written to memory as is and fo r lpm pscb.npa0/1 is written as is. table 8-45. rdpscb_gdh output results result bit length source description pscb ? register pscb is read from control store and stored in register pscb ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 331 of 539 8.2.7.12 setpatbit_gdh setpatbit_gdh instruction reads a bit from the hashedkey pattern or leaf reference pattern stored in tsrx of the shared memory pool and stores this bit in the setpatbit_gdh register. picocode must copy it to the appropriate patbit field of tsedpa_pscbx of the shared memory pool. pscb.rdwrpscb_lpm _compact_pscb_en 1 shared memory pool (127) this optional argument for lpm r educes memory read bandwidth. when not used, it must be set to ?0?. this option enables use of the lpm compact pscb. it indicates the lpm dt/pscb entry has no valid leaf address and is stored in memory that is 36 bits wide or less than 64 bits wide (that is, z0 and h1 sram memories). it is not used by fm. 0 for fm pscb/dt and when lpm dt/pscb is stored in 64-bit or wider memory for width = 1 and height = 1 (ddr dram memory). 1 when lpm dt/pscb is stored in memory that is narrower than 64 bits for width = 1 and height = 1 (36-bit z0 and h1 sram memories) and no prefix/lcba is present. when this argument is set to ?1?, pscb.addr+0 and pscb.addr+2 are treated as one pscb pair. pscb.addr +1 and pscb.addr+3 are treated as separate pscb pair. addresses are interleaved for a given pair. when this argument is set to ?1?, t he tse reads only the pscb.addr loca- tion for 0 branch and the pscb.addr+2 location for 1 branch. it is assumed that pscb.addr+1 and pscb.addr+3 are used as a pscb pair by some other pscb node. pscb.addr.lcba is ignored and address will is read in the control store using a 1x1 shape. the contents of the pscb.lcba in the shared mem- ory pool are set to zero. this argum ent is stored in the shared memory pool. this argument is valid for np2g. pscb ? shared memory pool the pscb is read from the shared memo ry pool pscb ibm powernp np2g network processor preliminary tree search engine page 332 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 setpatbitgdh_4bit is used by tree management code for multibit nbt lpm search trees and is valid for np2g. table 8-48. setpatbit_gdh input operands operand bit length operand source description direct indirect dpa_pscb 6 imm16(5..0) imm12(5..0) the dpa_pscb is a full address of the thread?s shared address (see 7.2.4 shared memory pool on page 172). this indicates the working address of the pscb register. the d pa_pscbx.index field will be used. tsedpa_hk_leaf 4 imm16(9..6) imm12(9..6) indicates the leaf or hashedkey st orage location in the thread shared memory pool. the tsedpa is the high or der 4 bits of the thread?s shared memory pool address (see 7.2.4 shared memory pool on page 172) and is constrained to be on a f our-qw boundary. use only val ues of x ?8?, x ?a?, x ?c?, and x ?e?. when hk_leaf_flag = 0, hashedkey will be used for this operation. when hk_leaf_flag = 1, leaf content will be used for operation. when leaf is to be used, location for leaf will be tsedpa_hk_leaf; and when hashedkey is used, location for hashedkey will be tsedpa_hk_leaf +2. hk_leaf_flag 1 imm16(10) imm12(10) when hk_leaf_flag = 0, hashedkey will be used for this operation and tsedpa_hk_leaf +2 will be used as a hashedkey location in shared memory pool. when hk_leaf_flag = 1, leaf content will be used for operation and tsedpa_hk_leaf will be used as a leaf location in shared memory pool. hashedkey 192 shared memory pool contains the hashed pattern, and it will be stored at tsedpa_hk_leaf +2 & +3 qw location. structure of hashed key in shared memory pool is shown in the above figure. hashedkeylen 8 shared memory pool contains length of hashed pattern minus 1, and it will be stored at tsedpa_hk_leaf +3 (7..0) qw location. structure of hashed key in shared memory pool is s hown in the above figure. tsrx 512 shared memory pool contains second pattern with pattern length (for lpm only). tsrx is mapped into the shared memory pool, starting at an offset of 4 qw past the qw indicated by the input t sedpa_hk_leaf parameter, for a length of 4 qw. table 8-49. setpatbit_gdh output results result bit length source description setpatbit_gdh 1 register smallest bit position in which the pattern in hashedkey differs from the pattern in the leaf at tsedpa_hk_leaf location. its addr ess in register address map is x?01b?. setpatbit_gdh_4bit 4 register smallest four bit positions where the pattern in hashedkey differs from the pattern in leaf at tsedpa_hk_leaf location. its addres s in register address map is x?01c?. this register is valid for np2g. note: this command needs the value of the p1p2_max_s ize value as a part of its computation. since the ludeftable entry is not read during this command, it uses the contents fr om the local copy of the ludefcopy_gdh re gister. the values in the ludefcopy_gdh re g- ister are assumed to be valid prior to this command. this val ue is stored as a scal ar register and is independent for each thre ad copro- cessor. setpatbit_gdh applies to lpm only. ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 333 of 539 8.2.8 gth hardware assist instructions gth hardware assist instructions can be executed only by the gth thread (1) on tse0. general tse instructions (see table 8-26 on page 316) cannot execute concurrently with gth hardware assist instructions. gth hardware assist instructions are used to perform tree management functions such as insert and delete operations. the general tse instruction set is also able to perform these functions, but they require additional code steps. for applications requiring a high rate of tree insert and delete operations, the use of the general tse instruction set is recommended because multiple threads can be employed. other tree management functions (such as aging, which employs ardl and tlir) or memory management functions (which employs tsenqfl and tsdqfl) can be performed using software-created and managed structures. table 8-50. general gth instructions opcode command detail section 16 hk_gth 8.2.8.1 hash key gth (hk_gth) on page 334 17 rdludef_gth 8.2.8.2 read ludeftable gth (rdludef gth) on page 334 18 tsenqfl 8.2.8.3 tree search enqueue free list (tsenqfl) on page 335 19 tsdqfl 8.2.8.4 tree search dequeue free list (tsdqfl) on page 336 20 rclr 8.2.8.5 read current leaf from rope (rclr) on page 336 21 ardl 8.2.8.6 advance rope with optional delete leaf (ardl) on page 337 22 tlir 8.2.8.7 tree leaf insert rope (tlir) on page 338 23 reserved 24 clrpscb 8.2.8.8 clear pscb (clrpscb) on page 338 25 rdpscb 8.2.8.9 read pscb (rdpscb) on page 339 26 wrpscb 8.2.8.10 write pscb (wrpscb) on page 339 27 pushpscb 8.2.8.11 push pscb (pushpscb) on page 340 28 distpos 8.2.8.12 distinguish (distpos) on page 340 29 tsr0pat 8.2.8.13 tsr0 pattern (tsr0pat) on page 341 30 pat2dta 8.2.8.14 pattern 2dta (pat2dta) on page 342 31 reserved note: the instructions listed in this t able can only be executed by the gth. ibm powernp np2g network processor preliminary tree search engine page 334 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 8.2.8.1 hash key gth (hk_gth) 8.2.8.2 read ludeftab le gth (rdludef gth) rdludef reads the ludeftable at a specified entry and stores the result in the ludefcopy register. the tse can read ludeftable while picocode builds a key because rdludef is executed asynchronously. once the key is ready, the tree search execution can be executed with the useludefcopyreg flag set to ?1?. table 8-51. hash key gth input operands operand bit length operand source description direct indirect ludefindex 8 imm16(12..5) gpr(7..0) defines ent ry in ludeftable containing hash type tsedpa 4 imm16(4..1) imm12(4..1) the tsedpa is the high order 4 bits of the thread?s shared memory pool address (see 7.2.4 shared memory pool on page 172) and is constrained to be on a four-qw boundary. direct_ hashtype_en 1 imm16(0) imm12(0) enable direct hashtype definition 0 hashtype defined by ludefentry 1 hashtype defined via command direct_ hashtype 4 imm16(8..5) gpr(3..0) use defined hash type for hashing. valid when direct_hashtype_en = 1 key 192 shared memory pool provides pattern to be searched. must be initialized before search. located in the shared memory pool. keylen 8 shared memory pool defines length of pattern minus 1 in key. must be initialized before search. located in the shared memory pool. color 16 shared memory pool must be initialized before search - used only when enabled in ludeftable. located in the shared memory pool. invalid when direct_hashtype_en is set to value ?1?. table 8-52. hash key gth output results result bit length source description hashedkeyreg 192 register contains the hashedkey, including color when color is enabled in ludeftable, according to section 8.2.1 input key and color register for fm and lpm trees on page 293 and section 8.2.2 input key and color register for smt trees on page 293. hash function is defined in ludeftable. hashed key is not stored in shared memory pool. hashedkeylen 8 register contains length of pattern minus 1 in hashedkeyreg. hashed key is not stored in shared memory pool. dta 26 register dtentry address (hashed key is not stored in shared memory pool.) ludefcopy 96 register set to contents of ludeftable at entry given by ludefindex. note: valid for gth only. ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 335 of 539 8.2.8.3 tree search enqueue free list (tsenqfl) tsenqfl releases a control block such as a leaf or pscb to a free list. the address of the memory location to be freed is stored in lcba0 / 1. the leaf or pscb index to the free list is provided by the ludeftable or directly by the command line. the enqueue operation always adds an address to the bottom of a free list fifo-style. entries cannot be added or removed from the middle of a free list. when freelistctrl = 11, tsenqfl increments the leafcount field in ludeftable. table 8-53. rdludef_gth input operands operand bit length operand source description direct indirect ludefindex 8 imm16(12..5) gpr(7..0) defines entry in ludeftable table 8-54. rdludef_gt h output results result bit length source description ludefcopy 96 register scalar register contains cont ent of ludeftable at the entry. no content will be written back to shared memory pool. ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation table 8-55. tsenqfl input operands operand bit length operand source description direct indirect freelistctrl 2 imm16(14..13) gpr(9..8) 00 direct free list index 10 pscb free list index from ludeftable 11 leaf free list index from ludeftable ludefindex/ freelistindex 8 imm16(12..5) gpr(7..0) defines the entry in the ludeftable used to read free list index infor- mation or directly defines freelistindex. srctype 3 imm16(2..0) imm12(2..0) 000 lcba0 001 lcba1 100 pscb0.addr (for gth only) 101 pscb1.addr (for gth only) 110 pscb2.addr (for gth only) lcba0 / 1 pscb0 / 1 / 2.addr 26 register the address to be freed or enqueued table 8-56. tsenqfl output results result bit length source description ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation ibm powernp np2g network processor preliminary tree search engine page 336 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 8.2.8.4 tree search dequeue free list (tsdqfl) tsdqfl dequeues an address from a given fqlinklist. the address that has been dequeued from the free list is stored in lcba0 / 1. the leaf or pscb index to th e free list is provided by the ludeftable or directly by the command line. when freelistctrl is ?11?, tsdqfl decrements the leafcount field in ludeftable. 8.2.8.5 read current leaf from rope (rclr) rclr is used to ?walk the rope? for such processes as aging. rclr reads the leaf at the current leaf address defined in ludeftable. it stores the leaf address in lcba0 and the leaf contents in tsr0. when rope walking begins, the tse invokes rclr and picocode saves the leaf address (lcba0) in a gpr. before reading the next leaf, the tse invokes the advance rope with optional delete leaf command (ardl), after which rclr can be invoked again. to determine whether a rope walk has ended, picocode compares lcba0 with the gpr to verify whether the leaf that was read is the same as the first leaf. if the leaf is the same, the rope walk has ended. at any time during the rope walk, picocode can delete a leaf from the rope using ardl with the deleteleaf flag set to 1. this is useful when the leaf is to be aged out. rclr can automati cally delete leaves from the rope when the deletepending bit in the leaf is set. when this feature is enabled, the tse deletes a leaf and reads the next leaf, which is also deleted when the deletepending bit is set. the process is repeated to delete multiple leaves. after rclr has executed with ok = 1, the contents of tsr0 and lcba0 correspond with cla in the ludeftable, and the previous leaf on the rope has an address of pla. ok = 0, or ko, means the rope is empty. table 8-57. tsdqfl input operands operand bit length operand source description direct indirect freelistctrl 2 imm16(14..13) gpr(9..8) 00 direct free list index 10 pscb free list index from ludeftable 11 leaf free list index from ludeftable ludefindex/ freelistindex 8 imm16(12..5) gpr(7..0) defines the entry in ludeftable us ed to read free list index informa- tion or directly def ines freelistindex. tgttype 3 imm16(2..0) imm12(2..0) 000 lcba0 001 lcba1 100 pscb0.addr (for gfh only) 101 pscb1.addr (for gfh only) 110 pscb2.addr (for gfh only) table 8-58. tsdqfl output results result bit length source description lcbao/1 pscb0 / 1 / 2.addr 26 register dequeued address ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 337 of 539 8.2.8.6 advance rope with optional delete leaf (ardl) ardl advances the rope, or updates cla and pla in ludeftable. the nla field from the leaf already stored in tsr0 is read and stored in cla. pla is then updated to the previous value of cla unless the leaf is deleted. in this case, pla remains the same and the nlarope field for the leaf with the current pla address is set to the new cla. when leaf deletion is enabled, the current leaf is deleted prior to advancing the rope. the contents of tsr0 and lcba0 can be destroyed be cause ardl uses tsr0 and lcba0 as work areas to update the nlarope field. after ardl is executed, cla and pla (in the ludeftable) are updated and rclr (described in the next section) can be executed again. table 8-59. rclr input operands operand bit length operand source description direct indirect ludefindex 8 imm16(12..5) gpr(7..0) defines entry in ludeftable used to read rope reserved 3 imm16(3..1) imm12(3..1) must be set to ?000? delenable 1 imm16(0) imm12(0) when ?1?, leaves with deletepending bit are automatically deleted from rope and leaf address will be enqueued in leaf free queue tsedpa 4 imm16(4..1) imm12(4..1) location for the leaf to be stored. the tsedpa is the high order 4 bits of the thread?s shared memory pool address (see 7.2.4 shared mem- ory pool on page 172) and is constr ained to be on a four-qw boundary. table 8-60. rclr output results result bit length source description ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation lcba0 26 register address of leaf that has been read tsrx 512 shared memory pool leaf content is stored in tsrx. tsrx is mapped into the shared memory pool, starting at an offset of 4 qw past the qw indicated by the input tsedpa parameter for a length of 4 qw. table 8-61. ardl input operands operand bit length operand source description direct indirect ludefindex 8 imm16(12..5) gpr(7..0) defines entry in ludeftable deleteleaf 1 imm16(0) imm12(0) enable deletion of current leaf from rope. 0 do not delete leaf. 1 delete leaf tsedpa 4 imm16(4..1) imm12(4..1) location of the current leaf addres s. the tsedpa is the high order 4 bits of the thread?s shar ed memory pool address (see 7.2.4 shared memory pool on page 172) and is constr ained to be on a four-qw boundary. tsrx 26 register contents of current leaf (address cla in ludeftable). tsrx is mapped into the shared memory pool, starting at an offset of 4 qw past the qw indicated by the input tsedpa parameter for a length of 4 qw. ibm powernp np2g network processor preliminary tree search engine page 338 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 8.2.8.7 tree leaf insert rope (tlir) tlir inserts a leaf into the rope. the leaf must already be stored in tsr0 (done automatically by picocode during tlir) and the leaf address must already be available in lcba0. tlir maintains the rope, which involves updating the pva field in lude ftable, the nlarope leaf field in control stor e, and the nlarope leaf field stored in tsrx. the leaf is inserted into the rope ahead of the current leaf, which has address cla. field pla is updated to the new leaf address, which is lcba0 / 1, in ludeftable. following tlir execution, pico- code must invoke mwr to write the leaf into control store. the contents of tsr1 and lcba1 can be destroyed because tlir uses tsr1 and lcba1 as a work area. 8.2.8.8 clear pscb (clrpscb) this command writes all zeros to pscb0 / 1 / 2. table 8-62. ardl output results result bit length source description tsrx 512 shared memory pool contents of tsrx will not be destroyed lcba0 26 register contents of lcba0 have been destroyed ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation table 8-63. tlir input operands operand bit length operand source description direct indirect ludefindex 8 imm16(12..5) gpr(7..0) defines entry in ludeftable lcba0 26 register address of leaf to be inserted into rope tsedpa 4 imm16(4..1) imm12(4..1) the tsedpa is the high order 4 bits of the thread?s shared memory pool address (see 7.2.4 shared memory pool on page 172) and is constrained to be on a four-qw boundary. only va lues of x?8?, x?a?, x?c?, and x?e? should be used. tsrx 26 shared memory pool contents of leaf to be inserted into rope. tsrx is mapped into the shared memory pool, starting at an offset of 4 qw past the qw indicated by the input tsedpa parameter for a length of 4 qw. table 8-64. tlir output results result bit length source description tsrx 512 shared memory pool leaf nla field has been updated ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation table 8-65. clrpscb input operands operand bit length operand source description direct indirect pn 2 imm16(1..0) -- selects pscb0, pscb1, or pscb2 register ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 339 of 539 8.2.8.9 read pscb (rdpscb) rdpscb reads a pscb from the control store and stores it in one of the pscb0 / 1 / 2 registers. for lpm, the entire pscb is read from memory at the address given by pscb ibm powernp np2g network processor preliminary tree search engine page 340 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 8.2.8.11 push pscb (pushpscb) pushpscb pushes the pscb stack. 8.2.8.12 distinguish (distpos) distpos performs a pattern compare between the patterns stored in hashedkey and tsr0. the result is stored in the distposreg register. the ok flag is set when a full match has been detected. table 8-69. wrpscb input operands operand bit length operand source description direct indirect pn 2 imm16(1..0) imm12(1..0) selects pscb0, pscb1, or pscb2 register pscb ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 341 of 539 8.2.8.13 tsr0 pattern (tsr0pat) tsr0pat reads a bit from the pattern stored in tsrx and stores this bit in the patbit_tsr0 register. table 8-72. distpos input operands operand bit length operand source description direct indirect hashedkey 192 register contains hashed pattern hashedkeylen 8 register contains length of hashed pattern minus 1 tsedpa 4 imm16(4..1) imm12(4..1) the tsedpa is the high order 4 bits of the thread?s shared memory pool address (see 7.2.4 shared memory pool on page 172) and is constrained to be on a four-qw boundar y. use only values of x?8?, x?a?, x?c?, and x?e?. tsrx 512 shared memory pool contains second pattern with pa ttern length (for lpm only). tsrx is mapped into the shared memory pool, starting at an offset of 4 qw past the qw indicated by the input tsedpa parameter for a length of 4 qw. table 8-73. distpos output results result bit length source description ok/ko 1 flag 0 pattern does not match 1 pattern in hashedkey matches pattern in tsrx distpos 8 register smallest bit position where patte rn in hashedkey differs from pattern in tsrx ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation table 8-74. tsr0pat input operands operand bit length operand source description direct indirect bitnum 8 -- gpr(7..0) selects bit in tsr0 pattern tsedpa 4 imm16(4..1) imm12(4..1) the tsedpa is the high order 4 bits of the thread?s shared memory pool address (see 7.2.4 shared memory pool on page 172) and is constrained to be on a four-qw boundar y. use only values of x?8?, x?a?, x?c?, and x?e?. table 8-75. tsr0pat output results result bit length source description patbit_tsr0 1 register set to value of bit bitnum of pattern stored in tsr0 ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation ibm powernp np2g network processor preliminary tree search engine page 342 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 8.2.8.14 pattern 2dta (pat2dta) pat2dta reads a pattern from tsrx, stores it in the hashedkey, and sets the dta register accordingly. pat2dta does not perform a hash since the pattern in a leaf is already hashed. pattern read from tsrx is assumed to be already hashed. 8.2.9 hash functions in the following figures, the input is always the 192-bi t key and the output is a 192-bit hashed output before color insertion. the hash_type field of the ludeftable defines the hasher to be used. if color is enabled, the color is inserted at the bit position given by dt_size in the ludeftable and 16 least significant bits of the key are ignored, since a maximum key length of 176 bits is supported when color is enabled. table 8-76. pat2dta input operands operand bit length operand source description direct indirect ludefindex 8 imm16(12..5) gpr(7..0) defines entry in ludeftable used to calculate dta from hashedkey tsedpa 4 imm16(4..1) imm12(4..1) the tsedpa is the high order 4 bits of the thread?s shared memory pool address (see 7.2.4 shared memory pool on page 172) and is constrained to be on a four-qw boundar y. use only values of x?8?, x?a?, x?c?, and x?e?. table 8-77. pat2dta output results result bit length source description dta 26 register dtentry address corresponding to dt definition in ludeftable and hashedkey ok/ko 1 flag 0 ko: unsuccessful operation 1 ok: successful operation table 8-78. general hash functions hash_type name description 0 no hash no hash is performed and hashed output h(191..0) equals input key k(191..0). can be used for smt trees or lpm trees if 32-bit ip lpm hash cannot be used. 1 192-bit ip hash uses four copies of ip hash box. see figure 8-14: 192-bit ip hash function on page 343. 2 192-bit mac hash see figure 8-15: mac hash function on page 344. 3 192-bit network distpatch see figure 8-16: network dispatcher hash function on page 345. 4reserved 5 48-bit mac swap see figure 8-17: 48-bit mac hash function on page 346. 6 60-bit mac swap see figure 8-18: 60-bit mac hash function on page 347. 7reserved 8 8-bit hasher see figure 8-19: 8-bit hash function on page 348. 9 12-bit hasher see figure 8-20: 12-bit hash function on page 348. 10 16-bit hasher see figure 8-21: 16 bit hash function on page 349. 11-15 reserved reserved. ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 343 of 539 figure 8-13. no-hash function figure 8-14. 192-bit ip hash function b0 a0 k0 (bits 191..160) d0 c0 b4 a4 k4 (bits 63..32) d4 c4 b5 a5 k5 (bits 31..0) d5 c5 b1 a1 k1 (bits 159..128) d1 c1 b2 a2 k2 (bits 127..96) d2 c2 b3 a3 k3 (bits 95..64) d3 c3 a0 h0 (bits 191..160) d0 c0 b4 a4 h4 (bits 63..32) d4 c4 b5 a5 h5 (bits 31..0) d5 c5 b1 a1 h1 (bits 159..128) d1 c1 b2 a2 h2 (bits 127..96) d2 c2 b3 a3 h3 (bits 95..64) d3 c3 b0 b0 a0 k0 (bits 191..160) d0 c0 b4 a4 k4 (bits 63..32) d4 c4 b5 a5 k5 (bits 31..0) d5 c5 b1 a1 k1 (bits 159..128) d1 c1 b2 a2 k2 (bits 127..96) d2 c2 b3 a3 k3 (bits 95..64) d3 c3 ip hash box ip hash box ip hash box ip hash box ip hash box ip hash box a0 h0 (bits 191..160) d0 c0 b4 a4 h4 (bits 63..32) d4 c4 b5 a5 h5 (bits 31..0) d5 c5 b1 a1 h1 (bits 159..128) d1 c1 b2 a2 h2 (bits 127..96) d2 c2 b3 a3 h3 (bits 95..64) d3 c3 b0 ibm powernp np2g network processor preliminary tree search engine page 344 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 figure 8-15. mac hash function b0 a0 k0 (bits 191..160) d0 c0 b4 a4 k4 (bits 63..32) d4 c4 b5 a5 k5 (bits 31..0) d5 c5 b1 a1 k1 (bits 159..128) d1 c1 b2 a2 k2 (bits 127..96) d2 c2 b3 a3 k3 (bits 95..64) d3 c3 ip hash box ip hash box ip hash box ip hash box ip hash box ip hash box a0 h0 (bits 191..160) d0 c0 b4 a4 h4 (bits 63..32) d4 c4 b5 a5 h5 (bits 31..0) d5 c5 b1 a1 h1 (bits 159..128) d1 c1 b2 a2 h2 (bits 127..96) d2 c2 b3 a3 h3 (bits 95..64) d3 c3 b0 ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 345 of 539 figure 8-16. network dispatcher hash function b0 a0 k0 (bits 191..160) d0 c0 b4 a4 k4 (bits 63..32) d4 c4 b5 a5 k5 (bits 31..0) d5 c5 b1 a1 k1 (bits 159..128) d1 c1 b2 a2 k2 (bits 127..96) d2 c2 b3 a3 k3 (bits 95..64) d3 c3 ip hash box ip hash box ip hash box ip hash box ip hash box ip hash box a0 h0 (bits 191..160) d0 c0 b4 a4 h4 (bits 63..32) d4 c4 b5 a5 h5 (bits 31..0) d5 c5 b1 a1 h1 (bits 159..128) d1 c1 b2 a2 h2 (bits 127..96) d2 c2 b3 a3 h3 (bits 95..64) d3 c3 b0 32-bit bitwise swap o(i) i(31-i) ibm powernp np2g network processor preliminary tree search engine page 346 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 figure 8-17. 48-bit mac hash function b0 a0 k0 (bits 191..160) d0 c0 b4 a4 k4 (bits 63..32) d4 c4 b5 a5 k5 (bits 31..0) d5 c5 b1 a1 k1 (bits 159..128) d1 c1 b2 a2 k2 (bits 127..96) d2 c2 b3 a3 k3 (bits 95..64) d3 c3 ip hash box ip hash box ip hash box ip hash box ip hash box ip hash box a0 h0 (bits 191..160) d0 c0 b4 a4 h4 (bits 63..32) d4 c4 b5 a5 h5 (bits 31..0) d5 c5 b1 a1 h1 (bits 159..128) d1 c1 b2 a2 h2 (bits 127..96) d2 c2 b3 a3 h3 (bits 95..64) d3 c3 b0 48-bit bitwise swap o(i) i(47-i) ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 347 of 539 figure 8-18. 60-bit mac hash function b0 a0 k0 (bits 191..160) d0 c0 b4 a4 k4 (bits 63..32) d4 c4 b5 a5 k5 (bits 31..0) d5 c5 b1 a1 k1 (bits 159..128) d1 c1 b2 a2 k2 (bits 127..96) d2 c2 b3 a3 k3 (bits 95..64) d3 c3 ip hash box ip hash box ip hash box ip hash box ip hash box ip hash box a0 h0 (bits 191..160) d0 c0 b4 a4 h4 (bits 63..32) d4 c4 b5 a5 h5 (bits 31..0) d5 c5 b1 a1 h1 (bits 159..128) d1 c1 b2 a2 h2 (bits 127..96) d2 c2 b3 a3 h3 (bits 95..64) d3 c3 b0 60-bit bitwise swap o(i) i(59-i) 84 4 ibm powernp np2g network processor preliminary tree search engine page 348 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 figure 8-19. 8-bit hash function figure 8-20. 12-bit hash function b0 a0 k0 (bits 191..160) d0 c0 b4 a4 k4 (bits 63..32) d4 c4 b5 a5 k5 (bits 31..0) d5 c5 b1 a1 k1 (bits 159..128) d1 c1 b2 a2 k2 (bits 127..96) d2 c2 b3 a3 k3 (bits 95..64) d3 c3 a0 h0 (bits 191..160) d0 c0 b4 a4 h4 (bits 63..32) d4 c4 b5 a5 h5 (bits 31..0) d5 c5 b1 a1 h1 (bits 159..128) d1 c1 b2 a2 h2 (bits 127..96) d2 c2 b3 a3 h3 (bits 95..64) d3 c3 b0 ibm np 8 8 8 ip 192 bit hasher note: effective hashed key will be longer by 8 bits and maxi mum key length allowed is 184 bits with no color. b0 a0 k0 (bits 191..160) d0 c0 b4 a4 k4 (bits 63..32) d4 c4 b5 a5 k5 (bits 31..0) d5 c5 b1 a1 k1 (bits 159..128) d1 c1 b2 a2 k2 (bits 127..96) d2 c2 b3 a3 k3 (bits 95..64) d3 c3 a0 h0 (bits 191..160) d0 c0 b4 a4 h4 (bits 63..32) d4 c4 b5 a5 h5 (bits 31..0) d5 c5 b1 a1 h1 (bits 159..128) d1 c1 b2 a2 h2 (bits 127..96) d2 c2 b3 a3 h3 (bits 95..64) d3 c3 b0 ibm np 12 12 12 ip 192 bit hasher d5 = 00000000 c5 = xxxx0000 note: effective hashed key will be longer by 12 bits and maxi mum key length allowed is 180 bits with no color. ibm powernp np2g preliminary network processor np2_ds_sec08_tree.fm.01 february 12, 2003 tree search engine page 349 of 539 figure 8-21. 16 bit hash function b0 a0 k0 (bits 191..160) d0 c0 b4 a4 k4 (bits 63..32) d4 c4 b5 a5 k5 (bits 31..0) d5 c5 b1 a1 k1 (bits 159..128) d1 c1 b2 a2 k2 (bits 127..96) d2 c2 b3 a3 k3 (bits 95..64) d3 c3 a0 h0 (bits 191..160) d0 c0 b4 a4 h4 (bits 63..32) d4 c4 b5 a5 h5 (bits 31..0) d5 c5 b1 a1 h1 (bits 159..128) d1 c1 b2 a2 h2 (bits 127..96) d2 c2 b3 a3 h3 (bits 95..64) d3 c3 b0 ibm np ip 192 bit hasher d5 = 00000000 c5 = 00000000 b0 a0 d0 c0 b4 a4 d4 c4 b5 a5 b1 a1 d1 c1 b2 a2 d2 c2 b3 a3 d3 c3 note: effective hashed key will be longer by 16 bits and maximum key length al lowed is 176 bits with no color. 8 8 ibm powernp np2g network processor preliminary tree search engine page 350 of 539 np2_ds_sec08_tree.fm.01 february 12, 2003 ibm powernp np2g preliminary network processor np2_ds_sec09_spm.fm.01 february 12, 2003 serial / parallel manager interface page 351 of 539 9. serial / parallel manager interface located within the embedded processor complex (epc), the serial / parallel manager (spm) interface is a serial interface for communication with external devices. the spm interface consists of a clock signal output, a bi-directional data signal, and an interrupt input. on th is interface, the np2g is the master and the external spm module is the only slave 1 . the spm interface loads picocode, allowing management of physical layer devices (phys) and access to ca rd-based functions such as light-emitting diodes (leds). the spm interface supports: an external spm module boot code load via external spm and eeprom boot override via cabwatch interface or boot_picocode configuration device i/o access to external phys, leds, management, and card-based functions 9.1 spm interface components figure 9-1 shows the functional blocks of the spm interf ace. the list following the figure describes them. 1.ibm does not supply the external spm module. figure 9-1. spm interface block diagram boot state machine starts up after reset if configured to do so by an external i/o pin (boot_picocode set to 0). it selects one of two boot images (picocode loads) based on a configuration flag found in the eeprom and places the code into the instruction memory in the epc. once the code is loaded, the boot state machine causes an interrupt that starts up the guided frame handler (gfh ) thread, which executes the loaded code. cab interface a memory mapped interface to the np 2g that allows the protocol processors to access any external device, including an spm module, external phys, or card leds. parallel to serial control converts between the internal 32-bit read/write parallel interface and the 3-bit external bi-directional serial interface. instruction memory cab boot state machine cab interface parallel to serial control external spm module ibm powernp np2g network processor preliminary serial / parallel manager interface page 352 of 539 np2_ds_sec09_spm.fm.01 february 12, 2003 9.2 spm interface data flow the spm interface is used initially to boot the np2g. following a reset, the spm interface reads an external eeprom and loads the eeprom?s conten ts into the epc?s instruction memory. when loading is complete, the spm interface causes a por interrupt that causes the guided frame handler (gfh) to start executing the boot code. the boot code initializes the network pr ocessor?s internal structures and configures all the interfaces that the network processor requires to oper ate. when all boot processing is complete, the gfh activates the operational signal to indicate its ava ilability to the control point fu nction (cpf). the cpf sends guided frames to further initialize and configure the network processor, preparing it for network operation. the boot state machine suppor ts two images of boot code in external eeprom (see figure 9-2 ). the contents of byte x'0 0000' in eeprom is examined du ring the read process to determine which image to load. when the most significant bit of this byte is a ?0?, the current image resides at addresses x?0 0001? - x?0 4000?. otherwise, the current image resides at add resses x?1 0001? - x?1 4000?. the boot state machine will load the appropriate im age and allow the other image area to be used for boot code updates. ibm powernp np2g preliminary network processor np2_ds_sec09_spm.fm.01 february 12, 2003 serial / parallel manager interface page 353 of 539 the spm interface is also used during initialization and statistics gathering. it interfaces with the ethernet phys, card leds, and other card-level structures through an external spm interface module supplied by the customer. these external structures are mapped to the control access bus (cab) address space and are accessed from the picocode using the same methods as those used to access any internal data structures: the picocode issues reads or writes to the appropri ate address and the spm interface converts these reads and writes to serial communications with the external spm module. the external spm module re-converts these serial communications to register reads and writes and to access the desired card device. through the spm interface, the picocode has indirect access to all card-level functions and can configure or gather statis- tics from these devices as if they were directly attached to the cab interface. figure 9-2. epc boot image in external eeprom boot flag reserved x?0 0000? x?0 0001? x?0 4000? boot code & post & boot gfh 70 x?0 4001? 16 k 8 k x?0 6000? x?0 6001? post overflow & extended post 16 k x?0 a000? x?0 a001? other 24 k not used reserved x?1 0000? x?1 0001? x?1 4000? boot code & post & boot gfh x?1 4001? 16 k 8 k x?1 6000? x?1 6001? post overflow & extended post 16 k x?1 a000? x?1 a001? other 24 k x?0 ffff? x?1 ffff? image b image a ibm powernp np2g network processor preliminary serial / parallel manager interface page 354 of 539 np2_ds_sec09_spm.fm.01 february 12, 2003 9.3 spm interface protocol the spm interface operates synchronously with the 33 mhz clock signal output. data, address, and control information is transferred serially on a bidirectional dat a signal. transitions on this data signal occur at the rising edges of the clock signal. each data exchange is initiated by the np2g and can be one to four bytes in length. figure 9-3 illustrates the timing of the spm interface. for single-byte transfers, the exchange begins when th e np2g drives the data signal to ?1? for one clock period. this ?select? indication is followed by a 1-bit write/read indication, a 4-bit burst length indication, and a 25-bit address value. for read and write transfers, the spm interface master waits for a response from the spm interface slave, and the slave communicates with the master using the following acknowledgments: ack: a ?1? driven onto the data bus by the spm interface slave to indicate each successful byte operation, either read or write. ack : a ?0? driven onto the data bus by the spm interface slave while the byte operation is in progress. for write transfers (see figure 9-4 ), the address is followed immediately by eight bits of data. the np2g puts its driver in high-z mode. one clock period later, the slave drives the data signal to ?0? (ack ) until the byte write operation is complete. the slave then drives the data signal to ?1? (ack). during the byte write operation, the np2g samples the data input looking for a ?1? (ack). immediately following the ack, the slave puts its driver in high-z mode. the transfer is concluded one clock period later. figure 9-3. spm bit timing figure 9-4. spm interface write protocol t .25t clock ... data .25t .25t ... sel write ... ... idle sel write ... ... idle r/w ... one byte write two byte write (burst length = 0010) ... r/w ... ... ... zero or more ack s preceding one ack new sequence can begin here bl3 bl0 a24 a0 d7 d0 ts ack ts sel bl3 bl0 a24 a0 d7 ts ts ts ts d0 ack start d7 ack d0 sel note: bl# = bit # of the burst length a# = bit # of the address ack = acknowledgment sel = select ibm powernp np2g preliminary network processor np2_ds_sec09_spm.fm.01 february 12, 2003 serial / parallel manager interface page 355 of 539 for read transfers (see figure 9-5 ), the address is followed by the np2g putting its driver into high-z mode. one clock period later, the slave drives the data signal to ?0? (ack ) until the byte of read data is ready for transfer. the slave then drives the data signal to ?1? (ack ). during this time, the np2g samples the data input looking for an ack. immediately following the ack, the slav e drives the eight bits of data onto the data signal and then puts its driver in high-z mode. the transfer is concluded one clock period later. the protocol for multiple byte transfers is similar, except that each byte written is accompanied by a bus turn- around, zero or more ack s, and an ack. read bursts are characterized by the slave retaining bus ownership until the last byte of the burst is transferred. each successive byte read is preceded by at least one ?0? on the data bus followed by one ?1? on the data bus (ack), and immediately followed by the eight bits of data. figure 9-5. spm interface read protocol read sel ... ... idle ... r/w read sel ... ... idle ... ... ... r/w ... one byte read two byte read (burst length = 0010) one or more acks preceding one ack zero or more acks preceding one ack new sequence can begin here bl3 bl0 a24 a0 ts ack d7 d0 ts sel bl3 bl0 a24 a0 ack ts d7 d0 ack d0 ts sel note: bl# = bit # of the burst length a# = bit # of the address ack = acknowledgment sel = select d7 ibm powernp np2g network processor preliminary serial / parallel manager interface page 356 of 539 np2_ds_sec09_spm.fm.01 february 12, 2003 9.4 spm cab address space the spm interface enables the contro l access bus (cab) to access an external eeprom an d other devices attached via an external spm module developed by the customer. the address space is divided into three areas: byte access word access eeprom access 9.4.1 byte access space all elements accessed in byte access spac e are limited to a single byte in width. 9.4.2 word access space all elements accessed in word ac cess space are a word in width. access type r/w base addresses x?2800 0000? through x?281f ffff? x?2880 0000? through x?28ff ffff? byte data reserved 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description byte data 31:24 data at this location reserved 23:0 reserved access type: r/w base addresses: x?2820 0000? through x?287f ffff? word data 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description word data 31:0 data at this location ibm powernp np2g preliminary network processor np2_ds_sec09_spm.fm.01 february 12, 2003 serial / parallel manager interface page 357 of 539 9.4.3 eeprom access space the spm interface and a customer-supplied external spm module can be combined to provide access to an attached eeprom. the eeprom access space contains locations fo r 16 m 1-byte elements. all write accesses are limited to a single byte, but read accesses may be in bursts of 1, 2, 3, or 4 bytes. the cab address is formed using the field definitions shown in table 9-1 . 9.4.3.1 eeprom single-byte access addresses in this space are used for single-byte read or write access to the eeprom. table 9-1. field definitions for cab addresses bits description 31:27 ?00101? 26:25 encoded burst length 00 4-byte burst (read only) 01 1-byte burst (read or write) 10 2-byte burst (read only) 11 3-byte burst (read only) 24 ?1? 23:0 starting byte address for read or write action access type: r/w base addresses: x?2b00 0000? through x?2bff ffff? byte data reserved 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description byte data 31:24 data at starting byte address reserved 23:0 reserved ibm powernp np2g network processor preliminary serial / parallel manager interface page 358 of 539 np2_ds_sec09_spm.fm.01 february 12, 2003 9.4.3.2 eeprom 2- byte access addresses in this space ar e used for a 2-byte read burst access to the eeprom. 9.4.3.3 eeprom 3- byte access addresses in this space ar e used for a 3-byte read burst access to the eeprom. access type: read only base addresses: x?2d00 0000? through x?2dff ffff? byte 0 data byte 1 data reserved 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description byte 0 data 31:24 data at starting byte address byte 1 data 23:16 data at starting byte address + 1 reserved 15:0 reserved access type: read only base addresses: x?2f00 0000? through x?2fff ffff? byte 0 data byte 1 data byte 2 data reserved 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description byte 0 data 31:24 data at byte address byte 1 data 23:16 data at byte address + 1 byte 2 data 15:8 data byte address + 2 reserved 7:0 reserved ibm powernp np2g preliminary network processor np2_ds_sec09_spm.fm.01 february 12, 2003 serial / parallel manager interface page 359 of 539 9.4.3.4 eeprom 4- byte access addresses in this space ar e used for a 4-byte read burst access to the eeprom. access type: read only base addresses: x?2900 0000? through x?29ff ffff? byte 0 data byte 1 data byte 2 data byte 3 data 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description byte 0 data 31:24 data at byte address byte 1 data 23:16 data at byte address + 1 byte 2 data 15:8 data byte address + 2 byte 3 data 7:0 data byte address + 3 ibm powernp np2g network processor preliminary serial / parallel manager interface page 360 of 539 np2_ds_sec09_spm.fm.01 february 12, 2003 ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 361 of 539 10. embedded powerpc? subsystem 10.1 description the np2g incorporates an embedded powerpc subsystem. this subsystem consists of mixture of macros from ibm?s powerpc macro library and other components that were designed specifically for the np2g. standard ibm powerpc macros include the following: 133 mhz ppc405 processor core with 16 k of instruction cache and 16 k of data cache - np2g uses the ppc405d4v6 core 133 mhz, 64-bit plb macro with plb arbiter 33/66 mhz, 32-bit pci to 133 mhz, 64-bit plb macro powerpc universal interr upt controller (uic) macro documentation for the above macros is contained in the ibm powerpc 405gp embedded processor user?s manual ( http://www-3.ibm.com/chip s/techlib/techlib.nsf/products/p owerpc_405gp_embedded_processor ) and is not repeated here. that document also contains information for other macro library components not contained in the np2g which does not apply to the above macros. the embedded powerpc subsystem includes a cab interface plb slave unit to access np2g internal struc- tures and a mailbox and dram interface plb slave unit for inter-processor communications and access to powerpc instructions. figure 10-1. powerpc subsystem block diagram powerpc 64-bit plb arbiter pci/plb mailbox & epc gph reset cntl to dram to pci bus cab 405 core interface dram i/f macro dram controller dram arbiter cab arbiter cab interrupts universal interrupt controller ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 362 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 10.2 processor local bus and device control register buses the on-chip bus structure consisting of the processor local bus (plb) and the device control register bus (dcr) provides a link between the processor core and th e other peripherals (plb master and slave devices) used in powerpc subsystem design. 10.2.1 processor local bus (plb) the plb is the high performance bus used to access me mory, pci devices, and np2g structures through the plb interface units. the plb interface units shown in figure 10-1 , the cab interface and the mailbox & dram interface, are plb slaves. the processor core has two plb master connections, one for instruction cache and one for data cache. the pci to plb interface unit, which is both a plb master and plb slave device, is also attached to the plb. the plb master corresponds to the pci target and the plb slave corre- sponds to the pci master. each plb master is attached to the plb through separate address, read data, and write data buses and a plurality of transfer qualifier signals. plb slaves ar e attached to the plb through shared, but decoupled, address, read data, and write data buses and a plurality of transfer control and status signals for each data bus. access to the plb is granted through a central arbitration mechanism that allows masters to compete for bus ownership. this mechanism is flexible enough to provid e for the implementation of various priority schemes. additionally, an arbitration locking mechanism is provided to support master-driven atomic operations. the plb is a fully-synchronous bus. timing for all plb si gnals is provided by a sing le clock source that is shared by all masters and slaves attached to the plb. table 10-1. plb master connections master id master unit description 0 processor core instruction cache unit 1 processor core data cache unit 2 plb/pci macro unit others unused ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 363 of 539 10.2.2 device control register (dcr) bus the device control register (dcr) bus is used primarily to access stat us and control registers within the plb and the universal interrupt controller (uic). the dcr bus architecture allows data transfers among peripherals to occur independently from, and concurrent with, data transfers between the processor and memory or among other plb devices. all plb arbiter registers and universal interrupt contro ller registers are device control registers. they are accessed by using the move from device control regi ster (mfdcr) and move to device control register (mtdcr) instructions. plb arbiter registers are architected as 32-bits and are privileged for both read and write. the dcr base address of the plb registers is x'080'. the dcr base address of the uic registers is x'0c0'. details regarding the plb and uic device control registers can be found in the ibm powerpc 405gp embedded processor user?s manual ( http://www-3.ibm.com/chips/techlib/techlib.nsf/products/ powerpc_405gp_embedded_processor ). table 10-2. device control registers register dcr offset description access processor local bus arbiter macro rev x?02? plb arbiter revision id r besr x?04? plb bus error status register r/clear bear x?06? plb bus error address register r acr x?07? plb arbiter control register r/w universal interrupt controller macro sr x?00? uic status register r/clear srs x?01? uic status register set r/set er x?02? uic enable register r/w cr x?03? uic critical register r/w pr x?04? uic polarity register r/w tr x?05? uic triggering register r/w msr x?06? uic masked status register r vr x?07? uic vector register r vcr x?08? uic vector configuration register w ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 364 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 10.3 plb address map components of the embedded powerpc subsystem are connected using the processor local bus (plb). these components recognize plb address values as their own. these plb address values are fixed by hardware. the plb address map describes the association of plb address values and the components that recognize them. table 10-3. address map for cab interface macro symbolic address plb address description access pwrpc_cab_addr x?7800 0000? powerpc cab address register r/w pwrpc_cab_data x?7800 0008? powerpc cab data register r/w pwrpc_cab_cntl x?7800 0010? powerpc cab control register r/w 1 pwrpc_cab_status x?7800 0018? powerpc cab status register r pwrpc_cab_mask x?7800 0020? powerpc cab mask register r/w pwrpc_cab_wum_data x?7800 0028? powerpc cab write under mask data register w host_cab_addr x?7800 8000? pci host cab address register r/w host_cab_data x?7800 8008? pci host cab data register r/w host_cab_cntl x?7800 8010? pci host cab control register r/w 1 host_cab_status x?7800 8018? pci host cab status register r host_cab_mask x?7800 8020? pci host cab mask register r/w host_cab_wum_data x?7800 8028? pci host cab write under mask data register w unassigned addresses in the range x?7801 0000? - x?7801 ffff? are reserved. 1. additional action occurs on register access using the specif ied address. refer to register detailed section for more information. table 10-4. plb address map for mailbox and dram interface macro (page 1 of 2) symbolic address plb address description access pci_interr_status x?7801 0000? pci interrupt status register r pci_interr_ena x?7801 0008? pci interrupt enable register r/w p2h_msg_resource x?7801 0010? powerpc subsystem to pci host resource register r/w 1 p2h_msg_addr x?7801 0018? powerpc subsystem to pci host message address register r/w 1 p2h_doorbell x?7801 0020? powerpc subsystem to pci host doorbell register (powerpc access) r/sum x?7801 0028? powerpc subsystem to pci host d oorbell register (pci host access) r/rum h2p_msg_addr x?7801 0050? pci host to powerpc subsystem message address register (reset status) r 1 x?7801 0060? pci host to powerpc subsystem message address register r/w 1 h2p_doorbell x?7801 0030? pci host to powerpc subsystem d oorbell register (pci host access) r/sum x?7801 0038? pci host to powerpc doorbell register (powerpc access) r/rum e2p_msg_resource x?7801 0040? epc to powerpc subsystem message resource register r/w unassigned addresses in the range x?7801 0000? - x?7801 ffff? are reserved 1. additional action occurs on register access using the specif ied address. refer to register detailed section for more information. ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 365 of 539 e2p_msg_addr x?7801 0048? epc to powerpc subsystem message address register r 1 e2p_doorbell x?7801 0058? epc to powerpc subsyste m doorbell register (powerpc access) r/rum p2e_msg_addr x?7801 0068? powerpc subsystem to epc message address register r/w p2e_doorbell x?7801 0070? powerpc subsystem to ep c doorbell register (powerpc access) r/sum e2h_msg_resource x?7801 0080? epc to pci host message resource register r/w e2h_msg_addr x?7801 0088? epc to pci host message address register r 1 e2h_doorbell x?7801 0098? epc to pci host doorbell register (pci host access) r/rum h2e_msg_addr x?7801 00a8? pci host to epc message address register r/w msg_status x?7801 00a0? message status register r h2e_doorbell x?7801 00b0? pci host to epc doorbell register (pci host access) r/sum sear x'7801 00b8' slave error address register r sesr x'7801 00c0' slave error status register rwr 1 perr_cntr x'7801 00c8' parity error counter register r pwrpc_inst_store x?0000 0000? - x?07ff ffff? powerpc instruction/data dram r/w table 10-4. plb address map for mailbox and dram interface macro (page 2 of 2) symbolic address plb address description access unassigned addresses in the range x?7801 0000? - x?7801 ffff? are reserved 1. additional action occurs on register access using the specif ied address. refer to register detailed section for more information. ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 366 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 10.4 cab address map some components of the embedded powerpc subsystem are also accessible via the np2g?s cab interface. these components are accessed using cab addresses as shown in the cab address map. table 10-5. cab address map for mailbox and dram interface macro symbolic address cab address description access boot_redir_inst x?3800 0110? - x?3800 0117? boot redirection instruction registers for instruction addresses x?ffff ffe0? - x?ffff fffc? r/w pwrpc_mach_chk x?3800 0210? powerpc subsystem machine check register r e2p_msg_resource x?3801 0010 ? epc to powerpc subsystem message resource register r 1 e2p_msg_addr x?3801 0020? epc to powerpc subsystem message address register r/w e2p_doorbell x?3801 0040? epc to powerpc d oorbell register (powerpc access) r/sum p2e_msg_addr x?3801 0080? powerpc subsystem to epc message address register r x?3802 0010? powerpc subsystem to epc message address register r 1 p2e_doorbell x?3801 0100? powerpc subsystem to epc doorbell register (powerpc access) r/rum e2h_msg_resource x?3801 0200? epc to pci host message resource register r 1 e2h_msg_addr x?3801 0400? epc to pci host message address register r/w e2h_doorbell x?3801 0800? epc to pci host d oorbell register (pci host access) r/sum h2e_msg_addr x?3801 1000? pci host to epc message address register r 1 x?3802 0020? pci host to epc message address register r 1 h2e_doorbell x?3801 2000? pci host to epc doorbell register (pci host access) r/rum msg_status x?3801 4000? message status register r 1. additional action occurs on register access using the specif ied address. refer to register detailed section for more information. ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 367 of 539 10.5 universal interrupt controller (uic) macro the universal interrupt controller (uic) provides all the necessary control, status, and communication between the various of interrupts sources and the micr oprocessor core. the uic supports six on-chip and two external sources of interrupts. status reporting (using the uic status register (uicsr)) is provided to ensure that systems software can determine the current and interrupting state of the system and respond appropri- ately. software can generate interrupts to simplify software development and for diagnostics. the interrupts can be programmed, using the uic critical register (uiccr), to generate either a critical or a non-critical interrupt signal. the uic supports internal and external interrupt sources as defined in table 10-6 . the on-chip interrupts (interrupts 0, and 3-7) and the external interrupts (interrupts 1-2) are programmable. however, the on-chip interrupts must be programmed as shown in table 10-6. for details regarding the control of the uic, including the programming of interrupts, see the ibm powerpc 405gp embedded processor user?s manual ( http://www-3.ibm.com/chips/techlib/techlib.nsf/products/ powerpc_405gp_embedded_processor table 10-6. uic interrupt assignments interrupt polarity sensitivity interrupt source 0 high edge dram d6 parity error 1 programmable programmable external interrupt 0 (pci_bus_nm_int input pin) 2 programmable programmable external in terrupt 1 (pci_bus_m_int input pin) 3 high level pci host to powerpc doorbell interrupt 4 high level pci host to powerpc message interrupt 5 high level embedded processor complex to powerpc doorbell interrupt 6 high level embedded processor complex to powerpc message interrupt 7 high level pci command write interrupt generated when an external pci master writes to the pci command register or bit 13 of the bridge options 2 register is set to ?1? via pci conf iguration. see description of the pci macro?s bridge options 2 register in the ppc405gp embedded control- ler user?s manual for details. 8-31 high level unused, interrupt input to uic tied low. ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 368 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 10.6 pci/plb bridge macro the peripheral component interconnect (pci) interface controller provides an interface for connecting plb- compliant devices to pci device s. the controller complies with pc i specification, version 2.2 ( http://www.pcisig.com ). values of the pci device configuration header for the are initialized by hardware. these values are shown in table 10-7 . when the boot picocode is loaded from the management bus (boot_picocode is tied to ?0?) and the powerpc subsystem boots from dram d6 (boot_ppc is tied to ?0?, see 2.1.8 miscellaneous pins on page 75), a general reset initializes the pci/plb macro?s bridge options 2 register (pcibrdgopt2) with its host configuration enable bit set to ?0? (disabled). this allows the powerpc subsystem to alter the contents of the pci device configuration header registers prio r to access by external configuration. the powerpc code then enables external host configuration. the pci/plb macro responds as a target on the plb bus in several address ranges. these ranges allow a plb master to configure the pci/plb macro, and to cause the pci/plb macro to generate memory, i/o, configuration, interrupt acknowledge, and special cycles to the pci bus. table 10-8 shows the address map from the view of the plb, that is, as dec oded by the pci/plb macro as a plb slave. table 10-7. np2g pci device configuration header values register name register value vendor id x?1014? device id x?01e8? revision id x?00? class code x?028000? subsystem id x?0000? subsystem vendor id x?0000? table 10-8. plb address map for pci/plb macro (page 1 of 2) plb address range description pci address range x?e800 0000? - x?e800 ffff? pci i/o accesses to this range are translated to an i/o access on pci in the range 0 to 64 kb - 1 x?0000 0000? - x?0000 ffff? (i/o) x?e801 0000 x?e87f ffff? reserved pci/plb macro does not respond (oth er bridges use this space for non-contiguous i/o). x?e880 0000? - x?ebff ffff? pci i/o accesses to this range are translated to an i/o access on pci in the range 8 mb to 64 mb - 1 x?0080 0000? - x?03ff ffff? (i/o) x?ec00 0000? - x?eebf ffff? reserved pci/plb macro does not respond x?eec0 0000? - x?eecf ffff? pci configuration address and data x?eec0 0000?: pcicfgaddr x?eec0 0004?: pcicfgdata x?eec0 0008? - x?eecf ffff?: rese rved (can mirror pcicfgdata) ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 369 of 539 following a general reset of the np2g, the pci target map 1 is enabled for a pci address range of 128 kb and is mapped to the plb address range of x?78 00 0000 to x?7801 ffff?. the corresponding pci base address for this range must be set by pci configuratio n of the pci ptm1 base address register. likewise, the pci target map 2 is enabled for a pci address range of 128 mb and is mapped to the plb address range of x?0000 0000 to x?07ff ffff?. the corresponding pci base address for this range must be set by pci configuration of the pci ptm2 base address register. the pci/plb macro has a mode that enables a plb master to access a pci memory range without initial configuration cycles. this mode is enabled by strapping the boot_ppc input pin high. system designers, for instance, may use this mode to allow a processor to ac cess a boot rom in pci memory space. in this mode x?eed0 0000? - x?eedf ffff? pci interrupt acknowledge and special cycle x?eed0 0000? read: interrupt acknowledge x?eed0 0000? write: special cycle x?eed0 0004? - x?eedf ffff?: re served (can mirror interrupt acknowledge and special cycle) x?eee0 0000? - x?ef3f ffff? reserved. pci/plb macro does not respond. x?ef40 0000? - x?ef4f ffff? pci/plb macro local configuration registers x?ef40 0000?: pmm0la x?ef40 0004?: pmm0ma x?ef40 0008?: pmm0pcila x?ef40 000c?: pmm0pciha x?ef40 0010?: pmm1la x?ef40 0014?: pmm1ma x?ef40 0018?: pmm1pcila x?ef40 001c?: pmm1pciha x?ef40 0020?: pmm2la x?ef40 0024?: pmm2ma x?ef40 0028?: pmm2pcila x?ef40 002c?: pmm2pciha x?ef40 0030?: ptm1ms x?ef40 0034?: ptm1la x?ef40 0038?: ptm2ms x?ef40 003c?: ptm2la x?f400 0400? - x?ef4f ffff?: reserv ed (can mirror pci local regis- ters) x?0000 0000? - x?ffff ffff? pci memory - range 0 pmm 0 registers map a region in plb space to a region in pci mem- ory space. the address ranges ar e fully programmable. the pci address is 64 bits. x?0000 0000 0000 0000? x?ffff ffff ffff ffff? x?0000 0000? - x?ffff ffff? pci memory - range 1 pmm 1 registers map a region in plb space to a region in pci mem- ory space. the address ranges ar e fully programmable. the pci address is 64 bits. x?0000 0000 0000 0000? x?ffff ffff ffff ffff? x?0000 0000? - x?ffff ffff? pci memory - range 2 pmm 2 registers map a region in plb space to a region in pci mem- ory space. the address ranges ar e fully programmable. the pci address is 64 bits. x?0000 0000 0000 0000? x?ffff ffff ffff ffff? table 10-8. plb address map for pci/plb macro (page 2 of 2) plb address range description pci address range ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 370 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 the pci/plb macro comes out of reset with pmm0 enabled and programmed for the address range x?fffe 0000? - x?ffff ffff?. the me field of the pci comm and register (pcicmd[me]) is also set to 1 after reset. enabling pci boot mode does not prevent subsequent updates to the pmm0 registers. unless the boot picocode is loaded from the spm (boot_picocode tied to ?0?) and the powerpc subsystem boots from dram d6 (boot_ppc tied to ?0?), a general reset initializes the pci/plb macro?s bridge options 2 register (pcibrdgopt2) with its host configuration enable bit set to ?1? (e nabled). this allows an external source to access the pci/plb macr o?s configuration registers. otherwise, powerpc code must enable external host configuration and may alter the contents of the pci device configuration header registers prior to enabling external host configuration. table 10-9. pci/plb bridge macro configuration registers (page 1 of 2) register offset description access local host vendid x?01? - x?00? pci vendor id r/w r devid x?03? - x?02? pci device id r/w r cmd x?05? - x?04? pci command register r/w r/w status x?07? - x?06? pci status register r/w r/w revid x?08? pci revision id r/w r cls x?0b? - x?09? pci class register r/w r cachels x?0c? pci cache line size r r lattim x?0d? pci latency timer r/w r/w hdtype x?0e? pci header type r r bist x?0f? pci built in self test control r r ptm1bar x?17? - x?14? pci ptm 1 bar r/w r/w ptm2bar x?1b? - x?18? pci ptm 2 bar r/w r/w sbsysvid x?2d? - x?2c? pci subsystem vendor id r/w r sbsysid x?2f? - x?2e? pci subsystem id r/w r cap x?34? pci capabilities pointer r r intln x?3c? pci interrupt line r/w r/w intpn x?3d? pci interrupt pin r r mingnt x?3e? pci minimum grant r r maxltncy x?3f? pci maximum latency r r ics x?44? pci interrupt control/status r/w r/w erren x?48? error enable r/w r/w errsts x?49? error status r/w r/w brdgopt1 x?4b? - x?4a? pci bridge options 1 r/w r/w plbbesr0 x?4f? - x?4c? pci slave error syndrome 0 r/w r/w plbbesr1 x?53? - x?50? pci slave error syndrome 1 r/w r/w plbbear x?57? - x?54? pci slave error address register r r capid x?58? capability identifier r r ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 371 of 539 for further details regarding the pci/plb macro?s control and configuration registers, see the ibm powerpc 405gp embedded processor user?s manual ( http://www-3.ibm.com/chips/techlib/techlib.nsf/products/ powerpc_405gp_embedded_processor ). nextiptr x?59? next item pointer r r pmc x?5b? - x?5a? power management capabilities r r pmcsr x?5d? - x?5c? power management control status r/w r/w pmcsrbse x?5e? pmcsr pci to pci bridge support extensions r r data x?5f? data r r brdgopt2 x?63? - x?60? pci bridge options 2 r/w r/w pmscrr x?64? power management state change request register r/w r/w table 10-9. pci/plb bridge macro configuration registers (page 2 of 2) register offset description access local host ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 372 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 10.7 cab interface macro the cab interface macro provides duplicate facilities to s upport indepe ndent cab access of ibm network processor control and status facilities by the pci host processor and the embedded po werpc subsystem. exclusive access to these facilities, if requ ired, is enforced through software discipline. the pci host processor can access the ibm network processor?s cab interface through the following mech- anism: after pci configuration, one or more ranges of pci addresses are mapped to plb addresses. accessing these pci addresses also accesses powe rpc plb resources, which include the following cab interface registers: cab address register is set to the value of the cab address to be read or written. cab control register is written with parameters that control the behavior for cab access. cab data register, when accessed, initiates a cab access and determines its type (read or write). if the cab data register is written, t hen the cab access will be a write ac cess. likewise reading the cab data register will result in a cab read access. status register is read to determine, for polled access, whether read data is ready (rd_rdy). the cab control register (w/p ) controls the two modes of plb protocol for cab access: wait access, w/p = ?1?, causes the cab interface macro to insert wait states on the plb until the cab access is complete. software need not read the cab status register to determine completion. cab access in polled mode requires software to follow the protocol defined in figure 10-2: polled access flow diagram on page 373. behavior for cab accesses not following this protocol is undefined and may result in adverse effe cts. polled access, w/p = ?0? requires software to read the cab status register to synchronize software with the hardware when performing a cab transaction. a cab read transaction requires at least two read accesses to the cab_data register. an additional read access of the cab_data register may be required if the software is not synchronized with the hardware. software syn- chronization is determined initially by reading the cab_status register. the software is not synchronized when the rd_rdy status bit is set to ?1?. synchronization is achieved by reading the cab_data register and discarding the result. a subsequent read of the cab data register initiates a cab read access from the cab address con- tained in the cab address register. the data returned as a result of this read of the cab_data register is stale data and is discarded by software. software must then perform a final read of the cab_data regis- ter to acquire the data accessed on the cab and return the cab interface to its starting state (rd_rdy = ?0?). the np2g causes subsequent accesses to the cab inte rface registers to be retried until a pending cab access is complete. prolonged locking of the cab by the epc will result in exte nded retries by the pow- erpc subsystem or pci host. under these conditions , system hardware and software design must be able to tolerate long periods of retry. ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 373 of 539 figure 10-2. polled access flow diagram start read cab_status read cab_data and discard results read cab_data and discard results y n rd_rdy = 1 cab read or write wr rd read cab_data (sets rd_rdy to ?0?) finish write cab_data with data value rd_rdy = ?1? hardware/software synchronization pending cab read cab i/f access retried pending cab write cab i/f access retried ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 374 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 10.7.1 powerpc cab address (pwrpc_cab_addr) register the powerpc cab address register is accessible from the plb and supplies a cab address value for powerpc subsystem access to np2g structures via the cab interface. 10.7.2 powerpc cab data (pwrpc_cab_data) register the powerpc cab data register is accessible from the plb and contains the value of cab data written or read when the powerpc subsystem accesses np2g st ructures via the cab interface. writing to the pwrpc_cab_data register has the side effect of initiating a write access on the cab. the data value written to the pwrpc_cab_data register is written to the cab address contained in the pwrpc_cab_addr register. when the pwrpc_cab_cntl register has been configured with its w/p bit set to ?1? or if its w/p bit is set to ?0? and the rd_rdy bit of the pwrpc_cab_status register is set to ?0?, a read of the pwrpc_cab_data register has the side effect of initiating a corresponding read access on the cab. at the end of the cab read access, the data value indicated by the pwrpc_cab_addr register is stored in the pwrpc_cab_data register and the rd_rdy bit of the pwrpc_cab_status register is set to '1. when the w/p bit set to ?1?, the data value is also returned to the plb. otherwise, a subsequent read access of the pwrpc_cab_data register is required to retrieve the data value. access type read/write base address (plb) x?7800 0000? pwrpc_cab_addr 012345678910111213141516171819202122232425262728293031 field name bit(s) reset description pwrpc_cab_addr 0:31 x?0000 0000? cab address value for powerpc subsys tem access to np2g structures via the cab interface. access type read/write base address (plb) x?7800 0008? pwrpc_cab_data 012345678910111213141516171819202122232425262728293031 field name bit(s) reset description pwrpc_cab_data 0:31 x?0000 0000? cab data written or read when the powerpc subsystem accesses np2g structures via the cab interface. ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 375 of 539 10.7.3 powerpc cab control (pwrpc_cab_cntl) register the powerpc cab control register is accessible from the plb and controls the cab access protocol used by the powerpc subsystem. the bit in this register indica tes whether the wait or polled protocol is used when the powerpc subsystem accesses cab connected structures within the np2g. 10.7.4 powerpc cab status (p wrpc_cab_status) register the powerpc cab status register is accessible from the plb and monitors the status of powerpc cab accesses. bits within this register indicate the stat us of powerpc subsystem accesses of cab connected structures within the np2g. access type read/write base address (plb) x?7800 0010? reserved w/p 012345678910111213141516171819202122232425262728293031 field name bit(s) reset description reserved 0:30 reserved w/p 31 0 wait or polled access control value 0 powerpc subsystem polls the pw rpc_cab_status register to determine when access is complete 1 cab interface macro inserts wait states on the plb until the cab access is complete access type read base address (plb) x?7800 0018? reserved rd_rdy reserved 012345678910111213141516171819202122232425262728293031 field name bit(s) description reserved 0:29 reserved rd_rdy 30 read data ready indicator (used for polled access mode w/p = ?0? only) 0 no data in cab data register, a new cab access can begin. 1 data from a cab read access is waiting in the cab data register reserved 31 reserved ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 376 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 10.7.5 powerpc cab mask (p wrpc_cab_mask) register the powerpc cab mask (pwrpc_cab_mask) register is accessible from the plb and supplies a mask value used in conjunction with a write-under-mask cab access. each ?1? bit of the mask indicates which bits of the cab register will be updated . the corresponding bit value of t he pwrpc_cab_wum_data register is used to update the cab register . all other bits of the cab re gister will remain unaltered. hardware reset x?0000 0000? plb address x?7800 0020? powerpc cab mask register access type read/write cab_mask 012345678910111213141516171819202122232425262728293031 field name bit(s) description pwrpc_cab_mask 0:31 cab mask value for powerpc subsystem access to ibm network processor structures via the cab interface. each ?1? bit of the mask indicates which bits of the cab register will be updated. ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 377 of 539 10.7.6 powerpc cab write under ma sk data (pwrpc_cab_wum_data) the powerpc cab data (pwrpc_cab_wum_data) register is accessible from the plb and contains the value of cab data written when the powerpc subsyste m accesses ibm network processor structures via the cab interface using the write-under-mask function. writing to the pwrpc_cab_wum_data register has the side effect of initiating a write-under-mask access on the cab. the data value written to the pwrpc_cab_wum_data register is combined with the contents of the pwrpc_cab_mask register and the contents of the cab register indicated by the pwrpc_c ab_addr register. for each bit location in which the value of the pwrpc_cab_mask register is ?1?, the corresponding bit of the cab register is updated with the contents of the pwrpc_cab_wum_data register. all other bits of the cab register remain unaltered. the bits of this register are shared with t he pwrpc_cab_data register. writin g to this register will alter the contents of the pwrpc_cab_data register. 10.7.7 pci host cab address (host_cab_addr) register the pci host cab address register is accessible fr om the plb and supplies a cab address value for pci host access to np2g structures via the cab interface. hardware reset x?0000 0000? plb address x?7800 0028? powerpc cab wum data register access type write cab_wum_data 012345678910111213141516171819202122232425262728293031 field name bit(s) description pwrpc_cab_wum_data 0:31 cab data to be combined with the pwrpc_c ab_mask register when the powerpc sub- system accesses ibm network processor stru ctures via the cab interface in write- under_mask mode. access type read/write base address (plb) x?7800 8000? host_cab_addr 012345678910111213141516171819202122232425262728293031 field name bit(s) reset description host_cab_addr 0:31 x?0000 0000? cab address value for pci host access to np2g structures via the cab interface. ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 378 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 10.7.8 pci host cab data (host_cab_data) register the pci host cab data register is accessible from the plb and contains the value of cab data written or read when the pci host accesses np2g structures via the cab interface. writing to the host_cab_data register has the side effect of initiating a write access on the cab. the data value written to the host_cab_data register is written to the cab address contained in the host_cab_addr register. when the host_cab_cntl register has been configured with its w/p bit set to ?1? or if its w/p bit is set to ?0? and the rd_rdy bit of the host_cab_status register is set to ?0?, a read of the host_cab_data register has the side effect of initiating a corresponding read access on the cab. at the end of the cab read access, the data value indicated by the host_cab_addr register is stored in the host_cab_data register and the rd_rdy bit of the host_cab_status register is set to '1. when the w/p bit set to ?1?, the data value is also returned to the plb. otherwise, a subsequent read access of the host_cab_data register is required to retrieve the data value. 10.7.9 pci host cab control (host_cab_cntl) register the pci host control register is accessible from the plb and controls the cab access protocol used by the pci host. the bit in this register indicates whether the wait or polled protocol is used when the pci host accesses cab connected structures within the np2g. access type read/write base address (plb) x?7800 8008? host_cab_data 012345678910111213141516171819202122232425262728293031 field name bit(s) reset description host_cab_data 0:31 x?0000 0000? cab data written or read when the pc i host accesses np2g structures via the cab interface. reserved w/p 012345678910111213141516171819202122232425262728293031 access type read/write base address (plb) x?7800 8010? field name bit(s) reset description reserved 0:30 reserved w/p 31 0 wait or polled access control value 0 pci host polls the host_cab_status register to determine when access is complete 1 cab interface macro inserts wait states on the plb until the cab access is complete ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 379 of 539 10.7.10 pci host cab status (host_cab_status) register the pci host cab status register is accessible from the plb and monitors the status of pci host cab accesses. bits within this register indicate the stat us of pci host accesses of cab connected structures within the np2g. 10.7.11 pci host cab mask (host_cab_mask) register the pci host cab mask (pwrpc_cab_ma sk) register is accessible from the plb and supplies a mask value used in conjunction with a write-under-mask cab access. each ?1? bit of the mask indicates which bits of the cab register will be updated. the co rresponding bit value of the host_c ab_wum_data register is used to update the cab register. all other bits of the cab regi ster will remain unaltered. access type read base address (plb) x?7800 8018? reserved rd_rdy reserved 012345678910111213141516171819202122232425262728293031 field name bit(s) description reserved 0:29 reserved rd_rdy 30 read data ready indicator (used for polled access mode w/p = ?0? only) 0 no data in cab data register, a new cab access can begin. 1 data from a cab read access is waiting in the cab data register reserved 31 reserved hardware reset x?0000 0000? plb address x?7800 8020? pci host cab mask register access type read/write cab_mask 012345678910111213141516171819202122232425262728293031 field name bit(s) description host_cab_mask 0:31 cab mask value for pci host access to ibm network processor structures via the cab interface. each ?1? bit of the mask indicates which bits of the cab register will be updated. ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 380 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 10.7.12 pci host cab write under mask data (host_cab_wum_data) register the pci host cab data (host_cab_wum_data) register is accessible from the plb and contains the value of cab data written when the pci host accesses ibm network processor structures via the cab interface using the write-under-mask function. writing to the host_cab_wum_data register has the side effect of initi- ating a write-under-mask access on the cab. the data value written to the pwrpc_cab_wum_data register is combined with the contents of the pwrpc_cab_mask re gister and the contents of the cab register indi- cated by the pwrpc_cab_addr register. for each bit location in which the value of the host_cab_mask reg- ister is ?1?, the corresponding bit of the cab register is updated with the contents of the host_cab_wum_data register. all other bits of the cab register remain unaltered. the bits of this register are shared with the host_cab_data register. writing to this register will alter the con- tents of the host_cab_data register. hardware reset x?0000 0000? plb address x?7800 8028? pci host cab wum data register access type write cab_wum_data 012345678910111213141516171819202122232425262728293031 field name bit(s) description host_cab_wum_data 0:31 cab data to be combined with the host_cab_mask register when the pci host accesses ibm network processo r structures via the cab interface in write-under_mask mode. ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 381 of 539 10.8 mailbox communications and dram interface macro the mailbox and dram interface macro consists of two major portions. the first portion is a set of facilities for constructing and signalling messages between the various processors. a set of message resource regis- ters allocates buffers for message construction, a se t of message address regi sters accomplishes message signalling, and a set of door bell registers accomplishes ot her inter-proc essor signalling. the second portion is hardware that interfaces the np2g?s dram controller to the plb. the dram interface maps a range of plb addresses into dram addresses. dram connected via th is interface stores powe rpc instructions, message data, and other data associated with the powerpc subsystem. the mailbox and dram interface macro also provides re direction of boot code. this function is used in system implementations in which the np2g does not boot from pci memory. in these cases, hardware decodes the first powerpc instruction fetch and supplies up to eight instructions from registers internal to the mailbox and dram interface. these registers are accessible via the cab and are loaded by software prior to releasing the powerpc processor?s reset (pwrpc_reset). code stored in these registers redirects execution to locations in the dram. ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 382 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 10.8.1 mailbox communications between pci host and powerpc subsystem communication between the pci host and the powerpc subsystem is accomplished through pci host to powerpc subsystem (h2p) and powerpc subsystem to pci host (p2h) interrupts. the p2h interrupt is implemented by asserting the np2g?s inta# signal out put. pci interrupts are level sensitive and are asyn- chronous with the pci_clk signal. the existing pci macro?s inta# signal is supplemented with other inter- rupt generation outside of the pci macro. using the pci macro, the powerpc subsystem can send an interrupt to the pci host by writing to the pci/plb macro?s pci interrupt control/status register. this interrupt signal is recorded in the pci interrupt status regist er. doorbell and message register operations are addi- tional sources of pci interrupts. the pci macro can interrupt the powerpc subsystem by setting bit 13 of the pci macro?s bridge options 2 register. this interrupt signal is applied to the powerpc universal interrupt controller (uic). communications between the pci host and the powerpc subsystem use message buffers in pci address space. software running in the pci host manages these buffers. for communications from the powerpc subsystem to the pci host, the starting address of empty message buffers are stored in the p2h message resource (p2h_msg_resource) register. this register is accompanied by a p2h_bufr_valid status flag, located in the msg_status register, that indicates whet her or not the p2h_msg_resource register contains a valid buffer address. the pci host writes the p2h_msg_resource register with the pci address of an empty message buffer and the valid indicator flag is set. t he powerpc subsystem reads the flag value when a message buffer is required and then reads the valid message buffer address value from the p2h_msg_resource register. reading the p2h_msg_resource register resets the valid indicator bit. by polling th is indicator bit, the pci host knows when to replenish the p2h_msg_resource register with a new buffer address value. having acquired a message buffer, the powerpc subsystem composes a message in the buffer and writes the buffer?s starting address value into the p2h_msg_addr register. this write also sets the pci_interr_status register?s p2h_msg bit. a pci interr upt is generated when the corresponding bit of the pci_interr_ena register is set. the pci host reads the p2h_msg_addr register to find and process the message. the read clears the interrupt condition. for communication from the pci host to the powerpc, messages are composed in buffers in the pci address space. each message is then signalled to the powerpc subsystem by writing its starting pci address value into the h2p_msg_addr register. writing this register sets the h2p_msg_interr to the powerpc uic and sets the h2p_msg_busy bit of the msg_status register. an interrupt is generated when enabled by the uic. the powerpc subsystem reads the h2p_msg_addr register at one address location to find and process the message and, due to the read, the interrupt condition is cleared. a subsequent read of the h2p_msg addr register at anot her address location will reset the h2 p_msg_busy bit of the msg_status register. this second read signals the pci host that the powerpc subsystem has finished processing the data buffer, allowing it to be reused. the p2h_msg_addr register is written by the powerp c subsystem and read by the pci host processor. whenever the powerpc subsystem writes the p2h_msg_addr register, a bit in the pci interrupt status register is set to ?1? and is independent of the value written. the pci interrupt status register indicates the source of the pci interrupt. the pci interrupt status register bit is reset to '0' when the pci host processor reads the p2h_msg_addr register. software discipline controls the setting of the interrupt by the powerpc subsystem and the resetting of the interrupt by the pci host (only the powerpc subsystem writes this register and only the pci host reads this register). ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 383 of 539 the doorbell register is written and read by either the powerpc subsystem or the pcihost processor. the value recorded in this register depends upon the data value to be written, the current contents of the register, and whether the powerpc subsystem or the pci host processor is writing the register. when written by the powerpc subsystem , each bit of the register?s curr ent contents is compared with the corresponding data bit to be written. if the value of the data bit is ?1?, then the corresponding doorbell register is set to ?1?. otherwise it remains unch anged (?0? or ?1?). this effect is referred to as set under mask (sum). when written by the pci host processor, each bit of the register?s current contents is compared with the corresponding data bit to be written. if the value of the data bit is ?1?, then the corresponding doorbell register bit is reset to ?0?. otherwise, it remains unchanged (?0? or ?1?). this effect is referred to as reset under mask (rum). if one or more of the bits in the doorbell register are ?1?, then a signal is generated and stored in the pci interrupt status register. any of the signals recorded as ?1? in the pci interrupt status register activates the inta# signal if the corre- sponding condition is enabled in the np2g?s pci inte rrupt enable register. the pci host processor reads the pci interrupt status register to determine the interrupt source. ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 384 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 10.8.2 pci interrupt status (pci_interr_status) register the pci interrupt status register is accessible from the plb and records the source of the pci interrupts generated by the np2g. this register?s bits are set by hardware and are read by pci host software. when the interrupt source is cleared, the corresponding bi t of the pci_interr_status register is also cleared. access type read only base address (plb) x?7801 0000? reserved pci_macro reserved e2h_db e2h_msg p2h_db p2h_msg 012345678910111213141516171819202122232425262728293031 field name bit(s) reset description reserved 0:23 reserved pci_macro 24 0 pci interrupt from macro indicator. a pci interrupt is asserted by the plb to pci macro when bit 0 of the macro' s pciics register is set by software to a value of '1'. see the ibm powerpc 405gp embedded processor user?s manual for details. 0 interrupt absent 1 interrupt present reserved 25:27 reserved e2h_db 28 0 epc to pci host doorbell indicator. 0 pci interrupt from e2 h_doorbell register absent 1 pci interrupt from e2h_ doorbell register present e2h_msg 29 0 epc to pci host message indicator. 0 pci interrupt from e2h_message register absent 1 pci interrupt from e2h_message register present p2h_db 30 0 powerpc subsystem to pci host doorbell indicator. 0 pci interrupt from p2 h_doorbell register absent 1 pci interrupt from p2h_ doorbell register present p2h_msg 31 0 powerpc subsystem to pci host message indicator. 0 pci interrupt from p2h_message register absent 1 pci interrupt from p2h_message register present ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 385 of 539 10.8.3 pci interrupt enable (pci_interr_ena) register the pci interrupt enable register is accessible from the plb and enables pci interrupts from sources within the np2g. access type read/write base address (plb) x?7801 0008? reserved pci_macro reserved e2h_db e2h_msg p2h_db p2h_msg 012345678910111213141516171819202122232425262728293031 field name bit(s) reset description reserved 0:23 reserved pci_macro 24 0 pci macro interrupt - controls the asse rtion of a pci interrupt from the pci macro. a pci interrupt is asserted by the plb to pci macro when bit 0 of the macro's pciics register is set by software to a value of '1'. see the ibm powerpc 405gp embedded processor user?s manual for details. 0 interrupt disabled 1 interrupt enabled reserved 25:27 reserved e2h_db 28 0 epc to pci host doorbell interrupt - controls the assertion of a pci inter- rupt from the e2h_doorbell register. 0 interrupt disabled 1 interrupt enabled e2h_msg 29 0 epc to pci host message interrupt - controls the assertion of a pci inter- rupt from the e2h_message register. 0 interrupt disabled 1 interrupt enabled p2h_db 30 0 powerpc subsystem to pci host doorbell interrupt - controls the asser- tion of a pci interrupt from the p2h_doorbell register. 0 interrupt disabled 1 interrupt enabled p2h_msg 31 0 powerpc subsystem to pci host mess age interrupt - controls the asser- tion of a pci interrupt from the p2h_message register. 0 interrupt disabled 1 interrupt enabled ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 386 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 10.8.4 powerpc subsystem to pci host message resource (p2h_msg_resource) register the powerpc subsystem to pci host message resource register is accessible fr om the plb. the powerpc subsystem uses this register to obtain message bu ffers in pci address space for messages the powerpc subsystem sends to the pci host processor. the pci host writes the starting pci address value of a message buffer into the p2h_msg_resource register. writing to this register sets the p2h_bufr_valid flag found in the message status register (see 10.8.23 message status (msg_status) register on page 404) and reading the p2h_msg_resource register clears this flag. 10.8.5 powerpc subsystem to host message address (p2h_msg_addr) register the powerpc subsystem to pci host message address register is accessible from the plb and is used by the powerpc subsystem to send messages to the pci host processor. the value written into this register is the pci address at which the message begins. writing to this register sets the p2h_msg bit of the pci_interr_status register. when the corresponding bit of the pci_interr_ena register is set to ?1?, the inta# signal of the pci bus is activated. the p2h_msg bit of the pci_interr_status register is reset when the inter- rupt service routine reads the p2h_msg_addr register. access type read/write base address (plb) x?7801 0010? (additional actions occur when reading this register using this address. see register description for details.) p2h_msg_resource 012345678910111213141516171819202122232425262728293031 field name bit(s) reset description p2h_msg_resource 0:31 x?0000 0000? powerpc subsystem to pci host mess age resource value, written with the pci starting address of a message buffe r. writing this register sets to 1 the p2h_bufr_valid flag found in the message status register (see 10.8.23 message status (msg_status) register on page 404). reading this register sets to 0 the p2h_bufr_valid flag. access type read/write base address (plb) x?7801 0018? p2h_msg_addr 012345678910111213141516171819202122232425262728293031 field name bit(s) reset description p2h_msg_addr 0:31 x?0000 0000? powerpc subsystem to pci host me ssage address value, indicates the pci starting address of a message. ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 387 of 539 10.8.6 powerpc subsystem to host doorbell (p2h_doorbell) register the powerpc subsystem to pci host doorbell register is accessible from the plb and is used by the powerpc subsystem to signal interrupts to the pci host processor. the powerpc subsystem has read and sum write access to this register. the data contains the mask used to access this register. when bits of this register are set to ?1? and the corresponding bit of the pci_interr_ena register is set to ?1?, the inta# signal of the pci bus is activated. the pci host processor reads this register to determine which of the doorbells have been activated. the pci host processor has read and rum write access to this register using a different plb address value. access type power pc x?7801 0020? host x?7801 0028? base address (plb) power pc read/set under mask host read/reset under mask p2h_msg_doorbell 31 p2h_msg_doorbell 30 p2h_msg_doorbell 29 p2h_msg_doorbell 28 p2h_msg_doorbell 27 p2h_msg_doorbell 26 p2h_msg_doorbell 25 p2h_msg_doorbell 24 p2h_msg_doorbell 23 p2h_msg_doorbell 22 p2h_msg_doorbell 21 p2h_msg_doorbell 20 p2h_msg_doorbell 19 p2h_msg_doorbell 18 p2h_msg_doorbell 17 p2h_msg_doorbell 16 p2h_msg_doorbell 15 p2h_msg_doorbell 14 p2h_msg_doorbell 13 p2h_msg_doorbell 12 p2h_msg_doorbell 11 p2h_msg_doorbell 10 p2h_msg_doorbell 9 p2h_msg_doorbell 8 p2h_msg_doorbell 7 p2h_msg_doorbell 6 p2h_msg_doorbell 5 p2h_msg_doorbell 4 p2h_msg_doorbell 3 p2h_msg_doorbell 2 p2h_msg_doorbell 1 p2h_msg_doorbell 0 012345678910111213141516171819202122232425262728293031 field name bit(s) reset description p2h_msg_doorbell 31 0 0 powerpc subsystem to pci host doorbell - indicates which of the 32 pos- sible doorbells have been activated. 0 not activated 1 activated p2h_msg_doorbell 30:1 1:30 0 for all p2h_msg_doorbell 0 31 0 ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 388 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 10.8.7 host to powerpc subsystem message address (h2p_msg_addr) register the pci host to powerpc su bsystem message address register is accessible from the plb and is used by the pci host to send messages to the powerpc subsystem?s processor. the value written into this register is a message?s pci starting address. writing to this register activates the h2p_msg_interr input to the powerpc uic. when this interrupt is enabled, an interrupt to the powerpc subsystem is generated. reading this register resets the h2p_msg_interr input to the uic. r eading this register at the alternate plb address resets the message status register?s h2p_msg_busy bit (see 10.8.23 message status (msg_status) register on page 404). access type alternate read primary read/write base address (plb) alternate x?7801 0050? (additional actions occur when reading this register using this address. see register description for details.) primary x?7801 0060? (additional actions occur when reading this register using this address. see register description for details.) h2p_msg_addr 012345678910111213141516171819202122232425262728293031 field name bit(s) reset description h2p_msg_addr 0:31 x?0000 0000? the value is a message?s pci starting address. ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 389 of 539 10.8.8 host to powerpc subsystem doorbell (h2p_doorbell) register the pci host to powerpc subsystem doorbell (h2p_doorbell) register is accessible from the plb and is used by the pci host processor to signal interrupts to the powerpc subsystem. the pci host processor has read and sum write access to this register. the data contains the mask used to access this register. when any of this register?s bits are set to ?1?, an interrupt signal of the powerpc uic is activated. the powerpc subsystem reads this register to determine which of the doorbells have been activated. the powerpc subsystem has read and rum write access to this register using a different plb address value. access type host read/set un der mask write powerpc read/reset under mask write base address (plb) host x?7801 0030? powerpc x?7801 0038? h2p_doorbells h2p_msg_doorbell 31 h2p_msg_doorbell 30 h2p_msg_doorbell 29 h2p_msg_doorbell 28 h2p_msg_doorbell 27 h2p_msg_doorbell 26 h2p_msg_doorbell 25 h2p_msg_doorbell 24 h2p_msg_doorbell 23 h2p_msg_doorbell 22 h2p_msg_doorbell 21 h2p_msg_doorbell 20 h2p_msg_doorbell 19 h2p_msg_doorbell 18 h2p_msg_doorbell 17 h2p_msg_doorbell 16 h2p_msg_doorbell 15 h2p_msg_doorbell 14 h2p_msg_doorbell 13 h2p_msg_doorbell 12 h2p_msg_doorbell 11 h2p_msg_doorbell 10 h2p_msg_doorbell 9 h2p_msg_doorbell 8 h2p_msg_doorbell 7 h2p_msg_doorbell 6 h2p_msg_doorbell 5 h2p_msg_doorbell 4 h2p_msg_doorbell 3 h2p_msg_doorbell 2 h2p_msg_doorbell 1 h2p_msg_doorbell 0 012345678910111213141516171819202122232425262728293031 field name plb bit(s) reset description h2p_msg_doorbell 31 0 0 pci host to powerpc subsystem doorbell - indicates which of the 32 pos- sible doorbells have been activated. 0 not activated 1 activated h2p_msg_doorbell 30:1 1:30 0 for all h2p_msg_doorbell 0 31 0 ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 390 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 10.8.9 mailbox communications between powerpc subsystem and epc communication between the powerpc subsystem and the epc is accomplished by writing message data into buffers in the powerpc dram (d6) and signallin g the destination processo r with an interrupt. the powerpc software manages message data buffers for powerpc subsystem to epc (p2e) messages and epc to powerpc subsystem (e2p) messages. message data buffers are allocated to the epc by writing the buffers? starting address into the e2p_msg_resource register. writing to this register sets the e2p_bufr_valid flag in the msg_status register. this flag indicates to the epc that the buffer is valid and can be used by the epc. the epc reads the e2p_bufr_valid value when a message buffer is required. the epc then reads the e2p_msg_resource register via the cab interface to obtain the address of the message buffer and the e2p_bufr_valid indicator bit is reset. having acquired a message data buffer, the epc composes a message in the buffer and writes the buffer?s starting address value into the e2p_msg_addr register. writing to this register generates an inter- rupt signal to the powerpc uic. the powerpc subsyst em reads this register to find and process the message and, due to the read, the interrupt condition is cleared. to avoid message loss, the powerpc should not replenish the e2p_msg_resource register with a new buffer address value until the epc has returned the preceding buffer by writing the e2p_msg_addr register. there is no need for a p2e_msg_resource register because the powerpc software manages the message data buffers the powerpc subsystem composes a message in one of the data buffers and writes the starting address of the buffer into the p2e_msg_addr register. writing to this register produces an interrupt to the epc and sets the p2e_msg_busy bit of the msg_status register. as long as this flag is set, the epc is processing the message buffer. the epc reads the p2e_msg_addr register to locate the buffer in the powerpc dram. the epc resets the p2e_msg_busy bit by reading the p2e_msg_address register at an alternate cab address when message processing is complete. the powerpc subsystem will poll the busy flag to determine when the buffer can be reused. ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 391 of 539 10.8.10 epc to powerpc subsystem resource (e2p_msg_resource) register the powerpc subsystem accesses the epc to powerpc subsystem message resource register from the plb while the epc accesses this register from its c ab interface. the epc uses this register to obtain message buffers in the powerpc dram address space for messages it sends to the powerpc processor. the powerpc processor writes the starting dram address value of a message buffer. writing to this register sets the e2p_bufr_valid flag in the msg_status register (see 10.8.23 message status (msg_status) register on page 404). reading the e2p_msg_resource register from the cab resets this flag. cab view plb view cab view plb view access type cab read (see above description for additional actions that occur during a read of this register using this address.) plb read/write (see above description for additional actions that occur during a read of this register using this address.) base address cab x?3801 0010? plb x?7801 0040? e2p_msg_resource 313029282726252423222120191817161514131211109876543210 e2p_msg_resource 012345678910111213141516171819202122232425262728293031 field name bit(s) reset description e2p_msg_resource 31:0 x?0000 0000? epc to powerpc subsystem message resource - written with the pow- erpc dram starting address of a message buffer. field name bit(s) reset description e2p_msg_resource 0:31 x?0000 0000? epc to powerpc subsystem message resource - written with the pow- erpc dram starting address of a message buffer. ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 392 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 10.8.11 epc to powerpc subsystem message address (e2p_msg_addr) register the powerpc subsystem accesses the epc to powerpc subsystem message address register from the plb while the epc accesses this register from its cab interface. the epc uses this register to send messages to the powerpc processor. the value written into this register is the powerpc dram address at which the message begins. writing to this register se ts e2p_msg_interr input to the powerpc uic. when the uic is configured to enable this input, an interrupt signal to the powerpc processor is activated. reading the e2p_msg_addr register via the plb address resets the e2p_msg_interr input to the powerpc uic. cab view plb view cab view plb view access type cab read/write plb read base address cab x?3801 0020? plb x?7801 0048? (additional actions occur when reading this register using this address. see register description for details.) e2p_msg_addr 313029282726252423222120191817161514131211109876543210 e2p_msg_addr 012345678910111213141516171819202122232425262728293031 field name bit(s) reset description e2p_msg_addr 0:31 x?0000 0000? epc to powerpc subsystem message address - indicates the pci start- ing address of a message. field name bit(s) reset description e2p_msg_addr 0:31 x?0000 0000? epc to powerpc subsystem message address - indicates the pci start- ing address of a message. ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 393 of 539 10.8.12 epc to powerpc subsystem doorbell (e2p_doorbell) register the powerpc subsystem accesses the epc to powerpc subsystem doorbell register from the plb while the epc accesses this register from the cab interface. the epc uses this register to signal interrupts to the powerpc subsystem. the epc has read and sum write acce ss to this register using a cab address value. the data contains the mask used to access this register. when any of this register?s bits are set to ?1? an inter- rupt signal to the powerpc uic is activated. the powe rpc subsystem reads this register to determine which of the doorbells have been activated. the powerpc subsystem has read and rum write access to this register using a plb address value. cab view plb view cab view access type cab read/set under mask write plb read/reset under mask write base address cab x?3801 0040? plb x?7801 0058? e2p_doorbells e2p_msg_doorbell 31 e2p_msg_doorbell 30 e2p_msg_doorbell 29 e2p_msg_doorbell 28 e2p_msg_doorbell 27 e2p_msg_doorbell 26 e2p_msg_doorbell 25 e2p_msg_doorbell 24 e2p_msg_doorbell 23 e2p_msg_doorbell 22 e2p_msg_doorbell 21 e2p_msg_doorbell 20 e2p_msg_doorbell 19 e2p_msg_doorbell 18 e2p_msg_doorbell 17 e2p_msg_doorbell 16 e2p_msg_doorbell 15 e2p_msg_doorbell 14 e2p_msg_doorbell 13 e2p_msg_doorbell 12 e2p_msg_doorbell 11 e2p_msg_doorbell 10 e2p_msg_doorbell 9 e2p_msg_doorbell 8 e2p_msg_doorbell 7 e2p_msg_doorbell 6 e2p_msg_doorbell 5 e2p_msg_doorbell 4 e2p_msg_doorbell 3 e2p_msg_doorbell 2 e2p_msg_doorbell 1 e2p_msg_doorbell 0 313029282726252423222120191817161514131211109876543210 e2p_doorbells e2p_msg_doorbell 31 e2p_msg_doorbell 30 e2p_msg_doorbell 29 e2p_msg_doorbell 28 e2p_msg_doorbell 27 e2p_msg_doorbell 26 e2p_msg_doorbell 25 e2p_msg_doorbell 24 e2p_msg_doorbell 23 e2p_msg_doorbell 22 e2p_msg_doorbell 21 e2p_msg_doorbell 20 e2p_msg_doorbell 19 e2p_msg_doorbell 18 e2p_msg_doorbell 17 e2p_msg_doorbell 16 e2p_msg_doorbell 15 e2p_msg_doorbell 14 e2p_msg_doorbell 13 e2p_msg_doorbell 12 e2p_msg_doorbell 11 e2p_msg_doorbell 10 e2p_msg_doorbell 9 e2p_msg_doorbell 8 e2p_msg_doorbell 7 e2p_msg_doorbell 6 e2p_msg_doorbell 5 e2p_msg_doorbell 4 e2p_msg_doorbell 3 e2p_msg_doorbell 2 e2p_msg_doorbell 1 e2p_msg_doorbell 0 012345678910111213141516171819202122232425262728293031 field name bit(s) reset description e2p_msg_doorbell 31 31 0 epc to powerpc subsystem doorbell - indicates which of the 32 possible doorbells is activated. 0 not activated 1 activated e2p_msg_doorbell 30:1 30:1 0 for all e2p_msg_doorbell 0 0 0 ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 394 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 plb view 10.8.13 epc interrupt vector register the epc contains an interrupt vector 2 register which is accessible from the cab interface. this register records the source of epc interrupts generated by the np2g. this register?s bits are set by hardware and are read by epc software to determine the source of interrupts. 10.8.14 epc interrupt mask register the epc contains a interrupt mask 2 register which is accessible from the cab interface. this register enables epc interrupts from sources within the np2g. field name bit(s) reset description e2p_msg_doorbell 31 0 0 epc to powerpc subsystem doorbell - indicates which of the 32 possible doorbells is activated. 0 not activated 1 activated e2p_msg_doorbell 30:1 1:30 0 for all e2p_msg_doorbell 0 31 0 ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 395 of 539 10.8.15 powerpc subsystem to epc message address (p2e_msg_addr) register the powerpc subsystem accesses the powerpc subsystem to epc message address register from the plb, while the epc accesses this register from the cab interface. this register is used by the powerpc subsystem to send messages to the epc. the value written into this register is the powerpc dram address at which the message begins. writing to this register sets the p2e_msg_interr signal to the epc and the p2e_msg_busy bit of the msg_status register. readi ng the p2e_msg_addr register from the cab will reset the p2e_msg_interr signal to the epc. reading the p2e_msg_add r from an alternate cab address will reset the p2e_msg_busy bit of the msg_status register (see 10.8.23 message status (msg_status) register on page 404). cab view plb view cab view plb view access type primary read alternate read (additional actions occur when reading this register using this address. see register description for details.) plb read/write base address primary x?3801 0080? alternate x?3802 0010? plb x?7801 0068? p2e_msg_addr 313029282726252423222120191817161514131211109876543210 p2e_msg_addr 012345678910111213141516171819202122232425262728293031 field name bit(s) reset description p2e_msg_addr 31:0 x?0000 0000? powerpc subsystem to epc message address - indicates a message?s powerpc dram starting address. field name bit(s) reset description p2e_msg_addr 0:31 x?0000 0000? powerpc subsystem to epc message address - indicates a message?s powerpc dram starting address. ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 396 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 10.8.16 powerpc subsystem to epc doorbell (p2e_doorbell) register the powerpc subsystem accesses the powerpc subsystem to epc doorbell register from the plb, while the epc accesses this register from the cab interface. the powerpc subsystem uses this register to signal interrupts to the epc. the powerpc subsystem has read and sum write access to this register. the data contains the mask used to access this register. when any of this register?s bits are set to ?1?, an interrupt signal of the epc is activated. this register is read by the epc to determine which doorbells have been acti- vated. the epc has read and rum write access to this register using a cab address value. cab view plb view cab view access type cab read/reset under mask write plb read/set under mask write base address cab x?3801 0100? plb x?7801 0070? p2e_doorbells p2e_msg_doorbell 31 p2e_msg_doorbell 30 p2e_msg_doorbell 29 p2e_msg_doorbell 28 p2e_msg_doorbell 27 p2e_msg_doorbell 26 p2e_msg_doorbell 25 p2e_msg_doorbell 24 p2e_msg_doorbell 23 p2e_msg_doorbell 22 p2e_msg_doorbell 21 p2e_msg_doorbell 20 p2e_msg_doorbell 19 p2e_msg_doorbell 18 p2e_msg_doorbell 17 p2e_msg_doorbell 16 p2e_msg_doorbell 15 p2e_msg_doorbell 14 p2e_msg_doorbell 13 p2e_msg_doorbell 12 p2e_msg_doorbell 11 p2e_msg_doorbell 10 p2e_msg_doorbell 9 p2e_msg_doorbell 8 p2e_msg_doorbell 7 p2e_msg_doorbell 6 p2e_msg_doorbell 5 p2e_msg_doorbell 4 p2e_msg_doorbell 3 p2e_msg_doorbell 2 p2e_msg_doorbell 1 p2e_msg_doorbell 0 313029282726252423222120191817161514131211109876543210 p2e_doorbells p2e_msg_doorbell 31 p2e_msg_doorbell 30 p2e_msg_doorbell 29 p2e_msg_doorbell 28 p2e_msg_doorbell 27 p2e_msg_doorbell 26 p2e_msg_doorbell 25 p2e_msg_doorbell 24 p2e_msg_doorbell 23 p2e_msg_doorbell 22 p2e_msg_doorbell 21 p2e_msg_doorbell 20 p2e_msg_doorbell 19 p2e_msg_doorbell 18 p2e_msg_doorbell 17 p2e_msg_doorbell 16 p2e_msg_doorbell 15 p2e_msg_doorbell 14 p2e_msg_doorbell 13 p2e_msg_doorbell 12 p2e_msg_doorbell 11 p2e_msg_doorbell 10 p2e_msg_doorbell 9 p2e_msg_doorbell 8 p2e_msg_doorbell 7 p2e_msg_doorbell 6 p2e_msg_doorbell 5 p2e_msg_doorbell 4 p2e_msg_doorbell 3 p2e_msg_doorbell 2 p2e_msg_doorbell 1 p2e_msg_doorbell 0 012345678910111213141516171819202122232425262728293031 field name bit(s) reset description p2e_msg_doorbell 31 31 0 powerpc subsystem to epc doorbell. indicates which of the 32 possible doorbells is activated. 0 not activated 1 activated p2e_msg_doorbell 30:1 30:1 0 for all p2e_msg_doorbell 0 0 0 ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 397 of 539 plb view 10.8.17 mailbox communications between pci host and epc communication between the pci host processor and the epc is accomplished by writing message data into buffers in the powerpc dra m and signalling the destination proc essor with an interrupt. the pci host processor software manages message data buffers for pci host processor to epc (h2e) messages and epc to pci host processor (e2h) messages. message data buffers are allocated to the epc by writing the buffers? starting address into the e2h_msg_resource register. writing this register sets the e2h_bufr_valid flag in the msg_status register. this flag indicates to the epc that the buffer is valid and can be used by the epc. the epc reads the e2h_bufr_valid value when a message buffer is required. the epc then reads the e2h_msg_resource register via the cab interfac e and the e2p_bufr_valid indicator bit is reset. by polling this indicator bit, the pci host processor knows when to replenish the e2 h_msg_resource register with a new buffer address value. having acquired a message data buffer, the epc will compose a mess age in the buffer and write the buffer?s starting address value into the e2h_msg_addr register. writing to this register generates an interrupt to the pci host processor. the pci host processor reads this register to find and process the message. reading this register clears the interrupt condition. since the pci host processor software manages the message data buffers, there is no need for an h2e_msg_resource register. the pci host processor co mposes a message in one of the data buffers and writes the starting address of the buffer into the h2e_msg_addr register. writing to this register produces an interrupt input signal to the epc and sets the h2e_msg_busy bit of the msg_status register. as long as this flag is set, the epc is processing the message buffer. the epc reads the h2e_msg_addr register to locate the buffer in the powerpc dram and reset the interrupt input signal to the epc. the epc resets the h2e_msg_busy bit by reading the p2e_msg_addr register from an alternate cab address when message processing is complete. the pci host processor will po ll the h2e_msg_busy bit to det ermine when the buffer can be reused. field name bit(s) reset description p2e_msg_doorbell 31 0 0 powerpc subsystem to epc doorbell. indicates which of the 32 possible doorbells is activated. 0 not activated 1 activated p2e_msg_doorbell 30:1 1:30 0 for all p2e_msg_doorbell 0 31 0 ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 398 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 10.8.18 epc to pci host resource (e2h_msg_resource) register the pci host processor accesses the epc to pci host message resource register from the plb while the epc accesses this register from its cab interface. this epc uses this register to obtain message buffers in the powerpc dram address space for messages it se nds to the pci host processor. the pci host processor writes the starting dram address value of a message buffer into the e2p_msg_resource register. writing to this register sets the e2h_bufr_valid flag found in the message status register (see 10.8.23 message status (msg_status) register on page 404). reading the e2h_msg_resource register from the cab resets this flag. cab view plb view cab view plb view access type cab read (additional actions occur when reading this register using this address. see register description for details.) plb read/write base address cab x?3801 0200? plb x?7801 0080? e2h_msg_resource 313029282726252423222120191817161514131211109876543210 e2h_msg_resource 012345678910111213141516171819202122232425262728293031 field name bit(s) reset description e2h_msg_resource 31:0 x?0000 0000? epc to pci host message resource - written with the powerpc dram starting address of a message buffer. when reading this r egister via the cab, the e2h_bufr_valid flag found in the message status register (see 10.8.23 message status (msg_status) register on page 404) is set to 0. field name bit(s) reset description e2h_msg_resource 0:31 x?0000 0000? epc to pci host message resource - written with the powerpc dram starting address of a message buffer. when writing this register, the e2h_bufr_valid flag is set to 1. ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 399 of 539 10.8.19 epc to pci host message address (e2h_msg_addr) register the pci host processor accesses the epc to pci host message address register from the plb while the epc accesses this register from its cab interface. the epc uses this register to send messages to the pci host processor. the value written into this register is the powerpc dram address at which the message begins. writing to this register sets the e2h_msg bit of the pci_interr_status register. when the corre- sponding bit of the pci_interr_ena register is set to ?1?, an interrupt signal to the pci host processor is acti- vated. reading the e2h_msg_addr register from the plb resets the e2h_msg bit of the pci_interr_status register. cab view plb view cab view plb view access type cab read/write plb read base address cab x?3801 0400? plb x?7801 0088? (additional actions occur when reading this register using this address. see register description for details.) e2h_msg_addr 313029282726252423222120191817161514131211109876543210 e2h_msg_addr 012345678910111213141516171819202122232425262728293031 field name bit(s) reset description e2h_msg_addr 31:0 x?0000 0000? epc to pci host message address - indicates the powerpc dram start- ing address of a message. field name bit(s) reset description e2h_msg_addr 0:31 x?0000 0000? epc to pci host message address - indicates the powerpc dram start- ing address of a message. ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 400 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 10.8.20 epc to pci host doorbell (e2h_doorbell) register the pci host processor accesses the epc to pci host doorbell register from the plb while the epc accesses this register from the cab interface. the epc uses this register to signal interrupts to the pci host processor. the epc has read and sum write access to this register using a cab address value. the mask used to access this register is contained in the data. when any of this register?s bits are set to ?1? and the corresponding bit of the pci_interr_ena register is set to ?1?, an interrupt signal of the pci host processor is activated. this register is read by the pci host proces sor to determine which of the doorbells have been acti- vated. the pci host processor has read and rum write and read access to this register using a plb address value. cab view plb view cab view access type cab read/set under mask write plb read/reset under mask write base address cab x?3801 0800? plb x?7801 0098? e2h_doorbells e2h_msg_doorbell 31 e2h_msg_doorbell 30 e2h_msg_doorbell 29 e2h_msg_doorbell 28 e2h_msg_doorbell 27 e2h_msg_doorbell 26 e2h_msg_doorbell 25 e2h_msg_doorbell 24 e2h_msg_doorbell 23 e2h_msg_doorbell 22 e2h_msg_doorbell 21 e2h_msg_doorbell 20 e2h_msg_doorbell 19 e2h_msg_doorbell 18 e2h_msg_doorbell 17 e2h_msg_doorbell 16 e2h_msg_doorbell 15 e2h_msg_doorbell 14 e2h_msg_doorbell 13 e2h_msg_doorbell 12 e2h_msg_doorbell 11 e2h_msg_doorbell 10 e2h_msg_doorbell 9 e2h_msg_doorbell 8 e2h_msg_doorbell 7 e2h_msg_doorbell 6 e2h_msg_doorbell 5 e2h_msg_doorbell 4 e2h_msg_doorbell 3 e2h_msg_doorbell 2 e2h_msg_doorbell 1 e2h_msg_doorbell 0 313029282726252423222120191817161514131211109876543210 e2h_doorbells e2h_msg_doorbell 31 e2h_msg_doorbell 30 e2h_msg_doorbell 29 e2h_msg_doorbell 28 e2h_msg_doorbell 27 e2h_msg_doorbell 26 e2h_msg_doorbell 25 e2h_msg_doorbell 24 e2h_msg_doorbell 23 e2h_msg_doorbell 22 e2h_msg_doorbell 21 e2h_msg_doorbell 20 e2h_msg_doorbell 19 e2h_msg_doorbell 18 e2h_msg_doorbell 17 e2h_msg_doorbell 16 e2h_msg_doorbell 15 e2h_msg_doorbell 14 e2h_msg_doorbell 13 e2h_msg_doorbell 12 e2h_msg_doorbell 11 e2h_msg_doorbell 10 e2h_msg_doorbell 9 e2h_msg_doorbell 8 e2h_msg_doorbell 7 e2h_msg_doorbell 6 e2h_msg_doorbell 5 e2h_msg_doorbell 4 e2h_msg_doorbell 3 e2h_msg_doorbell 2 e2h_msg_doorbell 1 e2h_msg_doorbell 0 012345678910111213141516171819202122232425262728293031 field name bit(s) reset description e2h_msg_doorbell 31 31 0 epc to pci host doorbell - indicates wh ich of the 32 possible doorbells is activated. 0 not activated 1 activated e2h_msg_doorbell 30:1 30:1 0 for all e2h_msg_doorbell 0 0 0 ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 401 of 539 plb view field name bit(s) reset description e2h_msg_doorbell 31 0 0 epc to pci host doorbell - indicates wh ich of the 32 possible doorbells is activated. 0 not activated 1 activated e2h_msg_doorbell 30:1 1:30 0 for all e2h_msg_doorbell 0 31 0 ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 402 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 10.8.21 pci host to epc message address (h2e_msg_addr) register the pci host processor accesses the pci host to epc message address register from the plb while the epc accesses this register from the cab interface. the pci host uses this register to send messages to the epc. the value written into this register is the powerpc dram address at which the message begins. writing to this register sets the h2e_msg_interr signal to the epc and the h2e_msg_busy bit of the msg_status register. reading the h2e_msg_addr register from the primary cab address will reset the h2e_msg_interr signal to the epc. reading the h2e_msg_addr fr om the alternate cab address will reset the h2e_msg_busy bit of the msg_status register (see 10.8.23 message status (msg_status) register on page 404). cab view plb view cab view plb view access type primary read alternate read plb read/write base address primary x?3801 1000? (additional actions occur when reading this register using this address. see register description for details.) alternate x?3802 0020? (additional actions occur when reading this register using this address. see register description for details.) plb x?7801 00a8? h2e_msg_addr 313029282726252423222120191817161514131211109876543210 h2e_msg_addr 012345678910111213141516171819202122232425262728293031 field name bit(s) reset description h2e_msg_addr 31:0 x?0000 0000? pci host to epc message address - indicates a message?s powerpc dram starting address. field name bit(s) reset description h2e_msg_addr 0:31 x?0000 0000? pci host to epc message address - indicates a message?s powerpc dram starting address. ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 403 of 539 10.8.22 pci host to epc doorbell (h2e_doorbell) register the pci host processor accesses the pci host to epc doorbell register from the plb while the epc accesses this register from the cab interface. the pci host processor uses this register to signal interrupts to the epc. the pci host processor has read and sum write access to this register. the data contains the mask used to access this register. when any of this regist er?s bits are set to ?1?, an interrupt signal of the epc is activated. this register is read by the epc to determine which of the doorbells have been activated. the epc has read and rum write access to this register using a cab address value. cab view plb view cab view access type cab read/reset under mask write plb read/set under mask write base address cab x?3801 2000? plb x?7801 00b0? h2e_doorbells h2e_msg_doorbell 31 h2e_msg_doorbell 30 h2e_msg_doorbell 29 h2e_msg_doorbell 28 h2e_msg_doorbell 27 h2e_msg_doorbell 26 h2e_msg_doorbell 25 h2e_msg_doorbell 24 h2e_msg_doorbell 23 h2e_msg_doorbell 22 h2e_msg_doorbell 21 h2e_msg_doorbell 20 h2e_msg_doorbell 19 h2e_msg_doorbell 18 h2e_msg_doorbell 17 h2e_msg_doorbell 16 h2e_msg_doorbell 15 h2e_msg_doorbell 14 h2e_msg_doorbell 13 h2e_msg_doorbell 12 h2e_msg_doorbell 11 h2e_msg_doorbell 10 h2e_msg_doorbell 9 h2e_msg_doorbell 8 h2e_msg_doorbell 7 h2e_msg_doorbell 6 h2e_msg_doorbell 5 h2e_msg_doorbell 4 h2e_msg_doorbell 3 h2e_msg_doorbell 2 h2e_msg_doorbell 1 h2e_msg_doorbell 0 313029282726252423222120191817161514131211109876543210 h2e_doorbells h2e_msg_doorbell 31 h2e_msg_doorbell 30 h2e_msg_doorbell 29 h2e_msg_doorbell 28 h2e_msg_doorbell 27 h2e_msg_doorbell 26 h2e_msg_doorbell 25 h2e_msg_doorbell 24 h2e_msg_doorbell 23 h2e_msg_doorbell 22 h2e_msg_doorbell 21 h2e_msg_doorbell 20 h2e_msg_doorbell 19 h2e_msg_doorbell 18 h2e_msg_doorbell 17 h2e_msg_doorbell 16 h2e_msg_doorbell 15 h2e_msg_doorbell 14 h2e_msg_doorbell 13 h2e_msg_doorbell 12 h2e_msg_doorbell 11 h2e_msg_doorbell 10 h2e_msg_doorbell 9 h2e_msg_doorbell 8 h2e_msg_doorbell 7 h2e_msg_doorbell 6 h2e_msg_doorbell 5 h2e_msg_doorbell 4 h2e_msg_doorbell 3 h2e_msg_doorbell 2 h2e_msg_doorbell 1 h2e_msg_doorbell 0 012345678910111213141516171819202122232425262728293031 field name bit reset description h2e_msg_doorbell 31 31 0 pci host to epc doorbell - indicate s which of the 32 possible doorbells have been activated. 0 not activated 1 activated h2e_msg_doorbell 30:1 30:1 0 for all h2e_msg_doorbell 0 0 0 ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 404 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 plb view 10.8.23 message status (msg_status) register the message status register provides status inform ation associated with inter-processor messaging. this read only register is accessible from either the plb or the cab for the purpose of checking status associated with messaging. cab view plb view field name plb bit reset description h2e_msg_doorbell 31 0 0 pci host to epc doorbell - indicates wh ich of the 32 possible doorbells is activated. 0 not activated 1 activated h2e_msg_doorbell 30:1 1:30 0 for all h2e_msg_doorbell 0 31 0 access type cab read plb read base address cab x?3801 4000? plb x?7801 00a0? reserved p2h_bufr_valid h2p_msg_busy e2p_bufr_valid p2e_msg_busy e2h_bufr_valid h2e_msg_busy 313029282726252423222120191817161514131211109876543210 reserved p2h_bufr_valid h2p_msg_busy e2p_bufr_valid p2e_msg_busy e2h_bufr_valid h2e_msg_busy 012345678910111213141516171819202122232425262728293031 ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 405 of 539 cab view plb view field name cab bit(s) reset description reserved 31:6 reserved p2h_bufr_valid 5 0 powerpc subsystem to pci host message buffer valid indicator. 0 buffer not valid 1 buffer valid h2p_msg_busy 4 0 pci host to powerpc subsystem message busy indicator. 0 not busy processing h2p message 1 busy processing h2p message e2p_bufr_valid 3 0 epc to powerpc subsystem message buffer valid indicator. 0 buffer not valid 1 buffer valid p2e_msg_busy 2 0 powerpc to epc subsyste m message busy indicator. 0 not busy processing p2e message 1 busy processing p2e message e2h_bufr_valid 1 0 epc to pci host message buffer valid indicator. 0 buffer not valid 1 buffer valid h2e_msg_busy 0 0 pci host to epc message busy indicator. 0 not busy processing h2e message 1 busy processing h2e message field name bit(s) reset description reserved 0:25 reserved p2h_bufr_valid 26 0 powerpc subsystem to pci host message buffer valid indicator. 0 buffer not valid 1 buffer valid h2p_msg_busy 27 0 pci host to powerpc subsystem message busy indicator. 0 not busy processing h2p message 1 busy processing h2p message e2p_bufr_valid 28 0 epc to powerpc subsystem message buffer valid indicator. 0 buffer not valid 1 buffer valid p2e_msg_busy 29 0 powerpc subsystem to epc message busy indicator. 0 not busy processing p2e message 1 busy processing p2e message e2h_bufr_valid 30 0 epc to pci host message buffer valid indicator. 0 buffer not valid 1 buffer valid h2e_msg_busy 31 0 pci host to epc message busy indicator. 0 not busy processing h2e message 1 busy processing h2e message ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 406 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 10.8.24 powerpc boot redirection instruction registers (boot_redir_inst) in system implementation s in which the embedded powerpc sub system boots from the d6 dram, the mailbox and dram interface macro performs powerpc boot address redirection. under these conditions, the hardware provides instructions that redirect the boot sequence to a location in the powerpc dram. storage for eight instructions is provided by the boot_redir_inst registers. the powerpc boot redirection instruction (boot_redir_inst) registers are accessed from the cab interface. these registers provide capacity fo r eight instructions for plb addresses x?ffff ffe0? - x?ffff fffc? these instructions redirect the po werpc subsystem to boot from a lo cation in the powerpc dram and are configured before the ppc_reset is cleared. access type read/write base address x?3800 0110? - x?3800 0117? boot_redir_inst 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description boot_redir_inst 31:0 x?0000 0000? powerpc boot redirection instruction address values contains instructions used by the powerpc subsystem to r edirect the boot sequence to a loca- tion in d6 dram. offset corresponding powerpc instruction address 0 x?ffff ffe0? 1 x?ffff ffe4? 2 x?ffff ffe8? 3 x?ffff ffec? 4 x?ffff fff0? 5 x?ffff fff4? 6 x?ffff fff8? 7 x?ffff fffc? ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 407 of 539 10.8.25 powerpc machine check (pwrpc_mach_chk) register this register is accessible on the cab and indicates t he status of the machine check output of the powerpc processor core. 10.8.26 parity error status and reporting when reading the powerpc subsystem memory, any parity errors encountered are recorded and actions are taken. powerpc subsystem memory parity errors are indicated for each double word returned on the plb regardless of the object size read. for this reason, pari ty must be initialized for ev ery double word in each memory region used. furthermore, for powerpc processor code regions, correct parity must be initialized for each cache line in the region. parity will be set correctly when the memory is written. th erefore, for code regions, this parity initialization is accomplished automa tically when the code is loade d. likewise, this initial- ization is performed if a diagnostic is performed on the memory that writes to every location. in all other cases, this parity initialization must be performed for each region of memory used prior to use. since even bytes and odd bytes of the powerpc subsystem memory are stored in physically distinct mod- ules, error statistics are collected on an odd and even byte basis. this information may prove useful in isola- tion of a failing part. the wo rd address value of the mo st recent parity error is stored in the slave error address register (sear). in addition , bits of the slave error status register (sesr) indicate which plb masters have experienced parity errors in reading th e powerpc subsystem memory. this status information is indicated by odd and even byte for each of the three plb masters (instruction cache unit, data cache unit, and pci/plb macro). bits of the sesr are used to generate an interrupt input to the ui c. if any of thes e bits are set to b?1? then the parity error interrupt input to the uic is set to b?1?. when the uic is configured to enable this interrupt input, an interrupt signal is generated to the ppc405 core for processing. as a part of the interrupt service routine, the sesr must be read to clear the source of the interrupt. access type read base address (cab) x?3800 0210? reserved mach_chk 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description reserved 31:1 reserved mach_chk 0 0 powerpc machine check indication. 0 no machine check has occurred 1 a machine check has occurred ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 408 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 10.8.27 slave error address register (sear) the slave error address register records the word address value of the last occurrence of a parity error encountered by the dram interface sl ave unit. this address value will isolat e the location of the parity error to within a word. access type read base address (plb) x?7801 00b8? error address 012345678910111213141516171819202122232425262728293031 field name bit(s) reset description error address 0:31 x?0000 0000? last plb word address value that resulted in a parity error when using the dram interface slave unit. ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 409 of 539 10.8.28 slave error stat us register (sesr) the slave error status register contains status info rmation that indicates which masters have encountered parity errors in reading from the dram and whether these errors occurred in a byte with an even (perr_byte0) or an odd (perr_byte1) address value. the powerpc subsystem has three plb masters: the instruction cache unit (icu), the data cache unit (dcu), and the pci macro. the contents of this register are reset to x?0000 0000? when read. access type read and reset base address (plb) x?7801 00c0? icu_error_status dcu_error_status pci_error_status reserved perr_byte0 perr_byte1 reserved perr_byte0 perr_byte1 reserved perr_byte0 perr_byte1 reserved 012345678910111213141516171819202122232425262728293031 field name bit(s) reset description reserved 0:5 reserved perr_byte0 6 0 byte 0 parity error indication - whether or not the instruction cache unit plb master encountered a parity error since the register was last read. 0 no parity error encountered 1 parity error encountered perr_byte1 7 0 byte 1 parity error indication - whether or not the instruction cache unit plb master encountered a parity error since the register was last read. 0 no parity error encountered 1 parity error encountered reserved 8:13 reserved perr_byte0 14 0 byte 0 parity error indication - whether or not the data cache unit plb master encountered a parity error si nce the register was last read. 0 no parity error encountered 1 parity error encountered perr_byte1 15 0 byte 1 parity error indication - whether or not the data cache unit plb master encountered a parity error si nce the register was last read. 0 no parity error encountered 1 parity error encountered reserved 16:21 reserved perr_byte0 22 0 byte 0 parity error indication - whether or not the pci macro plb master encountered a parity error since the register was last read. 0 no parity error encountered 1 parity error encountered perr_byte1 23 0 byte 1 parity error indication - whether or not the pci macro plb master encountered a parity error since the register was last read. 0 no parity error encountered 1 parity error encountered reserved 24:31 reserved ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 410 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 10.8.29 parity error counter (perr_count) register the parity error counter register contains two 16-bit counter values. these counters accumulate the total number of parity errors for even and odd byte addresses since the last time the chip was reset. these counters roll over to zero when their maximum value is reached (65535). access type read base address (plb) x?7801 00c8? byte0_perr_count byte1_perr_count 012345678910111213141516171819202122232425262728293031 field name bit(s) reset description byte0_perr_count 0:15 x?0000? count of byte 0 parity errors encountered when reading dram from dram interface slave unit. byte1_perr_count 16:31 x?0000? count of byte 1parity errors encountered when reading dram from dram interface slave unit. ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 411 of 539 10.9 system start-up and initialization 10.9.1 np2g resets a general reset is performed whenever the np2g?s reset input pin is activated. a general reset includes the powerpc core, and the np2g network function reset domains. the powerpc core and the np2g network function reset domains are also controlled by separate configuration registers, powerpc_reset and soft_reset, respectively. each of these registers are accessible via the np2g?s cab interface. a general reset sets the powerpc_reset to ?1 ? (activated), but the soft_reset will be set to ?0? (deactivated). when the general reset is deactivated, the powerpc core remains in reset and the powerpc macros and the np2g network function are in an idle condition with state machines active and control structures un-initial- ized. the np2g network function w ill be functional once epc picocode has been loaded and control struc- tures are initialized. the epc is activated automatically when loading boot picocode from the spm interface or by setting the bd_override bit to ?1? in the boot override register (see 13.14.4 boot override register (boot_override) on page 463). the powerpc core is activated by clearing the bit of the powerpc_reset register. the powerpc core and the np2g network function domains are separately reset and activated by setting and clearing their respective reset registers. setting the control bit in the soft_reset register causes the network function to be momentarily reset while the powerpc subsystem is held in reset. the powerpc_reset is also activated wh enever the watch dog timer of the powerpc core expires for a second time and watch dog reset enable (wd_reset_ena) is set to ?1?. when enabled, the second expiration of the watch dog timer results in a pulse on the serr# signal of the pci bus. the tcr [wrc] of the powerpc core is set to ?10? to generate a chip reset request on the second expiration of the watch dog timer. the powerpc core can be reset from the riscwatch debugger environment. a core reset performed from riscwatch resets the ppc405 core, but does not set the powerpc_reset control register. this allows a momentary reset of the powerpc core and does not require a release of the powerpc core by clearing the powerpc_reset control regist er. the powerpc core is also reset and the powerpc_reset control register is set when a ?chip reset? command is performed from riscwatch and the watch dog reset enable is set to ?1?. this resets the powerpc core and holds it in reset until the powerpc_reset register is cleared. table 10-10. reset domains reset domain applies powerpc core applies only to the ppc405 proc essor core and is used to control it s start-up during system initialization network function applies to all other functions in the np2g ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 412 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 10.9.2 systems initialized by external pci host processors system implementations with control function centralized in a pci host processor are initialized primarily by an external pci host processor. these systems do not use the spm interface or its associated flash memory to boot the epc. the host processor (boot_ppc = '0') loads code for the powerpc processor and the epc picoprocessor. the general sequence of the start-up and initialization is as follows: 1. the host processor boots and performs board level configuration and testing while holding np2g sub- systems in reset. 2. the host processor releases the np2g?s reset signal. 3. release of the general reset input pin of the np2g activates its state machines. the np2g is in an idle state with un-initialized structures and the ppc405 core remains in reset and host pci configuration is enabled. 4. the host system uses the pci configuration protocol to configure internal registers of the pci interface macro. this configuration sets the base address values of the pci target maps. the pci master maps are disabled. 5. the host processor uses the appropriate pci target address values to configure and initialize the np2g?s dram controllers via the cab interface. 6. the host processor uses the appropriate pci target address values to load the powerpc code into one of the np2g?s drams. this code includes the branch code loaded into the boot_redir_inst registers. 7. the host loads the epc instruction memory. this memory is accessible via the cab interface macro. the addresses of the registers contro lling this interface were mapped to pci addresses in step 4. 8. the host processor starts the ppc405 core by clearing the powerpc_reset configuration register. this register is accessed via the cab interface. the powerpc subsystem starts by fetching the instruction at plb address x?ffff fffc?. this address is decoded by hardware to provide an unconditional branch to instruction space in the powerpc dram memory. 9. the host processor uses the cab interface to set the bd _override bit to ?1? in the boot override register (see 13.14.4 boot override register (boot_override) on page 463) to start the epc code. this code controls the initialization of the np2g structures in pre paration for network traffic. alternatively, this initial- ization is performed by the host processor via the cab interface. 10. communication ports are configured and enabled by either the host processor or the ppc405 core. ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 413 of 539 10.9.3 systems with pci host processors and initialized by powerpc subsystem the powerpc subsystem primarily controls start-up and initialization sequen ces of systems of this category. these systems do not use the spm interface or its associated flash memory for booting the epc boot pico- code (boot_picocode = '1'). the powerpc subsystem boots from pci address space (boot_ppc = '1') and loads code for the powerpc processor and the epc picoprocessors. the general sequence of the start-up and initialization is as follows: 1. the host processor boots and performs board level configuration and testing while holding np2g sub- systems in reset. 2. the host processor releases the np2g?s reset signal. 3. release of the general reset input pin of the np2g activates its state machines. the np2g is in an idle state with un-initialized structures and the ppc405 core remains in reset and host pci configuration is enabled. 4. the host system uses the pci configuration protocol to configure internal registers of the pci interface macro. this configuration sets the base address va lues of the pci target maps. the pci master maps are disabled except for the pmm0 which maps plb addresses x?fffe 0000? through x?ffff ffff? to the same addresses in pci address space. 5. the host processor starts the ppc405 core by clearing the powerpc_reset configuration register. this register is accessed via the cab interface. 6. the ppc405 core will boot from code residing in the pci add ress space starting at address x?ffff fffc?. 7. the ppc405 core processor configures and initializes the np2g?s dram controllers via the cab inter- face. 8. the ppc405 core processor loads the powerpc code, via the dram interface macro, into one of the np2g?s drams. 9. the ppc405 core processor loads the picocode for the epc via the cab interface. 10. using the cab interface, the host processor sets the bd_override bit to ?1? in the boot override register (see 13.14.4 boot override register (boot_override) on page 463) to start the epc picocode. this pico- code will control the initialization of the np2g structures in preparation for network traffic. alternatively, this initialization is performed by the pp c405 core processor via the cab interface. 11. communication ports are configured and enabled by the ppc405 core. ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 414 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 10.9.4 systems without pci host processors and initialized by powerpc subsystem the epc initially controls start-up an d initialization sequences of systems of this category, but they are prima- rily controlled by the powerpc subsystem. these syst ems use the spm interface and its associated flash memory for booting the epc picocode (boot_picocode = '0'). the powerpc subsystem boots from pci address space (boot_ppc = '1') and loads code for the powerpc processor and the epc picoprocessor. the general sequence of the start-up and initialization is as follows: 1. release of the general reset input pin of the np2g activates its state machines. the pci master maps are disabled except for the pmm0 which maps plb addresses x?fffe 0000? through x?ffff ffff? to the same addresses in pci address space. epc boot picoc ode is loaded from the flash memory via the spm interface. the spm interface automatically starts the epc and the ppc405 core remains in reset. 2. epc code executes diagnostic and initialization code which includes the initialization of the np2g?s dram controllers. 3. the epc starts the ppc405 core by clearing the powerpc_reset configuration register. this register is accessed via the cab interface. 4. the ppc405 core will boot from code residing in the pci add ress space starting at address x?ffff fffc?. 5. the ppc405 core processor loads the powerpc code via the dram interface macro into one of the np2g?s drams. 6. communication ports are configured and enabled by the ppc405 core. ibm powernp np2g preliminary network processor np2_ds_sec10_eppc.fm.01 february 12, 2003 embedded powerpc? subsystem page 415 of 539 10.9.5 systems without pci host or delayed pci configuration and initialized by epc the epc controls start-up and init ialization sequences of systems of this category. th ese systems use the spm interface and its associated flash memory for boot ing the epc picocode (boot_picocode = '0'). code for the powerpc subsystem and the epc are loaded by the spm interface and the epc (boot_ppc = '0'). code for the powerpc subsystem exists in the flash memory or is provided using guided traffic. the general sequence of the start-up and initialization is as follows: 1. release of the general reset input pin of the np2g activates its state machines. epc picocode is loaded from the flash memory via the spm interface. the spm interface automatically starts the epc. the ppc405 core remains in reset and pc i host configurat ion is disabled. 2. epc code executes diagnostic and initialization co de, which includes the init ialization of the np2g?s dram controllers. 3. the epc loads the code for the powerpc processor from the flash memory into the dram. this code includes the branch code loaded into the boot_redir_i nst registers. alternatively, this code is loaded using guided traffic. guided traffic flows once the communications port connecting the source has been enabled (see step 6). 4. the epc starts the ppc405 core by clearing the powerpc_reset configuration register. this register is accessed via the cab interface. 5. the ppc405 core will boot from code residing in the plb address space starting at address x?ffff fffc?. this address is decoded by hardware to provide an unconditional branch to instruction space in the powerpc dram memory. 6. if desired, the ppc405 core can change the contents of the pci configuration header registers and enable pci host configuration. 7. communication ports are configured and enabled by the ppc405 core or, alternatively, by the epc. ibm powernp np2g network processor preliminary embedded powerpc? subsystem page 416 of 539 np2_ds_sec10_eppc.fm.01 february 12, 2003 ibm powernp np2g preliminary network processor np2_ds_sec11_reset.fm.01 february 12, 2003 reset and initialization page 417 of 539 11. reset and initialization this section provides, by example, a method for initializ ing the np2g. it is not intended to be exhaustive in scope, since there are many configurations and enviro nments where the np2g may be applied. the external serial parallel manager (spm) field programmable gate array (fpga) mentioned in this chapter is a component of the network processor evaluation kit and is not sold separately. 11.1 overview the np2g supports a variety of system and adapter configurations. in order to support a particular environ- ment, the network processor must be initialized with parameters that match that environment?s system or adapter requirements. the sequence of reset and initialization is shown in table 11-1 . some system environments do not require all of the steps and some require that certain steps be performed differently. the np2g supports the system environments shown in figure 11-1 on page 418 for reset and initialization. table 11-1. reset and initialization sequence step action notes 1 set i/os device i/os set to match adapter requirements 2 reset must be held in reset for minimum of 1 s 3 boot several boot options 4 setup 1 low level hardware setup 5 diagnostics 1 memory and register diagnostics 6 setup 2 basic hardware setup 7 hardware initialization hardware self-i nitialization of various data structures 8 diagnostics 2 dat a flow diagnostics 9 operational everything ready for first guided frame 10 configure functional configuration 11 initialization complete everything ready for first data frame ibm powernp np2g network processor preliminary reset and initialization page 418 of 539 np2_ds_sec11_reset.fm.01 february 12, 2003 the following sections describe each step in the reset and initialization sequence and the various ways to accomplish each step. figure 11-1. system environments spm eeprom cabwatch host * external spm fpga * external eeprom * optional cabwatch spm cabwatch spm cabwatch * external spm fpga * external eeprom * optional cabwatch * external pci eeprom for powerpc * optional spm fpga * optional eeprom * optional cabwatch * optional pci eeprom for powerpc * external pci host pci pci ibm powernp ibm powernp ibm powernp eeprom eeprom eeprom eeprom np2g np2g np2g ibm powernp np2g preliminary network processor np2_ds_sec11_reset.fm.01 february 12, 2003 reset and initialization page 419 of 539 11.2 step 1: set i/os several np2g i/os must be set to appr opriate values to operate correctly. most of these i/os will be set to a fixed value at the card level, but some will be set to the appropriate va lue based on system parameters. the following table lists all configurable i/os that must be set pr ior to initial reset. additional configuration bits could be utilized by defining additional i/o on an external spm fpga as configu- ration inputs. if the user defines registers in the spm cab address space and a corresponding external spm fpga design, the np2g can read these spm i/os and ma ke configuration adjustments based on their values (for example, the type of cp interface might be 100 mb or 1 gb). custom boot picocode is required to take advantage of these additional features. all clocks must be operating prior to issuing a re set to the np2g. the clock_core and the iew clock drive internal plls that mu st lock before the in ternal clock logic will release the operational signal. the clock125 and dmu_*(3) inputs, if applicable, should also be operating in order to properly reset the dmu interfaces. the pci clock (pci_clk) must be operating in order to properly reset the pci interface. table 11-2. set i/os checklist i/o values notes testmode(1:0) see table 2-31: miscellaneous pins on page 75 for the encoding of these i/o. adapter may require mechanism to set test mode i/os in order to force various test scenarios. boot_picocode see table 2-31: miscellaneous pins on page 75 for the encoding of this i/o. controls which interface loads the internal epc instruction memory and boots the guided frame handler thread. boot_ppc see table 2-31: miscellaneous pins on page 75 for the encoding of this i/o. controls from where the internal ppc fetches its initial boot code. pci_speed see table 2-27: pci pins on page 71 for the encoding of this i/o. controls the speed of the pci bus. cpdetect_a see table 2-16: pmm interface pin multi- plexing on page 57 for the encoding of this i/o. used to find a locally attached control point function (cpf). cpdetect_c see table 2-16: pmm interface pin multi- plexing on page 57 for the encoding of this i/o. used to find a locally attached cpf. cpdetect_d see table 2-16: pmm interface pin multi- plexing on page 57 for the encoding of this i/o. used to find a locally attached cpf. spare_tst_rcvr(9:0) see table 2-31: miscellaneous pins on page 75 for the correct tie values for these i/o. used during manufacturing testing. ibm powernp np2g network processor preliminary reset and initialization page 420 of 539 np2_ds_sec11_reset.fm.01 february 12, 2003 11.3 step 2: reset the np2g once all configuration i/os are set and the clocks are running, the np2g can be reset using the reset signal. this signal must be held active for a minimum of 1 s and then returned to its inactive state. internal logic requires an additional 101 s to allow the plls to lock and all internal logic to be reset. at this point, the np2g is ready to be booted. in addition to the reset signal, the np2g supports two other ?soft? reset mecha- nisms: the soft_reset register allows the entire np2g to be reset (just like a reset ), and the powerpc_reset register allows the powerpc core to be reset. a reset or soft_reset causes the powerpc_reset register to activate and hold the powerp c core in reset until this re gister is cleared. there- fore, a reset resets the entire np2g and holds the powerpc co re in reset until it is released by the epc or an external host using the pci bus. ibm powernp np2g preliminary network processor np2_ds_sec11_reset.fm.01 february 12, 2003 reset and initialization page 421 of 539 11.4 step 3: boot 11.4.1 boot the embedded processor complex (epc) booting the np2g's epc involves loading the internal picocode instruction space and turning over control of execution to the gfh thread. the gfh thread executes the loaded picocode and completes the appropriate steps in the bringup process. the np2g supports four ways to load the internal picocode instruction space: through the spm interface logic, through the pci bus from an external host, through the embedded powerpc, or through cabwatch. when using the last three methods, once the picocode instruction space is loaded, the bd_override bit must be set to ?1? in the boot override register (see 13.14.4 boot override register (boot_override) on page 463), which causes the gfh thread to start the code stored at address '0'. 11.4.2 boot the powerpc there are two steps in the process of booting the np2g 's embedded powerpc. first, using the boot_ppc i/ o, the powerpc support logic must be configured to boot the powerpc from either the external d6 dram or the pci bus. second, the powerpc must be released to execute the appropriate boot code. the powerpc boot code can be mapped either into pci address space or into the np2g's external d6 dram, depending on the setting of the boot_ppc i/o. if an external host processor is used on the pci bus, it should use the pci configuration protocol to set the np2g's pci target maps for access into the network processor's internal address space. if the boot_ppc i/o chooses the pci bus, the internal plb bus addresses x'fffe 0000' through x'ffff ffff' are mapped to pci address space. once the powerpc_reset register is cleared (by either the epc or by an external host acro ss the pci bus), the powerpc will fetc h and execute the boot code from across the pci bus. if the boot_ppc i/o chooses the external d6 dram, the d6 dram must be written with the appropriate boot code and the boot_redir_inst registers must be written to point to the code in the d6 dram before the powerpc_reset register is released. the internal logic maps the powerpc's boot addresses of x'ffff ffe0' through x'ffff fffc' to the boot_redir_ins t registers and the remaining boot code is fetched from the external d6 dram. the d6 dram and the boot_redir_inst registers can be written by either the epc or an external host on the pci bus. when ev erything is set up, use a cab write to clear the powerpc_reset register to allow the powerpc core to execute the boot code. 11.4.3 boot summary the epc must be booted by first loading its picocode instructions (by either the spm, an external pci host, the embedded powerpc, or cabwatch) and then issuing the boot done signal (by the picocode loader). if the embedded powerpc is to be used, it must have its instruction space loaded (if d6 is used), then pointing the boot logic to the appropriate boot location (pci or d6), and finally releasing the powerpc_reset register (by either the epc, an external pci host, or cabwat ch). once one or both system s are booted, the following steps can be performed by one or both processing co mplexes. (some accesses to external memories can only be performed by the epc complex.) ibm powernp np2g network processor preliminary reset and initialization page 422 of 539 np2_ds_sec11_reset.fm.01 february 12, 2003 11.5 step 4: setup 1 setup 1 is needed to set some low level hardware functions that enable the np2g to interface with its external drams and to configure some internal registers that enable the execution of step 5: diagnostics 1. setup 1 should configure or check the following registers according to the system setup and usage: table 11-3. setup 1 checklist register fields notes memory configuration register all t his register is set to match t he populated external memories. dram parameter register all this r egister is set to match the ex ternal dram's characteristics. thread enable register all this register enables the non-gfh threads. the gfh is always enabled. initialization register dram cntl start t his bit starts the dram interfaces. initialization done register cm init done e_ds init done thes e bits indicate that the dram initialization has completed. ibm powernp np2g preliminary network processor np2_ds_sec11_reset.fm.01 february 12, 2003 reset and initialization page 423 of 539 11.6 step 5: diagnostics 1 diagnostics 1 tests internal registers, internal memori es, and external memories as required by the diagnos- tics program (read and write tests). this step comes before the hardware initialization step because several of these structures will be initialized by the hardware to contain function al data structures. by testing these structures first, the diagnostics program does not need to be concerned with corrupting the contents of these locations during hardware initialization. care must be taken that the values written to the structures do not force an undesirable situation (such as soft resetting the device). however, most of these structures can be tested by the diagnostics program to ensure proper operation. table 11-4 lists some of the structures that could be tested by this step. table 11-4. diagnostics 1 checklist structure test notes phase locked loop fail verify all plls locked if any pll fails, any further operation is questionable. dppu processors alu, scratch memory, internal processor registers test each thread. ingress data store read/write egress data store read/write control stores d0, d2, d3, d4 read/write control store d6 read/write coordi nated with powerpc code loading control store h0-h1 read/write counter definition table configure set up to test counters. counter memory read/write/add policy manager memory read/write egress qcbs read/write egress rcb read/write egress target port queues read/write mcca read/write pmm rx/tx counters read/write pmm sa tables read/write ingress bcb read/write ingress fcb read/write not all fields are testable. cia memory read/write ingress flow control pr obability memory read/write egress flow control probability memory read/write various internal configur ation registers read/write not all fields will be testable. care must be taken when chang- ing certain control bits. ibm powernp np2g network processor preliminary reset and initialization page 424 of 539 np2_ds_sec11_reset.fm.01 february 12, 2003 11.7 step 6: setup 2 setup 2 is needed to set up the hardware for self-initialization and to configure the hardware structures for operational state. these configuration registers must be set to the desirable values based on the system design and usage: table 11-5. setup 2 checklist register fields notes master grant mode all toggle mode bci mode all egress reassembly sequence check all aborted frame reassembly action control all packing control all ingress bcb_fq thresholds all egress sdm stack threshold all free queue extended stack maximum size all egress fq thresholds all fcb free queue size register (fcb_fq_max) all dmu configuration all dmu configuration can be postponed until step 10: configure if dmu init start is also postp oned. dmu for cpf must be done dur- ing setup 2. if the dmu is conf igured, the appropriate external physical devices must also be configured. note that external physical devices should be held in reset until the dmu configura- tion is completed. packet over sonet control all pos configuration can be postponed until step 10: configure if dmu init start is also postponed. ethernet encapsulation type for control all ethernet encapsulation type for data all iew all ibm powernp np2g preliminary network processor np2_ds_sec11_reset.fm.01 february 12, 2003 reset and initialization page 425 of 539 11.8 step 7: hardware initialization hardware initializat ion allows the np2g to self-i nitialize several internal stru ctures, thereby decreasing the overall time required to prepa re the processor for operation. several in ternal structures will be initialized with free lists, default values, or initial states in order to accept the first guided frames from the cpf. once these data structures are initialized, the picocode should not modify them with further read/write diagnostics. to initiate the hardware self-initialization, the registers shown in table 11-6 need to be written. 11.9 step 8: diagnostics 2 diagnostics 2 determines if the np2g is ready for operation and allows testing of data flow paths. the items listed in table 11-7 should be set up, checked, and/or tested. table 11-6. hardware initialization checklist register fields notes iew init all only start the iew initialization after the iew has been config- ured. initialization dmu set only start each dmu after its associated dmu configuration has been set. initialization functional is land starts all other isla nds? self-initialization. table 11-7. diagnostic 2 checklist register fields notes initialization done all started in hardware initialization step the code polls this register until a timeout occurs or all expected bits are set. iew timeout = 20 ms e_eds timeout = 15 ms iew initialization mode set the mode to operational. lu def table read/write test these structures c an only be tested after hardware initialization. smt compare table read/write test these structures can only be tested after hardware initialization. tree search free queues read/write test these structures can only be tested after hardware initialization. not all fields are testable. port configuration table all set to default values for diagnostics 2. lu def table all set to def ault values for diagnostics 2. ingress target port data storage map all set to default values for diagnostics 2. target port data storage map all set to default values for diagnostics 2. build frame on egress side lease twins and st ore test frame in egress data store. half wrap wrap test frame from eg ress to ingress using wrap dmu. full wrap wrap ingress frame back to the egress side. external wrap if external physical devices are configured, full external wraps can be performed. tree searches to test the tree search logic, tree searches can be performed on a pre-built sample tree written to memory. ibm powernp np2g network processor preliminary reset and initialization page 426 of 539 np2_ds_sec11_reset.fm.01 february 12, 2003 11.10 step 9: operational after the diagnostics 2 tests have finished, any previous ly written default values may need to be updated to allow this step to proceed. if all diagnostics have passed, the operational signal can be activated to indicate to an external cpf that the np2g is ready to receive guided frames. this signal is activated by writing the np2g ready register which then activates the operational i/o. if some portion of the diagnostics have not passed, the ready register should not be written. this causes the cpf to timeout and realize the diagnostic failure. to determine what portion of the diagnostics have failed, the system designer must make provisions at the board or system level to record the status in a location that is accessible by the cpf. one method is to provide an i 2 c interface to an external spm fpga which the cpf could access. 11.11 step 10: configure after the operational signal has been activated, the cp f can send guided frames to the np2g for functional configuration. items that can be configured include: table 11-8. configure checklist register fields notes dmu configuration all configure now if dmu configuration was postponed during setup 2 step. if the dmu is configured, the appropria te external physical devices also must be configured. note that extern al physical devices should be held in reset until the dmu configuration is completed. packet over sonet control all configure now if pos configuration was postponed during setup 2 step. functional picocode all functional picocode should be loaded into the instruction memory. port config table all functional values for the pct should be set. lu def table all functional values should be set. cia memory all functional values should be set. hardware classifier e_type all f unctional values should be set. hardware classifier sap all functional values should be set. hardware classifier ppp_type all functional values should be set. interrupt masks all functional values should be set. timer target all functional values should be set. interrupt target all functional values should be set. address bounds check control all f unctional values should be set. static table entries all any static table entries should be loaded. ingress target port data storage map all target port data storage map all egress qcbs all qd accuracy all sa address array all counter definition table all counters all any counters used by c ounter manager must be read/cleared. policy manager memory all set up initial values for policies. ibm powernp np2g preliminary network processor np2_ds_sec11_reset.fm.01 february 12, 2003 reset and initialization page 427 of 539 11.12 step 11: initi alization complete once steps 1 through 10 are complete and all items on the checklists have been configured, the np2g is ready for data traffic and the ports can be enabled. ibm powernp np2g network processor preliminary reset and initialization page 428 of 539 np2_ds_sec11_reset.fm.01 february 12, 2003 ibm powernp np2g preliminary network processor np2_ds_sec12_debug.fm.01 february 12, 2003 debug facilities page 429 of 539 12. debug facilities 12.1 debugging picoprocessors the np2g provides several mechanisms to fa cilitate debugging of the picoprocessors. 12.1.1 single step each thread of the np2g can be enabled individually for single step instruction execution. single step is defined as advancing the instruction address by one cycle and executing the instruction accordingly for enabled threads. coprocessors are not affected by single step mode. therefore, coprocessor operations that at ?live? speed would take several cycles may seem to take only one cycl e in single step mode. there are two ways to enable a thread for single step operation. the first is to write the single step enable register. this register is a single-step bit mask for each thread and can be accessed through the control access bus (cab). the second is the si ngle step exception register. this register is also a bit mask, one for each thread, but when set indicates which threads are to be placed into single step mode on a class3 inter- rupt . when a thread is in single step mode, the thread can only be advanced by writing the single step command register. 12.1.2 break points the np2g supports one instruction break point that is sh ared by all of the threads. when a thread?s instruc- tion address matches the break point address, a class3 level interrupt is generated. this causes all threads enabled in the single step exception register to enter single step mode. the break point address is config- ured in the break point address register. 12.1.3 cab accessible registers the scalar and array registers of the core language processor (clp) and of the dppu coprocessors are accessible through the cab for evaluation purposes. the clp?s general purpose registers, which are directly accessible with the clp, are mapped to read only scalar registers on the control access bus. ibm powernp np2g network processor preliminary debug facilities page 430 of 539 np2_ds_sec12_debug.fm.01 february 12, 2003 12.2 riscwatch the np2g supports riscwatch through the jtag interface. riscwatch is a hardware and software development tool for the embedded powerpc. it provides processor control and source-level debugging features, including: on-chip debugging via i eee 1149.1 (jtag) interface target monitor debugging open-source real-time operating system-aware debugging source-level and assembler debugging of c/c ++ executable files real-time trace support via the risctrace feature for the powerpc 400 series network support that enables customers to remotely debug the system s they are developing supports industry standard embedded abi for powerpc and xcoff abi command-file support for automated test and command sequences simple and reliable 16-pin interface to the system the customer is developing ethernet to target jtag interface hardware multiple hosts supported intuitive and easy-to-use windowed user interface for more information, go to http://www-3.ibm.com/chips/techlib/techlib.nsf/products/riscwatch_debugger . ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 431 of 539 13. configuration the ibm powernp ? np2g network processor must be configured after internal diagnostics have run. configuration is performed by a control point function (cpf) that generates guided traffic to write configura- tion registers. these configuration registers are reset by the hardware to a minimal option set. the following sections describe all configuration registers and their reset state. a base address and offset are provided. 13.1 memory configuration the np2g is supported by a number of memory subsystems as shown in figure 13-1 . these memory subsystems contain data buffers and controls used by the np2g. the d0, d2, d3, d4, ds_0, and ds_1 subsystems are required to operate the np2g base configuration. memory subsystems z0, z1, and d6 are optional and provide additi onal functionality or capa bility when added to the required set of memory subsystems. in its base configuration, the np2g does not perform enhanced scheduling, and has a limited look-up search capability. the enab ling of memory subsystem interfaces is controlled by the contents of the memory config- uration register (memory_config) (page 432). the bits in this register are set by hardware during reset to enable the base configuration. figure 13-1. np2g memory subsystems d4 np2g d6 z0 d0 d3 57 51 33 48 51 ds0 51 ds1 d2 33 51 z1 39 ibm powernp np2g network processor preliminary configuration page 432 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.1.1 memory configuration register (memory_config) the memory configuration register (memory_config) enables or disables memory interfaces. it also enables the egress scheduler and the z1 memory interface required by the egress scheduler to operate. access type read/write base address x?a000 0120? reserved crb_ifc_enable sch_ena z0 d4 d3 d2 reserved d0 reserved d6 ds_1 ds_0 313029282726252423222120191817161514131211109876543210 field name bits reset description reserved 31:13 reserved. crb_ifc_enable 12 0 when set to ?1?, enables the coprocessor response bus (crb) coprocessor external interface. the z0 memory subsystem interface enabled control (bit 9 of the memory configuration register (memory_config)) must also be set to ?1? to enable the cab interface. sch_ena 11:10 00 scheduler enabled control enables both egres s scheduler and z1 memory interface: 00 scheduler disabled, z1 interface disabled 01 scheduler enabled, z1 interface enabled 10 scheduler disabled, z1 interface enabled 11 reserved when enabling the scheduler, the target port queue count qcnt_pq must be zero for all ports. when setting this value to ?0?, t he target port queue count (qcnt_pq) + free queue (fq) must be zero for all ports. z0 9 0 z0 memory subsystem interface enabled control: 1 interface enabled 0 interface disabled d4 8 1 d4 memory subsystem interface enabled control: 1 interface enabled 0 interface disabled d3 7 1 d3 memory subsystem interface enabled control: 1 interface enabled 0 interface disabled d2 6 1 d2 memory subsystem interface enabled control: 1 interface enabled 0 interface disabled reserved 5 0 reserved. d0 4 1 d0 memory subsystem interface enabled control: 1 interface enabled 0 interface disabled reserved 3 0 reserved. d6 2 0 d6 memory subsystem interface enabled control: 1 interface enabled 0 interface disabled ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 433 of 539 ds_1 1 1 ds_1 memory subsystem interface enabled control: 1 interface enabled 0 interface disabled ds_0 0 1 ds_0 memory subsystem interface enabled control: 1 interface enabled 0 interface disabled field name bits reset description ibm powernp np2g network processor preliminary configuration page 434 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.1.2 dram parameter register (dram_parm) the dram parameter re gister (dram_parm) controls the operation of the dynamic random-access memory (dram) used by the embedded processor complex (epc) and the egress enqueuer/dequeuer/ scheduler (eds). each dram is controlled separately. base address offset 0 base address offset 1 base address offset 2 access type read/write base address x?a000 2400? epc_dram_parms eds_dram_parms strobe_cntl reserved cs_refresh_rate cs_bank_r_w_skip cas_ latency 8_bank_ena 11/10 drive_strength dll_disable dqs_clamping_ena dram_size fet_cntl_ena reserved d0_width ds_d4_refresh_rate ds_error_checking_disable d4_error_checking_disable cas_ latency 8_bank_ena 11/10 drive_strength dll_disable dqs_clamping_ena dram_size fet_cntl_ena 313029282726252423222120191817161514131211109876543210 epc_dram_parms d6_dram_parms reserved d6_refresh rate d6_bank_rw_skp cas_latency 11/10 drive_ strength dll_ disable dqs_ clamping_ ena d6_dram_size fet_cntl_ena d6_parity_mode 313029282726252423222120191817161514131211109876543210 reserved auto_precharge 313029282726252423222120191817161514131211109876543210 ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 435 of 539 base address offset 0 field name bits reset description strobe_cntl 31:30 00 strobe control for double data rate (ddr) dram interfaces: 00 each ddr dram interface uses one strobe (xx_dqs) for each byte of data lines. 01 d0, d2, d3 ddr dram interface use one strobe (xx_dqs) for each byte of data lines. ds0, ds1, and d4 ddr dram interface use one strobe (xx_dqs) for all data lines. 10 reserved. 11 reserved. reserved 29 reserved. cs_refresh_rate 28 1 cs_refresh_rate. controls the refresh rate for d0, d2, and d3: 0 double refresh rate (7.5 s) 1 normal refresh rate (15 s) cs_bank_rw_skp 27 0 controls the number of banks that must be skipped within a dram access window when switching from a read to a write: 0 skip 1 bank 1 skip 2 banks the proper setting for this bit is rela ted to the dram timing specifications and the cas_latency value. this control is for all control stores (d0, d2, d3, d6). cs_bank_rw_skp 27 0 this bit controls the number of bank s that must be skipped within a dram access window when switching from a read to a write: 0 skip 1 bank. cas_latency (bits 26:24) must be set to ?010? to support this option. 1 skip 2 banks. the proper setting for this bit is related to the times of the dram with respect to the cas_latency value. this control is for d0, d2, and d3 con- trol stores. cas_latency 26:24, 10:8 010 dram column address strobe (cas) latency value corresponds to the dram?s read latency measured from the column address. (ddr dram mode register, bits 6:4; see the dram documentation for more information.) 000 - 001 reserved 010 2 clock cycles (pc266a-compliant drams) 011 3 clock cycles 100 - 101 reserved 110 2.5 clock cycles (pc266b-compliant drams) 111 reserved 8_bank_enable 23, 7 0 eight bank addressing mode enable cont rol value. for proper operation, must be set to ?0?. 11/10 22, 6 1 ten- or eleven-cycle dram control value controls the number of core clock cycles the dram controller uses to define an access window: 0 10-cycle dram 1 11-cycle dram drive_strength 21, 5 0 dram drive strength control. (ddr dram extended mode register, bit 1, see the dram documentation for more information.) 0 strong 1 weak dll_disable 20, 4 0 delay-locked loop (dll) disable contro l. for proper operation, must be set to ?0?. (ddr dram extended mode register, bit 0, see the dram documentation for more information.) ibm powernp np2g network processor preliminary configuration page 436 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 dqs_clamping_ena 19, 3 0 data q strobe (dqs) clamping enabl e control. for proper operation, must be set to ?0?. dram_size 18:17 00 dram size indicates the size of the control stores d0-d3 in drams: 00 4x1mx16 ddr dram, burst = 4 01 4x2mx16 ddr dram, burst = 4 10 4x4mx16 ddr dram, burst = 4 11 reserved note: d0 can also be confi gured to be double-wide (x32). fet_cntl_ena 16, 0 0 field-effect transistor (fet) control enable control. for proper operation, must be set to ?0?. reserved 15 reserved. d0_width 14 1 d0 width control indicates if one or two drams are used for the d0 con- trol store (cs): 0 single-wide configuration using one dram. a single bank access provides 64 bits of data. 1 double-wide configuration usi ng two drams. a single bank access provides 128 bits of data. ds_d4_refresh_rate 13 0 refresh rate control for ds0, ds1 and d4: 0 normal refresh rate (15 s) 1 double refresh rate (7.5 s) ds_error_checking_disable 12 0 egress data store error checking disabl e control. when this field is set to ?1?, all dram error checking for t he egress data store is disabled. d4_error_checking_disable 11 0 d4 dram error checking disable. when this field is set to ?1?, all dram error checking for the d4 dram is disabled. dram_size 2:1 00 dram size indicates the size of th e egress data store (ds0, ds1) and d4 drams: 00 4 x 1 m x 16 ddr dram x 2 (or 4 x 1 m x 32 ddr dram x 1) 01 4 x 2 m x 16 ddr dram x 2 (or 4 x 2 m x 32 ddr dram x 1) 10 4 x 4 m x 16 ddr dram x 2 (or 4 x 4 m x 32 ddr dram x 1) 11 4 x 512 k x 32 ddr dram x 1 the setting of this field affects the size of the extended stack queues (see section 4.5 extended stack queues on page 323) as follows: gq 00 01 10 11 gtq 48 k 96 k 192 k 24 k gpq 48 k 96 k 192 k 24 k gfq 96 k 192 k 384 k 48 k gr0 96 k 192 k 384 k 48 k gr1 96 k 192 k 384 k 48 k gb0 96 k 192 k 384 k 48 k gb1 96 k 192 k 384 k 48 k discard 96 k 192 k 384 k 48 k field name bits reset description ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 437 of 539 base address offset 1 field name bit(s) reset description reserved 31:14 reserved. d6_refresh_rate 13 0 this field controls the refresh rate for d6: 0 normal refresh rate (15 s) 1 double refresh rate (7.5 s) d6_bank_rw_skp 12 0 this controls the number of banks that must be skipped within a dram access window when switching from a read to a write: 0 skip 1 bank. cas_latency (bits11:9) must be set to '010' to sup- port this option. 1 skip 2 banks. the proper setting for this is relat ed to the dram timing specifications and the cas_latency value. this control is for d6 only. cas_latency 11:9 010 dram column address strobe latency value corresponds to the dram?s read latency measured from the co lumn address. (ddr dram mode register, bits 6:4; see the dram documentation for more information.) 000 - 001 reserved 010 2 clock cycles (pc266a-compliant drams) 011 3 clock cycles 100 - 101 reserved 110 2.5 clock cycles (pc266b-compliant drams) 111 reserved 11/10 80 ten- or eleven-cycle dram control value controls the number of core clock cycles the dram controller uses to define an access window: 0 10-cycle dram 1 11-cycle dram drive_strength 7 0 dram drive strength control. (ddr dram extended mode register, bit 1, see the dram documentation for more information.) 0 strong 1 weak dll_disable 6 0 dll disable control. for proper operation, must be set to ?0?. (ddr dram extended mode register, bit 0, see the dram documentation for more information.) dqs_clamping_ena 5 0 dqs clamping enable control. for proper operation, must be set to ?0?. d6_dram_size 4:2 110 indicates the size of the d6 dram: 000 4x1mx16 001 4x2mx16 010 4x4mx16 011 reserved 100 4x4mx4 101 4x8mx4 110 4x16mx4 111 reserved fet_cntl_ena 1 0 fet control enable control. for proper operation, must be set to ?0?: d6_parity_mode 0 1 dram d6 parity mode disable control value: 0 d6 interface supports an additional two ddr drams which sup- port byte parity. the hardware generates on write and checks parity on read. 1 d6 interface does not support parity. ibm powernp np2g network processor preliminary configuration page 438 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 base address offset 2 field name bit(s) reset description reserved 31:8 reserved. auto_precharge 7:0 0 configures the address bit used to flag the auto precharge operation for the attached ddr dram. when set to ?0?, a10 is used. when set to ?1?, a8 is used. bit dram interface 7ds1 6ds0 5d6 4d4 3d3 2d2 0d0 ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 439 of 539 13.1.3 delay calibration registers these registers are used to modify the interface timing s for the ddr interfaces. these registers can be used to initialize the output multiplier fields in the following offsets to x?6a?. otherwise, these registers should be modified only when directed by an ibm field engineer. base address offset 0 (r/w) (d0, d2, d3, d4, d6, ds0, and ds1) access type base address offset 0 base address offset 2 base address offset 4 base address offset 6 base address offset 8 base address offset 10 base address offset 12 base address offset 15 read/write base address offset 1 base address offset 3 base address offset 5 base address offset 7 base address offset 9 base address offset 11 base address offset 13 read only base address d0_ddr_dcr x?a080 0010? d2_ddr_dcr x?a080 0040? d3_ddr_dcr x?a080 0080? d4_ddr_dcr x?a080 0100? d6_ddr_dcr x?a080 0200? ds0_ddr_dcr x?a080 0400? ds1_ddr_dcr x?a080 0800? reserved output override valid output override value output offset output multiplier 313029282726252423222120191817161514131211109876543210 ibm powernp np2g network processor preliminary configuration page 440 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 base address offset 1 (ro) (d0, d2, d3, d4, d6, ds0, and ds1) base address offset 2, n = 0 (r/w) (d0, d2, d3, d4, d6, ds0, ds1) base address offset 4, n = 1 (r/w) (d0, d2, d3, d4, d6, ds0, ds1) base address offset 6, n = 2 (r/w) (d0, d4, d6, ds0, ds1) base address offset 8, n = 3 (r/w) (d0, d4, d6, ds0, ds1) base address offset 3, n = 0 (ro) (d0, d2, d3, d4, d6, ds0, ds1) base address offset 5, n = 1 (ro) (d0, d2, d3, d4, d6, ds0, ds1) base address offset 7, n = 2 (ro) (d0, d4, d6, ds0, ds1) base address offset 9, n = 3 (ro) (d0, d4, d6, ds0, ds1) reserved calibration error output delay overrun raw delay 313029282726252423222120191817161514131211109876543210 reserved strobe n input override valid strobe n input override value strobe n input offset 313029282726252423222120191817161514131211109876543210 reserved strobe n input delay overrun strobe n input calculated delay 313029282726252423222120191817161514131211109876543210 ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 441 of 539 base address offset 10, n = 0 (r/w) (d6) base address offset 12, n = 1 (r/w) (d6) base address offset 11, n = 0 (ro) (d6) base address offset 13, n = 1 (ro) (d6) base address offset 15 (r/w) (d0, d2, d3, d4, d6, ds0, ds1) base address offset 0 (r/w) (d0, d2, d3, d4, d6, ds0, and ds1) reserved strobe par n input override valid strobe par n input override value strobe par n input offset 313029282726252423222120191817161514131211109876543210 reserved strobe par n input delay overrun strobe par n input calculated delay 313029282726252423222120191817161514131211109876543210 reserved common strobe input multiplier 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description reserved 31:25 reserved. output override valid 24 0 output override valid. output override value 23:16 0 output override value. output offset 15:8 0 output offset. output multiplier 7:0 x?35? output multiplier. prior to initializing the ddr drams, this field must be written to a value of x?6a?. ibm powernp np2g network processor preliminary configuration page 442 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 base address offset 1 (ro) (d0, d2, d3, d4, d6, ds0, and ds1) base address offset 2, n = 0 (r/w) (d0, d2, d3, d4, d6, ds0, ds1) base address offset 4, n = 1 (r/w) (d0, d2, d3, d4, d6, ds0, ds1) base address offset 6, n = 2 (r/w) (d0, d4, d6, ds0, ds1) base address offset 8, n = 3 (r/w) (d0, d4, d6, ds0, ds1) base address offset 3, n = 0 (ro) (d0, d2, d3, d4, d6, ds0, ds1) base address offset 5, n = 1 (ro) (d0, d2, d3, d4, d6, ds0, ds1) base address offset 7, n = 2 (ro) (d0, d4, d6, ds0, ds1) base address offset 9, n = 3 (ro) (d0, d4, d6, ds0, ds1) base address offset 10, n = 0 (r/w) (d6) base address offset 12, n = 1 (r/w) (d6) field name bit(s) reset description reserved 31:10 reserved. calibration error 9 0 calibration error. output delay overrun 8 0 output delay overrun. raw delay 7:0 0 raw delay. field name bit(s) reset description reserved 31:17 reserved. strobe n input override valid 16 0 strobe n input override valid. strobe n input override 15:8 0 strobe n input override value. strobe n input offset 7:0 0 strobe n input offset. field name bit(s) reset description reserved 31:9 reserved. strobe n input delay overrun 8 0 strobe n input delay overrun. strobe n input calculated delay 7:0 0 strobe n input calculated delay. field name bit(s) reset description reserved 31:17 reserved. strobe par n input override valid 16 0 strobe par n input override valid. strobe par n input override value 15:8 0 strobe par n input override value. strobe par n input offset 7:0 0 strobe par n input offset. ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 443 of 539 base address offset 11, n = 0 (ro) (d6) base address offset 13, n = 1 (ro) (d6) base address offset 15 (r/w) (d0, d2, d3, d4, d6, ds0, ds1) field name bit(s) reset description reserved 31:9 reserved. strobe par n input delay overrun 8 0 strobe par n input delay overrun. strobe par n input calculated delay 7:0 0 strobe par n input calculated delay. field name bit(s) reset description reserved 31:8 reserved. common strobe input multiplier 7:0 x?6a? common strobe input multiplier. ibm powernp np2g network processor preliminary configuration page 444 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.2 toggle mode register 13.3 bci format register base address offset 1 access type read/write base address x'a000 0411' reserved toggle mode 313029282726252423222120191817161514131211109876543210 access type read/write base address x'a000 0412' reserved bci_format_ctl 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description reserved 31:1 reserved. toggle mode 0 0 enables the toggle mode. 0 enables egress data store standard mode operation. places frame data into ds0, ds1, or both data stores. data storage unit (dsu) information fields indicate the following: two-bit dsu information field 00 reserved 01 ds0 10 ds1 11 ds0 and ds1 one-bit dsu information field 0ds0 1ds1 1 enables egress data store toggle mode operat ion. places frame data into ds0 and ds1 according to the twin format. dsu in formation fields indicate the following: two-bit dsu information field 00 invalid 01 twin format 0 10 twin format 1 11 invalid one-bit dsu information field 0 twin format 0 1 twin format 1 ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 445 of 539 base address offset 2 field name bit(s) reset description reserved 31:1 reserved. bci_format_ctl 0 0 controls the format of the byte count info rmation (bci) used in the egress frame control block page (fcbpage). the bci is located at word 1 (fcbpage byte offsets 4 through 7) of the fcbpage. see section 7.4.4 enqueue coprocessor on page 223. 0 compact format: bits description 31:20 reserved 19:14 starting byte 13:6 number of data buffers (weight) 5:0 ending byte 1 expanded format: bits description 31:22 reserved 21:16 starting byte 15:8 number of data buffers (weight) 7:6 reserved 5:0 ending byte ibm powernp np2g network processor preliminary configuration page 446 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.3.1 toggle mode the toggle mode provides increased bandwidth to egress data stores by changing the data storage method. the toggle mode is activated by confi guring the corresponding field in the toggle mode register (page 444). all data mover unit (dmu) modes are supported. when the toggle mode is inactive, frame data is assigned to ds0, ds1, or both data stores. bandwidth limita- tions occur when there is a consistent requirement for data to be stored in both data stores, such as with multicast and guided traffic. the toggle mode changes the data storage method by defining a ?twin? format for use by all twins assigned to a frame. unicast, multicast, and guided traffic frames are all assigned in the same manner. when the toggle mode is active, multicast and guided frames are assigned a twin format so that they are not written into both data stores. dsu settings found in the frame header are ignored; the twin format controls which data store is used for reading and writing. the twin format is assigned when the first frame buffer is loaded into the data store. for unpacked frames, the assignment toggles between formats at each start of frame. for packed frames, the assignment is based on the current write window. two twin formats are defined: twin format 0. the even buffer is located in ds0 and the odd buffer is located in ds1. twin format 1. the even buffer is located in ds1 and the odd buffer is located in ds0. for packed frames, assignment is based on where the current frame is written. this definition allows the entire packed cell (end of current frame and start of next frame) to be stored during the current write window: current frame data store next frame format 00 11 13.3.1.1 dsu information the np2g passes the dsu information that originates from the frame header to the general queues (gr0, gr1, gb0, gb1, gfq, gpq, and gtq), dispatch unit, data store coprocessor, fcbpage, discard queue, and common fcb. with the exception of the frame header dsu field, the various fields employed for this purpose are reused (when the toggle mode is active) to indicate the frame's assigned format. when the toggle mode is active, a two-bit dsu information field is defined as follows: 00 invalid 01 twin format 0 10 twin format 1 11 invalid when the toggle mode is active, a one-bit dsu information field is defined as follows: 0 twin format 0 1 twin format 1 ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 447 of 539 an example of a one-bit dsu field is the type(0) field found in the general queues (gr0, gr1, gb0, gb1, gfq, gpq, and gtq). to maintain the frame order in general data queues, gr1 or gb1 is always used. note: dispatch port configuration table (pct) entries 48 and 49 should be identical when the toggle mode is enabled because no information can be inferred about the frame other than the twin format. because the frame header dsu field is not used when the toggle mode is active, the egress fcbpage dsu field and the disp_dsu field (both two-bit dsu information fields) are initialized based on the value of type(0): type(0) fcbpage dsu, disp_dsu 001 110 the dscontrol field (a two-bit dsu information field) in the wreds, rdeds, rdmoree, and edirty data store coprocessor commands indicate data store use. when the toggle mode is active, the dscontrol field determines the format of the twins being written: 00 uses the disp_dsu value captured at dispatch 01 forces twin format 0 10 forces twin format 1 11 invalid disp_dsu conforms to the definition of a two-bit dsu information field. for the egress general data queue (e-gdq), type(1:0) indicates the twin format used and conforms to the two-bit dsu field definition above. 13.3.1.2 enqe command and qclass 5 or 6 when the toggle mode is inactive, the general data queue selected (gr0, gr1, gb0, or gb1) is based on the value of qid(2:0), where qid(0) is set to the dsusel va lue. when the toggle mode is active, gr1 or gb1 is used. this matches the selection made when the enqueue to the general data queues is performed as described in the previous section. ibm powernp np2g network processor preliminary configuration page 448 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.4 egress reassembly sequence chec k register (e_reassembly_seq_ck) this configuration register enables sequence checki ng by the egress reassembly logic. the sequence checking ensures that start of frame, optional middle of frame, and end of frame indications occur in the expected order for each cell of a frame being reassembled. each cell that does not indicate start or end of frame carries a sequence number that is checked for proper order. 13.5 aborted frame reassembly acti on control register (afrac) this configuration register controls the action the hardware takes on a frame whose reassembly was aborted due to the receipt of an abort command in a cell header for the frame. access type read/write base address x'a000 0420' reserved seq_chk_ena 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description reserved 31:1 reserved. seq_chk_ena 0 1 sequence check enable control: 0 sequence checking disabled 1 sequence checking enabled for the e_eds access type read/write base address x'a000 0440' reserved afrac 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description reserved 31:1 reserved. afrac 0 0 aborted frame reassembly action control: 0 aborted frames are enqueued to the discard queue. 1 aborted frames are enqueued with other frames on the associ- ated gq. ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 449 of 539 13.6 packing registers 13.6.1 packing control register (pack_ctrl) this configuration register is used to enable the transmission of packed cells through the iew. when enabled, the ingress cell data mover (i-cdm) determines if there is available space in the current cell being prepared for transmission and if there is an available packing candidate. a frame can be packed only if it is unicast and is longer than 48 bytes. the packed frame starts on the next quadword (qw) boundary following the last byte of the cu rrent frame. this cont rol does not affect the ability of the e_eds to receive packed cells. access type read/write base address x'a000 0480' reserved pack_ena 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description reserved 31:1 reserved. pack_ena 0 1 packing enabled flag: 0 cell packing disabled 1 cell packing enabled ibm powernp np2g network processor preliminary configuration page 450 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.6.2 packing delay register (pack_dly) the packing delay register (pack_dly) is used to modify the ingress scheduler actions by the use of programmable wait periods based on source port (sp) media speed, as determined by the dm_bus_mode setting (see data mover unit (dmu) configuration registers [page 485]). during processing of a frame for transmission to the egress si de, when it is determined that the next se rvice will be the last for the frame and if there is no packing candidate at that time, then the selected run queue is not included in subsequent service selections. a timer is used per run queue to keep the qu eue out of the service selection until either the timer expires or a packing candidate (the corresponding start-of-frame [sof] ring goes from empty to nonempty) is available. frames from the wrap dmu are not affected by this mechanism. multicast frames (which include guided traffic) and the discard queues are not affected by this mechanism. this function is disabled by setting the packing delay to ?0?. access type read/write base address x'a020 8000' reserved oc3_delay oc12_delay fasten_delay gb_delay reserved 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description reserved 31:20 reserved. oc3_delay 19:16 0 maximum packing delay in units of 3840 ns. oc12_delay 15:12 0 maximum packi ng delay in units of 960 ns. fasten_delay 11:8 0 maximum packing delay in units of 4800 ns. gb_delay 7:4 0 maximum packing delay in units of 480 ns. ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 451 of 539 13.7 initialization control registers 13.7.1 initialization register (init) this register controls the initialization of the function al islands. each functional island and the dram control- lers begin initialization when the bits in this register are set to ?1?. each functional island signals the successful completion of initialization by setting its bit in the initialization done r egister (init_done) (page 452). once a functional island has been initialized , changing the state of these bits will no longer have any effect until a reset occurs. access type read/write base address x?a000 8100? dmu_init functional_island_init dram_cntl_start reserved dc reserved a 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description dmu_init 31, 30, 28 000 data mover unit initializ ation control individually initializes each dmu. functional_island_init 27 0 functional island initialization control: 0 no operation (nop) 1 functional islands start hardware initialization. completion of hardware initialization is reported in the initialization done regis- ter (init_done) . dram_cntl_start 26 0 dram controller start control: 0nop 1 causes the dram controllers to initialize and start operation. when initialization completes, the dram controllers set the cs_init_done and e-ds init done bits of the initialization done register (init_done) . reserved 25:0 reserved. ibm powernp np2g network processor preliminary configuration page 452 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.7.2 initialization done register (init_done) this register indicates that functional islands have comp leted their initialization when the corresponding bits are set to ?1?. this register tracks the initialization state of the functional islands. the guided frame handler (gfh) reads this register during the initialization of the np2g. access type read only base address x?a000 8200? e_sched_init_done dmu_init_done i_eds_init_done reserved epc_init_done reserved cs_init_done e_ds_init_done e_eds_init_done reserved reserved iew_init_done reserved reserved dc reserved aw 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description e_sched_init_done 31 0 set to ?1? by the hardware when the egress scheduler hardware com- pletes its initialization. dmu_init_done 30, 29, 27, 26 0 set to ?1? by the hardware when the dmu hardware has completed its ini- tialization. bit dmu 30 d 29 c 27 a 26 wrap i_eds_init_done 25 0 set to ?1? by the hardware when the ingress eds completes its initialization. reserved 24 reserved. epc _ init_done 23 0 set to ?1? by the hardware when the epc completes its initialization. reserved 22 reserved. cs_init_done 21 0 set to ?1? by the hardware when the control store's dram controller com- pletes its initialization. e_ds_init_done 20 0 set to ?1? by the hardware when the egress data stores? dram controller completes its initialization. e_eds_init_done 19 0 set to ?1? by the hardware when the egress eds completes its initialization reserved 18:17 reserved. iew_init_done 16 0 set to ?1? by the hardware when the iew completes its initialization. reserved 14:0 reserved. ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 453 of 539 13.8 np2g ready regi ster (npr_ready) access type read/write base address x?a004 0020? ready reserved 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description ready 31 0 ready is configured by picocode to driv e a chip pin to indicate that the np2g has been initialized and is r eady to receive guided traffic: 0 np2g not ready 1 np2g ready reserved 30:0 reserved. ibm powernp np2g network processor preliminary configuration page 454 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.9 phase-locked loop registers 13.9.1 phase-locked loop fail register (pll_lock_fail) access type read only base address x?a000 0220? reserved pllc_lock_failed pllb_lock_failed plla_lock_failed pll_c_lock pll_b_lock pll_a_lock fail 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description reserved 31:7 reserved. pllc_lock_failed 6 pllc_lock_failed. 0 pllc has stayed correctly locked continuously since the last reset. 1 pllc has lost lock. (lock was lost any time since the last reset.) pllb_lock_failed 5 pllb_lock_failed. 0 pllb has stayed correctly locked c ontinuously since the last reset. 1 pllb has lost lock. (lock was lost any time since the last reset.) plla_lock_failed 4 plla_lock_failed. 0 plla has stayed correctly locked c ontinuously since the last reset. 1 plla has lost lock. (lock was lost any time since the last reset.) pll_c_lock 3 current status of lock indicator of the core clock pll: 0 phase/frequency lock 1 phase/frequency seek pll_b_lock 2 current status of lock indicator of the iew-b pll: 0 phase/frequency lock 1 phase/frequency seek pll_a_lock 1 current status of lock indicator of the iew-a pll: 0 phase/frequency lock 1 phase/frequency seek fail 0 phase-locked loop fail indicator - indicates that an on-chip pll has failed. this field is wr itten by the clock logic. 0 plls ok 1 pll failed ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 455 of 539 13.10 software controlled r eset register (soft_reset) this register provides a control for software to reset the network processor. 13.11 ingress free queue threshold configuration 13.11.1 bcb_fq threshold registers the value of the queue count in the bcb_fq control block is continuously compared to the values each of the three threshold registers contains. the result of this comparison affects the np2g?s flow control mecha- nisms. the values in these registers must be chosen such that bcb_fq_th_gt < bcb_fq_th_0 < bcb_fq_th_1 < bcb_fq_th_2. for proper operation the minimum value for bcb_fq_th_gt is x'08'. 13.11.2 bcb_fq threshold for guided traffic (bcb_fq_th_gt) the ingress eds reads this register to determine when to discard all packets received. access type write only base address x?a000 0240? full_reset reserved 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description full_reset 31 0 full reset value resets the np2g har dware via the picocode. this is the same full reset function provided by the reset i/o. 0 reserved 1 np2g performs an internal hardware reset reserved 30:0 reserved. access type read/write base address x'a000 1080' bcb_fq_th_gt reserved 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description bcb_fq_th_gt 31:27 x?08? buffer control block (bcb) free q ueue threshold guided traffic (gt) value is measured in units of indivi dual buffers. for exam ple, a threshold value of x?01? represents a threshold of one buffer. reserved 26:0 reserved. ibm powernp np2g network processor preliminary configuration page 456 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.11.3 bcb_fq_threshold_0 register (bcb_fq_th_0) access type read/write base address x?a000 1010? bcb_fq_th_0 reserved sa_th_0_ena bcb_fq_th_0_sa 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description bcb_fq_th_0 31:24 x?01? bcb free queue threshold 0 value, as measured in units of 16 buffers. for example, a threshold value of x?01? represents a threshold of 16 buffers. the ingress eds reads this field to determine when to perform a discard action. violation of this threshold (bcb queue count is less than the value indicated by this threshold) sends an interrupt to the epc. when bcb_fq_th_0 is violated, the disc ard action is to perform partial packet discards. new data buffers are not allocated for frame traffic and portions of frames may be lost. this discard action c ontinues until the bcb queue count is greater than the value indicated by the bcb_fq_th_0_sa value when sa_th_0_ena is set to ?1?, or when the bcb free queue count is greater t han the value indicated by the bcb_fq_th_0 value when sa_th_0_ena is set to ?0?. reserved 23:9 reserved. sa_th_0_ena 8 0 stop action threshold 0 enable. 0 the discard action started due to the bcb free queue count drop- ping below the value indicated by bcb_fq_th_0 continues until the bcb free queue count is greater than the value indicated by bcb_fq_th_0. 1 the discard action started due the bcb free queue count drop- ping below the value indicated by bcb_fq_th_0 continues until the bcb free queue count is greater than the value indicated by bcb_fq_th_0_sa. bcb_fq_th_0_sa 7:0 x?01? bcb free queue stop action threshold, as measured in units of 16 buffers. for example, a threshold value of x?01? represents a threshold of 16 buffers. when sa_th_0_ena is set to ?1?, this value is used to stop the discard action started due to the bcb fr ee queue count dropping below the value indicated by bcb_fq_th_0. ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 457 of 539 13.11.4 bcb_fq_threshold_1 register (bcb_fq_th_1) 13.11.5 bcb_fq_threshold_2 register (bcb_fq_th_2) access type read/write base address x?a000 1020? bcb_fq_th_1 reserved sa_th_1_ena bcb_fq_th_1_sa 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description bcb_fq_th_1 31:24 x?01? bcb free queue threshold 1 value, as measur ed in units of 16 buffers. for example, a threshold value of x?01? repres ents a threshold of 16 buffers. the ingress eds reads this field to determine when to perform a discard action. violation of this threshold (bcb queue count is less th an the value indicated by this threshold) sends an interrupt to the epc. when bcb_fq_th_1 is violated, the discard ac tion is to perform pa cket discards. new data buffers are not allocated for new frame tr affic, but frames already started continue to allocate buffers as needed. this discard ac tion continues until the bcb queue count is greater than the value indicated by t he bcb_fq_th_1_sa value when sa_th_0_ena is set to ?1?, or when the bcb free queue count is greater than the value indicated by the bcb_fq_th_1 value when sa_th_1_ena is set to ?0?. reserved 23:9 reserved. sa_th_1_ena 8 0 stop action threshold 1 enable. 0 the discard action started due to the bcb free queue count dropping below the value indicated by bcb_fq_th_1 cont inues until the bcb free queue count is greater than the value indicated by bcb_fq_th_1. 1 the discard action started due the bcb free queue count dropping below the value indicated by bcb_fq_th_1 continues unt il the bcb free queue count is greater than the value indicated by bcb_fq_th_1_sa. bcb_fq_th_1_sa 7:0 x?01? bcb free queue stop action threshold, as measur ed in units of 16 buffers. for example, a threshold value of x?01? represents a threshold of 16 buffers. when sa_th_1_ena is set to ?1?, this value is used to stop the discard action started due to the bcb free queue count dropping below the value indicated by bcb_fq_th_1. access type read/write base address x?a000 1040? bcb_fq_th_2 reserved 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description bcb_fq_th_2 31:24 x'01' bcb free queue threshold 2 value, as measur ed in units of 16 buffers. for example, a threshold value of x?01? repres ents a threshold of 16 buffers. violation of this threshold (bcb queue count is less than this threshold) sends an inter- rupt to the epc. reserved 23:0 reserved. ibm powernp np2g network processor preliminary configuration page 458 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.12 i-gdq threshold r egister (i-gdq_th) during ingress data movement for a frame being received, an ingress general data queue (i-gdq) threshold is tested and, if exceeded, the frame may be discarded. the discard action is to perform packet discards. new data buffers are not allocated for new frame traffic, but frames already started continue to allo- cate buffers as needed and will be enqueued as necessary. this is similar to actions taken with bcb_fq_th_1. discards due to this threshold being violated are included in the count maintained in the nfd_cnt field of the ingress port control blocks register (pcb and wrap pcb) (page 99). for debug and tuning, a global count of discards due to this threshold is maintained in the i-gdq threshold discard count (i-gdq_th_cnt) register (page 98). access type read/write base address x?a000 1100? reserved gdq_discard_th_hi reserved gdq_discard_th_lo 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description reserved 31:28 reserved. gdq_discard_th_hi 27:16 x'800' ingress gdq high threshold. when the i-gdq queue exceeds this thresh- old, the frame currently being serviced for data movement into the ingress data store may be discarded. the disca rd action is to perform new packet discards. new data buffers are not al located for new frame traffic, but frames already started continue to allocate buffers as needed and will be enqueued as necessary. reserved 15:12 reserved. gdq_discard_th_lo 11:0 x'800' if discards are occurring because t he ingress gdq high threshold was exceeded, the number of entries in the gdq queue must drop below this threshold before enqueues to the gdq queue can resume. ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 459 of 539 13.13 ingress target dmu data st orage map regist er (i_tdmu_dsu) this register defines the egress data storage units (dsus) used for each dmu. access type read/write base address x?a000 0180? dsu_encode reserved dmu_d dmu_c reserved dmu_a 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description dsu_encode 31:24 00 during enqueue operations, the values in this configuration register are loaded into the ingress frame control block?s dsu field when a dsu value is not specified by the enqueue. the hardware determines the target dmu from enqueue information and uses the corre- sponding field in this configurati on register to load the dsu field. four fields are defined, one for eac h dmu, with the following encode: 00 dsu 0 01 dsu 1 10 reserved 11 dsu0, dsu1 bits dmu 31:30 dmu_d 29:28 dmu_c 27:26 reserved 24:25 dmu_a reserved 23:0 reserved. ibm powernp np2g network processor preliminary configuration page 460 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.14 embedded processor co mplex configuration 13.14.1 powerpc core reset register (powerpc_reset) this register contains a control value used to hold the powerpc (ppc) core in reset state. access type read/write base address x?a000 8010? ppc_reset reserved 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description ppc_reset 31 1 powerpc core reset - holds the powerpc core in a reset state when set to ?1?. the rest of the powerpc functional island is not affected by this control and can only be reset by a full reset. 0 powerpc core reset disabled 1 powerpc core held in reset reserved 30:0 reserved. ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 461 of 539 13.14.2 powerpc boot redirection instruction registers (boot_redir_inst) in system implementations in which the embedded powerpc boots from the d6 dram, the mailbox and dram interface macro performs powerpc boot address redirection. under these conditions, the hardware provides instructions that redirect the boot sequence to a location in the powerpc?s dram. storage for eight instructions is provided by the boot_redir_inst registers. the powerpc boot redirect ion instruction registers (boot_redir_inst) are accessed from the cab interface. these registers provide capacity for eight instru ctions for processor local bus (plb) addresses x?ffff ffe0? - x?ffff fffc? these instructions redirect the powerpc to boot from a location in the powerpc?s dram and are configured be fore the ppc_reset is cleared. access type read/write base address x?3800 0110? - x?3800 0117? ibm powernp np2g network processor preliminary configuration page 462 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.14.3 watch dog reset enable register (wd_reset_ena) this register controls the action of a watch dog timer expiration. when set to ?1?, the second expiration of the watch dog timer causes a reset to the powerpc core. access type read/write base address x?a000 4800? wd_reset_ena reserved 313029282726252423222120191817161514131211109876543210 ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 463 of 539 13.14.4 boot override register (boot_override) with the proper setting of the boot_picocode i/o (see table 2-31: miscellaneous pins on page 75 ), this register provides boot sequence control. when the boot_picocode i/o is held to ?0?, boot control is given over to the serial/parallel manager (spm) interface hardware. when the spm completes its boot actions, a power-on reset (por) interrupt is set (inter- rupt vector 1, bit 0) which causes the gfh to start execution. when the boot_picocode i/o is held to ?1?, boot control is given over to an external source, either a host on the peripheral component interconnect (pci) or the eppc. when boot is completed, a cab write is required to set bd_override to ?1?, which causes a por interrupt (interrupt vector 1, bit 0), causing the gfh to start execution. access type read/write base address x?a000 8800? bl_override bd_override reserved 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description bl_override 31 see description set to the value of the boot_picocode i/o during reset: 0 boot code is loaded by the spm interface state machine. 1 boot code is loaded by intervention of software. the boot code can be loaded using the cabwatch interface, using the pci bus, or by using the embedded power pc. when reset to ?1?, a cab write can set this field to ?0? to start the spm interface controlled boot sequence. the spm interface reads this field to control the behavior of its state machine. bd_override 30 0 boot done override control value: 0 nop 1 when the spm interface controlled boot loading sequence is overridden, this bit is set after the epc?s instruction memory has been loaded to start the epc. a cab write can set this field to ?1? to indicate that the epc?s instruction memory is loaded. the configuration register logic reads this field when generating the por interrupt to the epc. reserved 29:0 reserved. ibm powernp np2g network processor preliminary configuration page 464 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.14.5 thread enable register (thread_enable) this register contains control information used to enable or disable each thread. 13.14.6 gfh data disable register (gfh_data_dis) this register is used to enable the dispatch to assign data frames to the gfh for processing. access type read/write bits 23:1 read only bit 0 base address x?a000 8020? reserved thread_num_ena 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description reserved 31:24 reserved. thread_num_ena (23:1) 23:1 0 thread enable: 0 disabled 1 corresponding thread enabled for use thread_num_ena 0 0 1 thread 0 (the gfh) is alwa ys enabled and cannot be disabled through this bit. access type read/write base address x?24c0 0030? reserved gfh_data_dis 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description reserved 31:1 reserved. gfh_data_dis 0 0 guided frame handler data enable control: 0 enabled 1 not enabled this field is configured to ena ble or disable the dispatchi ng of data frames to the gfh. ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 465 of 539 13.14.7 ingress maximum dcb entries (i_max_dcb) this register defines the maximum number of ingress frames that are currently allowed to be simultaneously serviced by the dispatch unit. this limits the total number of ingress frames occupying space in the dispatch control block (dcb). 13.14.8 egress maximum dcb entries (e_max_dcb) this register defines the maximum number of egress fr ames that are currently allowed to be simultaneously serviced by the dispatch unit. this limits the total number of egress frames occupying space in the dispatch control block. access type read/write base address x?2440 0c40? i_max_dcb reserved 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description i_max_dcb 31:27 x?10? maximum number of ingress frames al lowed service in the dispatch con- trol block. reserved 26:0 reserved. access type read/write base address x?2440 0c50? e_max_dcb reserved 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description e_max_dcb 31:27 x?10? maximum number of ingress frames al lowed service in the dispatch con- trol block. reserved 26:0 reserved. ibm powernp np2g network processor preliminary configuration page 466 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.14.9 ordered semaphore enable register (ordered_sem_ena) this register enables ordered semaphore operation in the np2g. a thread may have two semaphores locked at a time, with the restriction that only one of them may be ordered. when ordered semaphores are disabled, a thread may hold locks on two unordered semaphores at a time. note: failure to follow these re strictions will result in unpredictabl e operation. access type read/write base addresses x'2500 0180' reserved ordered_ena 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description reserved 31:2 reserved. ordered_ena 1:0 0 00 ordered semaphores disabled. 01 ordered semaphores enabled for ordered semaphore id queue 0. 10 ordered semaphores enabled for ordered semaphore id queue 1. 11 ordered semaphores enabled for both ordered semaphore id queues 0 and 1. ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 467 of 539 13.14.10 enhanced classification enable register (enh_hwc_ena) this register enables ad ditional hardware-a ssisted classification capabilities. access type read/write base addresses x'2500 0190' reserved enh_ipv4 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description reserved 31:1 reserved. enh_ipv4 0 0 enhanced ipv4 classificati on enable bit. when set to ?0?, enhanced ipv4 classifica- tion is disabled. when set to ?1?, the following functions are enabled: a pct bit for ipv4 forwarding (bit 24 of the pct) is added. three code entry points for ipv4 exc eption (exception_entry) for three frame formats (point-to-point protocol [ppp], ethernet with virtual local-area network [vlan], and ethernet without vlan) are added to the hccia (see section 3.13.1 hardware classifier instruction address memory (hccia_memory) on page 273). the code entry points are located at the cur- rent three ipv4 hccia entries for the three formats. when enh_ipv4 is set to ?1?, an ip frame will go to the exception_entry if: - the pct entry for ipv4 forwarding is '0'. - the version and header length fields of the ipv4 header are not x'45'. - the first four bits of the internet pr otocol (ip) destinat ion address (da) are greater than x'e'. three code entry points for ipv4 multicast (ip_mc_entry) for three frame for- mats (ppp, ethernet with vlan, and ethernet without vlan) are added to the hccia table. an ip frame will go to the ip_mc_entry if: - it does not go to the exception entry. - the first four bits of the ip da equal x'e'. three code entry points for ipv4 unicast (uc_entry) for three frame formats (ppp, ethernet with vlan, and ethernet without vlan) are added to the hccia table. an ip frame will go to the uc_entry if: - it does not go to the exception entry. - the first four bits of the ip da are less than x'e'. the time to live (ttl) is checked. if ttl 1, the r1 flags (bit 7) are set. ibm powernp np2g network processor preliminary configuration page 468 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.15 flow control structures 13.15.1 ingress flow control hardware structures 13.15.1.1 ingress transmit probability memory register (i_tx_prob_mem) the ingress flow control hardware cont ains an internal memory that holds 64 differen t transmit probabilities for flow control. the probability memory occupies 16 en tries in the cab address space. ea ch probability entry in the cab is 32 bits wide and contains four 7- bit probabilities. the 4-bit access address to each probability entry comprises two components: the 3-bit qosclass field (qqq) and the 1-bit remote egress status bus value for the current priority (t). the address is formed as qqqt. the qosclass is taken from the ingress fcbpage. the remote egress status bus value for the current priority reflects the threshold status of the egress? leased twin count. the ingress flow control ha rdware accesses probabilities within each probability memory entry by using the 2-bit color portion of the fc_info fi eld taken from the ingr ess fcbpage as an index. the probabilities are organized as shown below. access type read/write base address x?3000 00#0? note: the base address is listed with a ?#? replacing one of the hex digits. the ?#? ranges from x?0? to x?f?, and indicates which probabilit y entry is being referenced. reserved prob_0 reserved prob_1 reserved prob_2 reserved prob_3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31 reserved. prob_0 30:24 transmit probability 0 - transmit probabi lity accessed when color is ?11?. reserved 23 reserved. prob_1 22:16 transmit probability 1 - transmit probabi lity accessed when color is ?10?. reserved 15 reserved. prob_2 14:8 transmit probability 2 - transmit probabi lity accessed when color is ?01?. reserved 7 reserved. prob_3 6:0 transmit probability 3 - transmit probabili ty accessed when color is ?00?. ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 469 of 539 13.15.1.2 ingress pseudorandom number register (i_rand_num) this register contains a 32-bit pseudorandom num ber used in the flow control algorithms. the cab accesses this register in order to modify its starting point in the pseudorandom sequence. however, a write to this register is not necessary to start the pseudor andom sequence: it starts generating pseudorandom numbers as soon as the reset is finished. 13.15.1.3 free queue thresholds register (fq_th) this register contains three thresholds that are compared against the ingress free queue. the results of this comparison are used in the flow control algori thms. thresholds are in units of 16 buffers. access type read/write base addresses x?3000 0100? rand_num 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description rand_num 31:0 32-bit pseudorandom number. access type read/write base addresses x?a040 0020? reserved fq_sbfq_th fq_p0_th fq_p1_th 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:24 reserved. fq_sbfq_th 23:16 x?ff? threshold for comparison to the ingress free queue count (bcb_fq). when the number of buffers indicated by bcb_fq is less than the num- ber of buffers indicated by fq_sbf q_th, then i_freeq_th i/o is set to ?1?. fq_p0_th 15:8 x?ff? threshold for comparison to the ingress free queue count (bcb_fq), when determining flow control acti ons against priority 0 traffic. when the number of buffers indicated by bcb_fq is less than the num- ber of buffers indicated by fq_p0_t h, then flow control hardware dis- cards the frame. fq_p1_th 7:0 x?ff? threshold for comparison to the ingress free queue count (bcb_fq), when determining flow control acti ons against priority 1 traffic. when the number of buffers indicated by bcb_fq is less than the num- ber of buffers indicated by fq_p1_t h, then flow control hardware dis- cards the frame. ibm powernp np2g network processor preliminary configuration page 470 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.15.2 egress flow control structures 13.15.2.1 egress transmit probability memory (e_tx_prob_mem) register the egress flow control hardware cont ains an internal memory that hold s 64 different tran smit probabilities for flow control. the probability memory occupies 16 en tries in the cab address space. ea ch probability entry in the cab is 32 bits wide and contains four 7-bi t probabilities. an entry in the egre ss probability memory is accessed by using the 4-bit fc_info field taken from the egress fcbpage as an index. the egress flow control ha rdware uses a 2-bit address to access the probabilities with in each probability memory entry. this address (formed as fp) comprises two components: a 1-bit ?threshold exceeded? value for the current priority of the flow queue count (see section 4.7.1 flow queues (qcb) on page 349), and a 1- bit ?threshold exceeded? value for the current priority of the combined flow/port queue count (see section 4.7.2 target port queues (tpq) on page 356). access type read/write base addresses x?b000 00#0? note: the base address is listed with a ?#? replacing one of the hex digits. the ?#? ranges from x?0? to x?f?, and indicates which probabilit y entry is being referenced. reserved prob_0 reserved prob_1 reserved prob_2 reserved prob_3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31 reserved. prob_0 30:24 transmit probability 0 - transmit probabi lity accessed when ?fp? is ?11?. reserved 23 reserved. prob_1 22:16 transmit probability 1 - transmit probabi lity accessed when ?fp? is ?10?. reserved 15 reserved. prob_2 14:8 transmit probability 2 - transmit probabi lity accessed when ?fp? is ?01?. reserved 7 reserved. prob_3 6:0 transmit probability 3 - transmit probabili ty accessed when ?fp? is ?00?. ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 471 of 539 13.15.2.2 egress pseudorandom number (e_rand_num) this register contains a 32-bit pseudorandom num ber used in the flow control algorithms. the cab accesses this register in order to modify its starting point in the pseudorandom sequence. however, a write to this register is not necessary to start the pseudor andom sequence: it starts generating pseudorandom numbers as soon as the reset is finished. 13.15.2.3 p0 twin count threshold (p0_twin_th) this register contains the threshold value that is compared against the priority 0 twin count. the results of this comparison are used in the flow control algorithms. 13.15.2.4 p1 twin count threshold (p1_twin_th) this register contains the threshold value that is compared against the priority 1 twin count. the results of this comparison are used in the flow control algorithms. access type read/write base addresses x?b000 0100? rand_num 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description rand_num 31:0 32-bit pseudorandom number. access type read/write base addresses x?a040 0100? reserved p0_twin_th 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:19 reserved. p0_twin_th 18:0 x?0 0000? p0 twin count threshold value us ed in the egress flow control hardware algorithm. access type read/write base addresses x?a040 0200? reserved p1_twin_th 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:19 reserved. p1_twin_th 18:0 x?0 0000? p1 twin count threshold value used in the egress flow control hardware algorithm. ibm powernp np2g network processor preliminary configuration page 472 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.15.2.5 egress p0 twin count ewma threshold register (e_p0_twin_ewma_th) this register contains the threshol d value that is compared against the egress p0 twin count exponentially weighted moving average (ewma) (see section 4.11.2 egress p0 twin count ewma register (e_p0_twin_ewma) on page 374). the results of this comparison are placed on the remote egress status bus. 13.15.2.6 egress p1 twin count ewma threshold register (e_p1_twin_ewma_th) this register contains the threshold value that is compared against the egress p1 twin count ewma(see section 4.11.3 egress p1 twin count ewma register (e_p1_twin_ewma) on page 375). the results of this comparison are placed on the remote egress status bus. access type read/write base addresses x?a040 0400? reserved p0_twin_ewma_th 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:19 reserved. p0_twin_ewma_th 18:0 x?0 0000? priority 0 egress leased twin c ount exponentially weighted moving average threshold value. this value is compared against the egress p0 twin count ewma and its result placed on the remote egress status bus. access type read/write base addresses x?a040 0800? reserved p1_twin_ewma_th 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:19 reserved. p1_twin_ewma_th 18:0 x?0 0000? egress priority 1 twin count exponentially weighted moving average threshold value. this value is compared against the egress p1 twin count ewma and its result placed on the remote egress status bus. ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 473 of 539 13.15.3 exponentially weighted moving a verage constant (k) register (ewma_k) this register contains constant (k ) values for the various exponentially weighted moving averages calcu- lated in the ingress and egress flow control hardware. the k value is encoded as follows: k encoding constant value 00 1 01 1/2 10 1/4 11 1/8 access type read/write base addresses x?a040 0040? reserved e_fq_ewma_k e_twin_ewma_k i_fq_ewma_k 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:6 reserved. e_fq_ewma_k 5:4 00 k value for the egress free queue count exponentially weighted moving average calculation in the egress flow control hardware. e_twin_ewma_k 3:2 00 k value for the egress p0/p1 twin count ewma calculation in the egress flow control hardware. i_fq_ewma_k 1:0 00 k value for the ingress free queue count exponentially weighted moving average calculation in the ingress flow control hardware. ibm powernp np2g network processor preliminary configuration page 474 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.15.4 exponentially weighted moving average sample period (t) register (ewma_t) this register contains the sample periods for the vari ous exponentially weighted moving averages calculated in the ingress and egress flow control hardware. the values in this register are the number of 10 s multi- ples for the interval between calculations of the res pective expwas. the computation of an ewma does not occur unless the respective field in this register is nonzero. access type read/write base addresses x?a040 0080? reserved e_fq_ewma_t e_twin_ewma_t i_fq_ewma_t 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:30 reserved. e_fq_ewma_t 29:20 x?000? sample period for the egress free queue count exponentially weighted moving average calculation in the egress flow control hardware. e_twin_ewma_t 19:10 x?000? sample period for the egress p0/p1 twin count ewma calculation in the egress flow control hardware. i_fq_ewma_t 9:0 x?000? sample period for the ingress free queue count exponentially weighted moving average calculation in the ingress flow control hardware. ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 475 of 539 13.15.5 flow control force discard register (fc_force_discard) this register is used to send egress packets to the di scard port when the scheduler is disabled, or the desig- nated discard queue control block (qcb) when the sche duler is enabled. this register is added for debug purposes, but may be useful for soft reset/soft restart functions. base address offset 0 base address offset 1 base address offset 0 base address offset 1 access type read/write base addresses x?a040 2000? discard_tp reserved discard_tp reserved discard_tp reserved discard_tp reserved discard_tp reserved discard_tp reserved discard_tp reserved discard_tp reserved discard_tp 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved discard_tp reserved discard_tp reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description discard_tp 31:30, 27:26, 23:22, 19:18, 15:14, 11:10, 7:6, 3:2, 0 x?0 0000? each bit of the discard_tp field co rresponds a port identifier value (see table 9-1: target port mapping on page 499). when a bit is set to ?1?, and the fcinfo field is not set to x'f' during an enqueue, then the enqueued egress frame for the port identifier is discarded by the fl ow control logic. reserved 29:28, 25:24, 21:20, 17:16, 13:12, 9:8, 5:4, 1 reserved. field name bit(s) reset description reserved 31:8, 5:4, 1:0 reserved. discard_tp(39:38, 35:34) 7:6, 3:2 0 each bit of the discard_tp field co rresponds a port identifier value(see table 9-1: target port mapping on page 499). when a bit is set to ?1?, and the fcinfo field is not set to x'f' during an enqueue, then the enqueued egress frame for the port identifier is discarded by the fl ow control logic. ibm powernp np2g network processor preliminary configuration page 476 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.16 egress cdm stack threshold register (e_cdm_stack_th) base address offset 0 base address offset 1 base address offset 0 base address offset 1 access type read/write base address x?a000 1800? threshold reserved 313029282726252423222120191817161514131211109876543210 reserved cdm_b_bkpr cdm_a_bkpr 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description threshold 31:28 x?8? e-cdm stack threshold value. when th is threshold is violated (threshold value is greater than or equal to th e count of empty entries in the e-cdm stack), send grant is set to its disable state. the depth of the cdm stack is 32 entri es, and this field has a resolution of two buffers (i.e., a value of x'8' indicates 16 entries). reserved 27:0 reserved. field name bit(s) reset description reserved 31:2 reserved. cdm_bkpr 0 0 cdm force backpressure control. when set to ?1?, the send_grant signal is set to ?0?, indicating that the inte rface is unable to accept additional data cells. when set to ?0?, send_gr ant is set based on a e_cdm_stack threshold violation. ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 477 of 539 13.17 free queue extended stack maxi mum size (fq_es_ max) register this register sets the number of buffers that are released into the free queue and thus made available for the storage of received frames. the egress eds reads this register when building the fq_es. access type read/write base address x?a000 2100? fq_es_max reserved 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description fq_es_max 31:24 x?08? maximum size of the free queue extended stack measured in incre- ments of 2 k buffer twins. the egress eds reads this value when building the fq_es. the maximum size is li mited by the ddr dram used by the egress data store. each 128-bit page hol ds six entries each. once this register is written, the hardware creates entries in the buffer free queue (fq) at a rate of 6 entries every 150 or 165 ns (rate is dependent on the setting of bit 6 of the dram parameter register - 11/10 ). the value in this register can be m odified; however, the new value cannot be smaller than the current value. reserved 23:0 reserved. ibm powernp np2g network processor preliminary configuration page 478 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.18 egress free queue thresholds a queue count is maintained by the free queue extended stack management hardware. the count value is continuously compared to the value contained in each of three threshold registers. the result of this compar- ison affects the np2g?s flow c ontrol mechanisms. the register values must be chosen such that fq_es_th_0 fq_es_th_1 fq_es_th_2. 13.18.1 fq_es_threshold_0 register (fq_es_th_0) access type read/write base address x?a000 2010? fq_es_thresh_0 reserved 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description fq_es_thresh_0 31:17 x?0000? free queue extended stack threshold 0 as measured in units of 16 twins. when this threshold is violated (the threshold value is greater than the number of remaining twins in the free queue): frame data received at the iew is discarded (the number of frames discarded is counted). frames that have started reassembly that receive data while this threshold is violated are also disc arded (all data associated with the frame is discarded). guided traffic data is not discarded. an interrupt is sent to the epc. reserved 16:0 reserved. ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 479 of 539 13.18.2 fq_es_threshold_1 register (fq_es_th_1) 13.18.3 fq_es_threshold_2 register (fq_es_th_2) access type read/write base address x?a000 2020? fq_es_thresh_1 reserved 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description fq_es_thresh_1 31:17 x?0000? free queue extended stack threshold 1 as measured in units of 16 twins. when this threshold is violated (the threshold value is greater than the number of remaining twins in the free queue), an interrupt is sent to the epc. reserved 16:0 reserved. access type read/write base address x?a000 2040? fq_es_thresh_2 reserved 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description fq_es_thresh_2 31:17 x?0000? free queue extended stack threshold 2 as measured in units of 16 twins. when this threshold is violated (the threshold value is greater than the number of remaining twins in the free queue), an interrupt is sent to the epc and, if enabled by dmu configur ation, the ethernet preamble is reduced to 6 bytes. reserved 16:0 reserved. ibm powernp np2g network processor preliminary configuration page 480 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.19 egress frame data qu eue thresholds (e_grx_gbx_th) the np2g supports four queues for egress data frames gr0 and gr1 (high priority) and gb0 and gb1 (low priority). see section 4.5.2 general queues (gr0, gr1, gb0, gb1, gfq, gpq, gtq) on page 328 for more information. thresholds are provided for the egress frame data queues to allow configuration of discard actions when these queues become full. when a threshold is violated, the frame attempting to be enqueued in the general queue is sent to the egress general discard queue (e-gdq) instead (see section 4.5.3 discard queue (gdq) on page 331). when the e-gdq is full, no further cells are pulled from the iew until the condition is resolved. each threshold has a 32-entry resolution; high and low thresholds are defined for each egress frame data queue. when exceeding the high threshold, the above discard actions occur and continue until the number of entries in the queue drops below the low threshold. base address offset 0 base address offset 1 base address offset 0 access type read/write base address x?a000 1200? reserved grx_hi_th reserved grx_lo_th 313029282726252423222120191817161514131211109876543210 reserved gbx_hi_th reserved gbx_lo_th 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description reserved 31:30 reserved. grx_hi_th 29:16 x?3fff? grx high threshold. when a grx qu eue (gr0 or gr1) exceeds this threshold, new frames are enqueued to the discard stack until the number of entries drops below the grx low threshold. reserved 15:14 reserved. grx_lo_th 13:0 x?3fff? grx low threshold. if discards are occurring because the grx high threshold was exceeded, the number of entries in the corresponding grx queue (gr0 or gr1) must drop below this threshold before enqueues to the corresponding grx queue can resume. ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 481 of 539 base address offset 1 13.20 discard flow qcb register (discard_qcb) this register is used by the egress hardware when th e scheduler and flow control are enabled. this register contains the address of the flow queue control blo ck (qcb) to be used when egress flow control actions require that the frame be discarded. this register and the qcb referenced by the address must be configured by hardware. see section 6 beginning on page 141 for details on configuring the qcb. when the scheduler is disabled, the register contains the target port queue to which the flow control discarded frames are sent. this value should be set to x?029?. field name bit(s) reset description reserved 31:30 reserved. gbx_hi_th 29:16 x?3fff? gbx high threshold. when a gbx queue (gb0 or gb1) exceeds this threshold, new frames are enqueued to the discard stack until the number of entries drops below the gbx low threshold. reserved 15:14 reserved. gbx_lo_th 13:0 x?3fff? gbx low threshold. if discards are occurring because the gbx high threshold was exceeded, the number of entries in the corresponding gbx queue (gb0 or gb1) must drop below this threshold before enqueues to the corresponding gbx queue can resume. access type read/write base address x?a000 1400? reserved discard_qid 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description reserved 31:11 reserved. discard_qid 10:0 x?029? the discard queue identification (qid ) field contains the address of the qcb that has been configured for discarding egress frames while the scheduler is enabled. when the scheduler is disabled, this is the target port id (x?029?) to whic h discarded frames due to flow control discard actions are sent. ibm powernp np2g network processor preliminary configuration page 482 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.21 bandwidth allocation register (bw_alloc_reg) the bandwidth (bw) allocation register is used to assure bandwidth to the egress data store for the epc data store coprocessor and the dispatch unit. for the epc data store coprocessor, this register provides assured bandwidth when writing to the egress data store. for the epc dispatch unit, it provides assured bandwidth when reading the egress data store. access type read/write base addresses x?a000 2800? reserved disp_bw_alloc ds_bw_alloc 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:16 reserved. disp_bw_alloc 15:8 0 dispatch unit read bw allocation cont rol value. an 8-bit countdown value. a value of 0 disables this function. the value is loaded into a control regis- ters and is decremented each data store access window. while the con- trol register is nonzero, the following priority is observed for read access to the egress data stores: 8/9ths of the time 1/9th of the time 1. pmm - dmu a-d read requests pmm - dmu a, c, d read requests 2. discard port dispatch unit dispatch unit epc data store coprocessor read 3. epc data store coprocessor read discard port 4. pmm - wrap dmu pmm - wrap dmu once the control register decrements to zero, the following priority is observed: 8/9th of the time 1/9th of the time 1. dispatch unit dispatch unit 2. pmm - dmu a-d read requests pmm - dmu a, c, d read requests discard port epc data store coprocessor read 3. epc data store coprocessor read discard port 4. pmm - wrap dmu pmm - wrap dmu when the dispatch unit is serviced , or a dram refresh occurs for ds0/ds1, the control register is re loaded with the configuration value. ds_bw_alloc 7:0 0 data store coprocessor write bw allo cation control value. an 8-bit count- down value. a value of 0 disables this function. this value is loaded into a control register and is decrement ed each data store access window. while the control register is nonzero, the iew interface has high priority for data store write access. the epc data store coprocessor write requests must wait until there is a fr ee window. once the control register has counted down to zero, the epc request for the data store write access window has high priority. the cont rol register remains at zero until an epc data store coprocessor write request is serviced. whenever an epc data store write wi ndow request is serviced and the configuration register is nonzero, the control register is reloaded with the configuration value. ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 483 of 539 13.22 miscellaneous controls register (misc_cntrl) this register sets the speed of the embedded powe rpc processor and sets a guaranteed egress data store bandwidth for the wrap port access type read/write base addresses x?9001 6e00? reserved powerpc_2x wrap_port_bw reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description reserved 31:17 reserved. powerpc_2x 16 0 powerpc processor speed. 0 powerpc processor runs at 133 mhz. 1 powerpc processor runs at 266 mhz. wrap_port_bw 15:8 x?00? wrap port read bandwidth allocation control value. an 8-bit countdown value. a value of 0 disables this function. the value is loaded into a control r egister and is decremented at each data store access window. when the cont rol register is nonzero, the prior- ity for read access to the egress data store is as described in the band- width allocation register (see section 13.21 on page 482). when the control register becomes zero , the priorities shown in the table for the bandwidth allocation register c hange so that the wrap port is priori- tized above the dispatch unit in all four cases. reserved 7:0 reserved. ibm powernp np2g network processor preliminary configuration page 484 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.23 frame control block fq size register (fcb_fq_max) this register sets the number of frame control blocks that are released to the fcb fq during initialization. this register must be set prior to initialization (see initialization register (init) [page 451]) to affect the fcb fq size. any changes after in itialization will not affect th e number of available fcbs. access type read/write base address x?a000 2200? fcb_fq _max reserved 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description fcb_fq_max 31:30 00 indicates the number of fcbs released into the fcb free queue during initialization. 00 128k 01 256k 10 512k 11 reserved reserved 29:0 reserved. note: the following settings are recommended based on the size of the d4 dram which is configured in bits 2:1 of the dram param- eter register (dram_parm) (page 434). dram_size fcb_fq_max 00 01 01 10 10 10 11 reserved ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 485 of 539 13.24 data mover unit (dmu ) configuration registers there are three data mover units (dmu) configured for internal medium access control (mac) operation, for external connection detection (i.e., attached control point detection), and for external bus operation (i.e., gigabit media-independent interface [gmii], serial media-independent interface [smii], ten-bit interface [tbi], and packet-over-sonet [pos] framer). base address offset 0 base address offset 1 base address offset 2 base address offset 3 access type base address offset 0 read only base address offset 1 base address offset 2 base address offset 3 read/write base address dmu_a x?a001 0010? dmu_c x?a001 0040? dmu_d x?a001 0080? reserved in_reset cp_detect 313029282726252423222120191817161514131211109876543210 reserved framer_ac_strip ac_strip_ena framer_ac_insert ac_insert_ena bus_delay crc_type_32 vlan_chk_dis etype_chk_dis pause_chk_dis ignore_crc enet_catchup_ena tx_thresh dm_bus_mode tx_ena(9:0) 313029282726252423222120191817161514131211109876543210 reserved rx_ena (9:0) fdx/hdx (9:0) jumbo (9:0) 313029282726252423222120191817161514131211109876543210 reserved honor_pause (9:0) 313029282726252423222120191817161514131211109876543210 ibm powernp np2g network processor preliminary configuration page 486 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 base address offset 0 base address offset 1 field name bit(s) reset description reserved 31:2 reserved. in_reset 1 1 dmu in reset indicator origin ates in the clocking logic: 0 written when the clock logic removes the reset signal for the dmu. 1 dmu is held in reset mode. cp_detect 0 0 control point detected indicator value originat es in the physical mac multiplexer (pmm): 0 control point processor connection not present 1 dmu detected a control point processor connection field name bit(s) reset description reserved 31:28 reserved. framer_ac_strip 27 0 configures the mac operation for an attached pos framer: 0 framer passes address control (ac) field to the network processor. 1 framer does not pass ac field to the ne twork processor. t he cyclic redundancy check (crc) performed is modified to account for the missing field. an ac value of x'ff03' is assumed. ac_strip_ena 26 0 configures the mac operation for an attached pos framer: 0 ac field is not stripped from the packet. 1 ac field is stripped from th e packet prior to being stor ed in the ingress data store. framer_ac_insert 25 0 configures the mac operation for an attached pos framer: 0 ac field is assumed present in the packet sent to the framer. 1 ac field is not present in the packet sent to the framer. the framer inserts this field and crc generation is adjus ted to account for the missing ac field. an ac value of x'ff03' is assumed. ac_insert_ena 24 1 configures the mac operation for an attached pos framer: 0 ac field is not inserted by the mac. for proper operation, framer_ac_insert must be set to ?1?. 1 ac field is inserted by the mac. for proper operation, framer_ac_insert must be set to ?0?. bus_delay 23 0 bus delay controls the length of the delay between a poll request being made and when the mac samples the framer?s response: 0 sample is taken 1 cycle after the poll request 1 sample is taken 2 cycles after the poll request. crc_type_32 22 0 crc_type_32 controls the type of frame cr c checking and generation performed in the pos mac. this field does not control crc generation for the ethernet mac. the ether- net mac can generate only 32-bit crc. 0 16-bit crc in use 1 32-bit crc in use vlan_chk_dis 21 0 vlan checking disable control value: 0 enable vlan checking. 1 disable vlan checking by the dmu. etype_chk_dis 20 0 ethernet type checking disable control value: 0 enable dmu checking 1 disable dmu checking of e_type_c and e_type_d ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 487 of 539 base address offset 2 pause_chk_dis 19 0 pause frame checking disable control value: 0 pause frames are processed by the mac. they are not sent to the ingress eds. 1 pause frames are not processed by the ma c. the frames are sent to the ingress eds for service. see also honor_pause in offset 3 for additional control of the mac in relation to pause frames. ignore_crc 18 0 ignore crc controls the behavior of crc checking for each dmu. 0 discard frames with bad crc 1 ignore bad crc enet_catchup_ena 17 1 ethernet mac catch up enabled. when enabled and fq_es_threshold_2 is violated, the mac uses a 6-byte preamble in stead of a 7-byte preamble. 0 disabled 1 enabled tx_thresh 16:14 100 transmit threshold configures the number of cell buffers that must be filled before the transmission of a frame can start. 000 invalid 001-100 range available for all dmu_bus_mode settings 101-111 range available only for gigabi t ethernet, pos oc-3, and pos oc-12 dmu_bus_mode settings the normal setting for this fiel d is half of the available buffers unless toggle mode is used, in which case this field should be set to ?100? for all modes. 011 fast ethernet mode 100 all other modes dm_bus_mode 13:10 1010 data mover bus mode configures the mode in which the data mover bus operates: 0000 reserved 0001 10/100 ethernet smii mode (dmu c & d only) 0010 gigabit ethernet gmii mode 0011 gigabit ethernet tbi mode 0100 pos oc-12 mode; nonpolling pos support 0101 pos 4xoc-3 mode; polling pos support (dmu c & d only) 0110-1001 reserved 1010 cp detect mode 1011 debug mode (dmu d only). this mode is supported only when its use is directed by an ibm network pr ocessor applications engineer. 1100-1101 reserved 1110 dmu disabled 1111 reserved note: when configuring the dmu, the dmu_bus_mode field must be set first. subse- quent cab writes can used to configure the remaining fields. tx_ena(9:0) 9:0 0 port transmit enable control is a bi twise enable for each port?s transmitter: 0 disable port 1 enable port field name bit(s) reset description reserved 31:30 reserved. rx_ena(9:0) 29:20 0 port receive enable control is a bitwise enable for each port?s receiver: 0 disable port 1 enable port field name bit(s) reset description ibm powernp np2g network processor preliminary configuration page 488 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 base address offset 3 fdx/hdx(9:0) 19:10 0 full duplex or half duplex operation mode for ports 9 to 0 controls the mode of operation for the associated port: 0 half duplex (hdx) operation 1 full duplex (fdx) operation jumbo(9:0) 9:0 0 jumbo frame operation mode for ports 9 to 0 controls the mode of operation for the associated port: 0 jumbo frames disabled 1 jumbo frames enabled the maximum length of a jumbo frame is determined by the value in the ethernet jumbo frame size register (en_jumbo_fs) (page 489). field name bit(s) reset description reserved 31:10 reserved. honor_pause(9:0) 9:0 0 honor pause control value is a bitwise control value for the port?s pause function: 0 ignore pause frames received by corresponding port 1 pause when pause frame re ceived by corresponding port field name bit(s) reset description ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 489 of 539 13.25 frame pad configurat ion register (dmu_pad) this register configures the hardware-assisted fram e alteration padding function for each dmu. the minimum number of bytes per frame and the padding byte are specified. the padding function is available only when the dm_bus_mode field of the data mover unit (dmu) configuration register (page 485) is set to ?0001?, ?0010?, or ?0011? (one of the ethernet mac modes of operation). 13.26 ethernet jumbo frame si ze register (en_jumbo_fs) this register controls the maximum frame size supported by the network processor when the dmu is config- ured for ethernet operation. this register configurat ion is used when jumbo frame support is enabled in the data mover unit (dmu) configuration register (page 485). the network processor is constrained to a maximum of 14k (14336) bytes. frames received by the network processor that exceed the length specified by this register are aborted during reception. note that this value is modified by an additional four bytes when a vlan-tagged frame is detected. access type read/write base address dmu_a_pad x?a002 0100? dmu_c_pad x?a002 0400? dmu_d_pad x?a002 0800? reserved pad_byte min_size 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description reserved 31:16 reserved. pad_byte 15:8 x?00? contains the value us ed to pad the frame to minimum size. min_size 7:0 0 the minimum size value (in bytes). when set to zero, the padding function is disabled. access type read/write base address x?a040 8000? reserved jumbo_max 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description reserved 31:14 reserved. jumbo_max 13:0 x?233a? defines the maximum length for jumbo ethernet frames. this value is used to determine when to abort receipt of a frame and/or increment long frame counts. the value used to caus e the above actions is increased by four bytes when a vlan-tagged frame is detected. ibm powernp np2g network processor preliminary configuration page 490 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.27 qd accuracy register (qd_acc) the qd accuracy register (qd_acc) tunes the egress scheduler?s weighted fair queueing (wfq) rings (see section 6.4 the egress scheduler on page 152 ). the values assure fairness and some benefit to queues with lower defined qd values that expect better service when enqueueing to an empty queue. the value is also a scaling factor when servicing queues. configuration recommendations are dependent on the maximum frame sizes expected for a dmu: max frame size qd_acc_dmu 2 k 6 9 k 8 14 k 10 there is one field defined per media dmu (a, c, d). access type read/write base address x?a002 4000? qd_acc_ dmu_d qd_acc_ dmu_c reserved qd_acc_ dmu_a reserved 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description qd_acc_dmu_d 31:28 0 qd accuracy value used for dmu_d. qd_acc_dmu_c 27:24 0 qd accuracy value used for dmu_c. reserved 23:20 0 reserved. qd_acc_dmu_a 19:16 0 qd accuracy value used for dmu_a. reserved 15:0 reserved. ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 491 of 539 13.28 packet over sonet co ntrol register (pos_ctrl) one configuration register per dmu is provided to control pos framer interaction. this register configures transmit and receive burst sizes and sets the value used for ac field insertion. the ac_specification value allows per-port configuration of the ac value used when the ac_insert_ena, framer_ac_strip, and/or framer_ac_insert fields are set to ?1?. when either the framer_ac_strip or framer_ac_insert field is set to ?1?, an initial crc value (determined by the ac value assumed for the port) must be loaded into offsets 12-15. for cases where both the framer_ac_strip and framer_ac_insert fields are set to ?1?, the ac byte assumed for the port on ingress (framer_ac_strip) and egress (framer_ac_insert) must be the same value. a backward compatibility mode allows a single insert value to be specified for all ports (offset 0) on the transmit side and a value of x'ff03' to be assumed for all ports on the receive side. base address offset 0 base address offset 8, port 0 base address offset 9, port 1 (for dmu c and d only) base address offset 10, port 2 (for dmu c and d only) base address offset 11, port 3 (for dmu c and d only) base address offset 12, port 0 base address offset 13, port 1 (for dmu c and d only) base address offset 14, port 2 (for dmu c and d only) base address offset 15, port 3 (for dmu c and d only) access type read/write base address dmu_a x?a004 0100? dmu_c x?a004 0400? dmu_d x?a004 0800? tx_burst_size rx_burst_size a/c insert value 313029282726252423222120191817161514131211109876543210 disable reserved ac_specification 313029282726252423222120191817161514131211109876543210 initial_crc 313029282726252423222120191817161514131211109876543210 ibm powernp np2g network processor preliminary configuration page 492 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 base address offset 0 base address offset 8, port 0 base address offset 9, port 1 (for dmu c and d only) base address offset 10, po rt 2 (for dmu c and d only) base address offset 11, po rt 3 (for dmu c and d only) base address offset 12, port 0 base address offset 13, po rt 1 (for dmu c and d only) base address offset 14, po rt 2 (for dmu c and d only) base address offset 15, po rt 3 (for dmu c and d only) field name bit(s) reset description tx_burst_size 31:24 x'10' transmit burst size. used only for oc-3 modes of operation. oc-12 inter- faces transmit until the framer de-asserts txpfa. when set to ?0?, the mac uses txpfa from the frame to stop transmission of data. when set to a value other than 0, the mac will burst data to the framer up to the burst size or until the fram er drops txpfa. it is recommended that the low water mark in the frame be set to a value equal to or greater than the value of tx_burst_size. rx_burst_size 23:16 x'10' receive burst size. a/c insert value 15:0 x'ff03' value used by the mac when ac_insert_ena is set to ?1?. field name bit(s) reset description disable 31 1 disables the per-port ac by te specification for port n. 0 when the ac_insert_en field in the data mover unit (dmu) con- figuration register (page 485) is set to ?1?, the ac_specification field is used. when the fr amer_ac_strip field in the dmu con- figuration register is set to ?1?, the initial_crc value (this offset plus four) plus the frame data are used for crc checking. when the framer_ac_insert field in the dmu configuration register is set to ?1?, the initial_crc value (this offset plus four) plus the frame data are used for crc generation. 1 when the ac_insert_en field for the dmu configuration register is set to ?1?, the a/c insert value found in offset 0 is used. when the framer_ac_strip field in the dmu configuration register is set to ?1?, an ac value of x?ff03? plus the frame data are used for crc checking. when the framer _ac_insert field of the dmu configuration register is set to ?1?, an ac value of x?ff03? plus the frame data are used for crc generation. reserved 30:16 reserved. ac_specification 15:0 x?ff03? used when the ac_insert_en field of the dmu configuration register is set to ?1?, and the disable fiel d (bit 31 above) is set to ?0?. field name bit(s) reset description initial_crc 31:0 x?1382 d02d? initial crc value for port n . used for crc generation (when the framer_ac_insert field in the dmu configuration register is set to ?1?) or checking (when the framer_a c_strip field in the dmu configuration reg- ister is set to ?1?) when the disable field (this offset minus four) is set to ?0?. the reset value is based on an ac va lue of x?ff03? and the 32-bit crc. ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 493 of 539 13.28.1 initial crc value determination the tcl script below illustrate s the algorithm for determining the initia l_crc value when the user provides the software application program interface (api) with the ac byte specification when the framer_ac_strip and/or frame_ac_insert fields of the data mover unit (dmu) configuration register (page 485) are set to ?1?. # initial crc value generation for pos ac specifications proc initcrc { acbytes crctype } { # acbytes is a bit vector passed in hex format (eg 0xaacc) # crctype is either 32 or 16 # golden crc test: initcrc 0xff03 32 results in 0x1382d02d # initcrc 0xff03 16 results in 0x0000c7bc # these values are set into the configuration register as shown. ie cabwrite $address 0x0000c7bc # puts "setting up initial next_crc and crc values" for {set i 0} {$i < 32} {incr i} { set next_crc($i) 1 ;# initialize next_crc value 0 up to 31 set crc($i) $next_crc($i) ;# initialize crc value 0 up to 31 } # puts "creating bit array of input acbytes" for {set i 0} {$i < 16} {incr i} { set temp [expr { ($acbytes >> $i) & 0x0001 }] set input_data_stored($i) $temp ;# input data 15 down to 0 # puts [format "input_data_stored bit %u : %u" $i $input_data_stored($i)] } for {set pass 0} {$pass < 2} {incr pass} { # puts [format "starting pass %u" $pass] # set up input data for crc generation. data is 7 down to 0 for {set j 0} {$j < 8} {incr j} { set data_stored($j) $input_data_stored([expr {$j + (1-$pass) * 8}]) } if {($crctype == 32)} { # puts "generating 32 bit crc" for {set i 0} {$i < 8} {incr i} { set crcbit [expr {31 - $i}] # puts [format "datastored(%u): %u \t crc(%u): %u" $i $data_stored($i) $crcbit $crc($crcbit)] set n($i) [expr {$data_stored($i) ^ $crc($crcbit)}] } set next_crc(31) [expr {$crc(23) ^ $n(2)}] set next_crc(30) [expr {$crc(22) ^ $n(0) ^ $n(3)}] set next_crc(29) [expr {$crc(21) ^ $n(0) ^ $n(1) ^ $n(4)}] set next_crc(28) [expr {$crc(20) ^ $n(1) ^ $n(2) ^ $n(5)}] set next_crc(27) [expr {$crc(19) ^ $n(0) ^ $n(2) ^ $n(3) ^ $n(6)}] set next_crc(26) [expr {$crc(18) ^ $n(1) ^ $n(3) ^ $n(4) ^ $n(7)}] set next_crc(25) [expr {$crc(17) ^ $n(4) ^ $n(5)}] set next_crc(24) [expr {$crc(16) ^ $n(0) ^ $n(5) ^ $n(6)}] set next_crc(23) [expr {$crc(15) ^ $n(1) ^ $n(6) ^ $n(7)}] set next_crc(22) [expr {$crc(14) ^ $n(7)}] set next_crc(21) [expr {$crc(13) ^ $n(2)}] set next_crc(20) [expr {$crc(12) ^ $n(3)}] set next_crc(19) [expr {$crc(11) ^ $n(0) ^ $n(4)}] set next_crc(18) [expr {$crc(10) ^ $n(0) ^ $n(1) ^ $n(5)}] set next_crc(17) [expr {$crc(9) ^ $n(1) ^ $n(2) ^ $n(6)}] set next_crc(16) [expr {$crc(8) ^ $n(2) ^ $n(3) ^ $n(7)}] set next_crc(15) [expr {$crc(7) ^ $n(0) ^ $n(2) ^ $n(3) ^ $n(4)}] set next_crc(14) [expr {$crc(6) ^ $n(0) ^ $n(1) ^ $n(3) ^ $n(4) ^ $n(5)}] ibm powernp np2g network processor preliminary configuration page 494 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 set next_crc(13) [expr {$crc(5) ^ $n(0) ^ $n(1) ^ $n(2) ^ $n(4) ^ $n(5) ^ $n(6)}] set next_crc(12) [expr {$crc(4) ^ $n(1) ^ $n(2) ^ $n(3) ^ $n(5) ^ $n(6) ^ $n(7)}] set next_crc(11) [expr {$crc(3) ^ $n(3) ^ $n(4) ^ $n(6) ^ $n(7)}] set next_crc(10) [expr {$crc(2) ^ $n(2) ^ $n(4) ^ $n(5) ^ $n(7)}] set next_crc(9) [expr {$crc(1) ^ $n(2) ^ $n(3) ^ $n(5) ^ $n(6)}] set next_crc(8) [expr {$crc(0) ^ $n(3) ^ $n(4) ^ $n(6) ^ $n(7)}] set next_crc(7) [expr {$n(0) ^ $n(2) ^ $n(4) ^ $n(5) ^ $n(7)}] set next_crc(6) [expr {$n(0) ^ $n(1) ^ $n(2) ^ $n(3) ^ $n(5) ^ $n(6)}] set next_crc(5) [expr {$n(0) ^ $n(1) ^ $n(2) ^ $n(3) ^ $n(4) ^ $n(6) ^ $n(7)}] set next_crc(4) [expr {$n(1) ^ $n(3) ^ $n(4) ^ $n(5) ^ $n(7)}] set next_crc(3) [expr {$n(0) ^ $n(4) ^ $n(5) ^ $n(6)}] set next_crc(2) [expr {$n(0) ^ $n(1) ^ $n(5) ^ $n(6) ^ $n(7)}] set next_crc(1) [expr {$n(0) ^ $n(1) ^ $n(6) ^ $n(7)}] set next_crc(0) [expr {$n(1) ^ $n(7)}] } else { # 16 bit crc # puts "generating 16 bit crc" for {set i 0} {$i < 8} {incr i} { set n($i) [expr {$data_stored($i) ^ $crc([expr {15 - $i}])}] } for {set i 16} {$i < 32} {incr i} { set next_crc($i) 0 } set next_crc(15) [expr {$n(0) ^ $n(4) ^ $crc(7)}] set next_crc(14) [expr {$n(1) ^ $n(5) ^ $crc(6)}] set next_crc(13) [expr {$n(2) ^ $n(6) ^ $crc(5)}] set next_crc(12) [expr {$n(0) ^ $n(3) ^ $n(7) ^ $crc(4)}] set next_crc(11) [expr {$n(1) ^ $crc(3)}] set next_crc(10) [expr {$n(2) ^ $crc(2)}] set next_crc(9) [expr {$n(3) ^ $crc(1)}] set next_crc(8) [expr {$n(0) ^ $n(4) ^ $crc(0)}] set next_crc(7) [expr {$n(0) ^ $n(1) ^ $n(5)}] set next_crc(6) [expr {$n(1) ^ $n(2) ^ $n(6)}] set next_crc(5) [expr {$n(2) ^ $n(3) ^ $n(7)}] set next_crc(4) [expr {$n(3)}] set next_crc(3) [expr {$n(0) ^ $n(4)}] set next_crc(2) [expr {$n(1) ^ $n(5)}] set next_crc(1) [expr {$n(2) ^ $n(6)}] set next_crc(0) [expr {$n(3) ^ $n(7)}] } ; # if crctype # move next_crc into crc for {set i 0} {$i < 32} {incr i} { set crc($i) $next_crc($i) ;# crc value 0 up to 31 } } ; # for pass set golden_crc 0x00000000 for {set i 0} {$i < 32} {incr i} { # puts [format "%u : %u" $i $crc($i)] set golden_crc [expr {($golden_crc << 1) | $crc([expr {31 - $i}])}] } puts [format "golden crc is %#010x" $golden_crc] } ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 495 of 539 13.29 packet over sonet maxi mum frame size (pos_max_fs) this register controls the maximum frame size supported by the network processor. pos permits frames up to 64 k bytes, however, the network processor is cons trained to 14 k (14336) bytes maximum. this register allows setting for smaller fr ame sizes. frames received by the netw ork processor that exceed the length specified by this register are aborted during reception. access type read/write base address x?a004 0080? reserved pos_max_fs 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description reserved 31:14 reserved. pos_max_fs 13:0 x?3800? packet over sonet maximum frame si ze sets the maximum frame size that the network processor can receiv e on a pos port. the value in this register is used to determine the l ength of a long frame for the ingress and egress long frame counters. ibm powernp np2g network processor preliminary configuration page 496 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.30 ethernet encapsulation type register for control (e_type_c) this configuration register is used by the pmm to recognize ethernet-encapsulat ed guided frames. when the ethernet frame?s type field matches this value, the mac destination address (da), source address (sa), and type fields of the frame are stripped and the frame is queued onto the guided frame queue (gfq). 13.31 ethernet encapsulation type register for data (e_type_d) this configuration register is used by the pmm to recognize ethernet-encapsulated data frames. when the ethernet frame?s type field matches this value, the ma c da, sa, and type fields of the frame are stripped and the frame is queued onto the general data queue (gdq). access type read/write base addresses x?a001 1000? e_type reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description e_type 31:16 x?0000? ethernet type used for encapsulated guided traffic. reserved 15:0 reserved. access type read/write base addresses x?a001 2000? e_type reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description e_type 31:16 x?0000? ethernet type used for encapsul ated control point (cp) data traffic. reserved 15:0 reserved. ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 497 of 539 13.32 source address array (sa_array) the sa array is a register array containing 64 source address values. the sa pointer from the egress fcb references elements of this register array. the value retrieved from the sa array is used to insert or overlay the sa field of transmitted frames during egress frame alteration. base address offset 0 base address offset 1 base address offset 0 base address offset 1 access type read/write base addresses note: each dmu listed below contains 64 entries. nibbles 5 and 6 of the base address are incremented by x?01? for each successive entry, represented by ?##,? and ranging from x?00? to x?3f?. the word offset is represented by ?w,? and ranges from x?0? to x?1?. dmu_a x?8810 0##w? dmu_c x?8812 0##w? dmu_d x?8813 0##w? wrap x?8814 0##w? sa (47:16) 313029282726252423222120191817161514131211109876543210 sa (15:0) reserved 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description sa(47:16) 31:0 not defined source address value. the dmu acce sses an sa value when it performs egress frame alteration f unctions. the data is the source address that is either overlaid or inserted into a frame. the entry address is from the saptr field of the fcb. field name bit(s) reset description sa(15:0) 31:16 not defined source address value. the dmu acce sses an sa value when it performs egress frame alteration f unctions. the data is the source address that is either overlaid or inserted into a frame. the entry address is from the saptr field of the fcb. reserved 15:0 reserved. ibm powernp np2g network processor preliminary configuration page 498 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.33 destination address array (da_array) the da array is a register array containing 64 destination address values. the daptr field from the egress fcb, when enabled by the egress fcb field en_hwa(2), is used to reference elements of this register array. the value retrieved from the da array is used to insert or overlay the da field of transmitted frames during egress frame alteration. base address offset 0 base address offset 1 base address offset 0 base address offset 1 access type read/write base addresses note: each dmu listed below contains 64 entries. nibbles 5 and 6 of the base address are incremented by x?01? for each successive entry, represented by ?##,? and ranging from x?00? to x?3f?. the word offset is represented by ?w,? and ranges from x?0? to x?1?. dmu_a x?8830 0##w? dmu_c x?8832 0##w? dmu_d x?8833 0##w? wrap x?8834 0##w? da (47:16) 313029282726252423222120191817161514131211109876543210 da (15:0) reserved 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description da(47:16) 31:0 not defined destination address value. when enabled by fcb field en_hwa(2), the dmu accesses a da value when it per forms sa/da insert/overlay egress frame alteration functions. the data is the destination address that is either overlaid or inserted into a fr ame. the entry address is from the fcb daptr field. field name bit(s) reset description da(15:0) 31:16 not defined destination address value. when enabled by fcb field en_hwa(2), the dmu accesses a da value when it per forms sa/da insert/overlay egress frame alteration functions. the data is the destination address that is either overlaid or inserted into a fr ame. the entry address is from the fcb daptr field. reserved 15:0 reserved. ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 499 of 539 13.34 programmable i/o register (pio_reg) this configuration register provides the control for t he programmable input and output (pio) signal pins (see section 2.1.8 miscellaneous pins on page 75) . access type read/write base address x?a040 4000? reserved pio_state pio_enable pio_write 313029282726252423222120191817161514131211109876543210 field name bit(s) reset description reserved 30:9 reserved. pio_state 8:6 current value on the pio(2:0) signal pins. pio signal pin mapping to reg- ister bits is: bit pio 8pio(2) 7pio(1) 6pio(0) pio_enable 5:3 0 controls pio(2:0) driver state. control values are: 0 driver is in tristate 1 driver is enabled. pio signal pin mapping to register bits is: bit pio 5pio(2) 4pio(1) 3pio(0) pio_write 2:0 0 value to be driven onto pio(2:0) signal pins when the corresponding driver is enabled. pio signal pin mapping to register bits is: bit pio 2pio(2) 1pio(1) 0pio(0) ibm powernp np2g network processor preliminary configuration page 500 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 13.35 ingress-to-egress wrap configuration registers these registers define the operating parameters for the iew function. 13.35.1 iew configuration 1 register (iew_config1) 13.35.2 iew configuration 2 register (iew_config2) access type read/write base address x?a000 0110? mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description mode 31:0 x'2003 1000' set the mode to x'a003 2000' for initialization. after initialization is complete (see section 13.7.2 initialization done reg- ister (init_done) on page 452), set the mode to x'a00b 2000', which is the operational state. access type read/write base address x?a002 0080? enable reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description enable 31:30 ?00? 00 disabled 11 enabled reserved 29:0 reserved. ibm powernp np2g preliminary network processor np2_ds_sec13_config.fm.01 february 12, 2003 configuration page 501 of 539 13.35.3 iew initialization register (iew_init) access type read/write base address x?a000 0210? enable reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field name bit(s) reset description enable 31 0 setting this field to ?1? begins the iew initialization. reserved 30:0 reserved. ibm powernp np2g network processor preliminary configuration page 502 of 539 np2_ds_sec13_config.fm.01 february 12, 2003 ibm powernp np2g preliminary network processor np2_ds_sec14_elec.fm.01 february 12, 2003 electrical and thermal specifications page 503 of 539 14. electrical and thermal specifications the np2g utilizes ibm cm os sa-27e technology. table 14-1. absolute maximum ratings symbol parameter rating units notes 1.8 v v dd power supply voltage 1.95 v 1 t a operating temperature (ambient) -40 to +100 c1 t j junction temperature -40 to +125 c1 t stg storage temperature -65 to +150 c1 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent dama ge to the device. this is a stress rating only and functional operation of the device at these or any other condi tions above those indicated in the operati onal sections of this specification is not im plied. exposure to absolute maximum rating conditions for extended periods may affect r eli- ability. table 14-2. input capacitance (pf) (t a = 25 c, f = 1 mhz, v dd = 3.3 v 0.3 v) (page 1 of 18) grid position signal name total incap a02 sch_addr(11) 11.31 a03 spare_tst_rcvr(2) 9.37 a04 sch_addr(02) 11.01 a05 iew_clk_b 8.67 a06 sch_data(08) 10.81 a07 sch_addr(00) 10.21 a08 sch_data(15) 10.31 a09 sch_data(07) 10.01 a10 sch_data(00) 9.91 a11 d4_addr(01) 9.81 a12 dd_ba(0) 10.01 a13 d4_data(31) 8.8 a14 d4_data(24) 8.5 a15 d4_data(19) 8.7 a16 d4_data(11) 8.5 a17 d4_data(04) 8.7 a18 ds1_data(26) 8.5 a19 ds1_data(19) 8.8 a20 ds1_data(14) 8.7 a21 ds1_data(06) 9 a22 ds1_data(00) 9.1 a23 ds0_addr(10) 10.21 ibm powernp np2g network processor preliminary electrical and thermal specifications page 504 of 539 np2_ds_sec14_elec.fm.01 february 12, 2003 a24 ds0_dqs(2) 9 a25 ds0_data(28) 9.2 a26 ds0_data(20) 9.5 a27 ds0_data(14) 9.5 a28 ds0_addr(00) 11.41 a29 ds0_data(09) 10 a30 ds0_data(13) 10.4 a31 ds0_cs 11.81 a32 ds0_data(01) 10.8 a33 ds0_data(03) 11.7 aa05 lu_addr(17) 7.31 aa06 lu_data(23) 7.71 aa07 lu_data(28) 7.51 aa08 lu_data(29) 7.01 aa09 lu_addr(00) 6.81 aa10 lu_addr(02) 6.31 aa11 lu_addr(18) 5.81 aa12 d0_data(00) 4.8 aa14 d0_addr(04) 6.11 aa16 d3_data(01) 5.1 aa17 d3_addr(06) 6.21 aa18 d2_data(03) 5 aa19 d2_addr(12) 6.21 aa20 da_ba(1) 6.1 aa22 jtag_tck 5.85 aa23 jtag_tdo 6.15 aa25 dmu_a(28) 7.05 aa26 dmu_a(27) 7.25 aa27 dmu_a(26) 7.15 aa28 dmu_a(25) 7.55 aa29 dmu_a(24) 7.85 aa30 dmu_a(23) 8.45 aa31 dmu_a(22) 8.95 aa32 dmu_a(21) 9.55 aa33 dmu_a(20) 9.95 ab05 lu_addr(14) 7.81 ab07 lu_addr(03) 7.51 table 14-2. input capacitance (pf) (t a = 25 c, f = 1 mhz, v dd = 3.3 v 0.3 v) (page 2 of 18) grid position signal name total incap ibm powernp np2g preliminary network processor np2_ds_sec14_elec.fm.01 february 12, 2003 electrical and thermal specifications page 505 of 539 ab09 lu_addr(16) 6.91 ab11 d0_data(03) 4.7 ab13 d0_data(28) 5 ab15 d0_addr(05) 6.11 ab19 d2_dqs(0) 5.1 ab21 d6_data(04) 5 ab23 c405_debug_halt 6.15 ab25 pci_ad(02) 8.55 ab27 pci_ad(01) 8.55 ab29 pci_ad(00) 9.75 ab31 dmu_a(30) 8.85 ab33 dmu_a(29) 9.95 ac01 lu_addr(07) 9.41 ac04 lu_addr(11) 8.41 ac08 lu_r_wrt 7.51 ac09 lu_addr(04) 7.01 ac11 d0_data(13) 5 ac12 d0_dqs(1) 5 ac14 d0_addr(10) 6.31 ac15 d0_data(29) 5.1 ac17 d3_dqs(1) 5.1 ac18 d3_addr(07) 6.41 ac20 d2_addr(05) 6.51 ac21 d6_data(10) 5.1 ac22 d6_data(15) 5.1 ac23 pci_bus_m_int 7.45 ac24 pci_ad(11) 8.15 ac25 pci_ad(10) 8.55 ac26 pci_ad(09) 8.45 ac27 pci_ad(08) 8.65 ac28 pci_cbe(0) 9.25 ac29 pci_ad(07) 9.65 ac30 pci_ad(06) 10.35 ac31 pci_ad(05) 10.45 ac32 pci_ad(04) 10.85 ac33 pci_ad(03) 11.35 ad07 lu_addr(12) 7.71 table 14-2. input capacitance (pf) (t a = 25 c, f = 1 mhz, v dd = 3.3 v 0.3 v) (page 3 of 18) grid position signal name total incap ibm powernp np2g network processor preliminary electrical and thermal specifications page 506 of 539 np2_ds_sec14_elec.fm.01 february 12, 2003 ad09 d0_data(01) 5.9 ad11 d0_data(23) 5.2 ad13 db_ba(1) 6.5 ad19 d3_we 6.81 ad21 d2_addr(06) 6.81 ad25 pci_cbe(1) 8.55 ad27 pci_ad(15) 9.45 ad29 pci_ad(14) 9.95 ad31 pci_ad(13) 10.65 ad33 pci_ad(12) 11.45 ae06 lu_addr(05) 8.61 ae07 lu_addr(06) 7.61 ae08 lu_addr(15) 7.71 ae09 d0_data(11) 5.9 ae10 d0_data(22) 5.9 ae11 d0_dqs(2) 5.8 ae13 db_ras 6.7 ae15 d3_data(03) 5.8 ae16 d3_data(09) 5.7 ae17 d2_data(08) 6.3 ae18 d3_addr(05) 7.11 ae19 d3_addr(12) 7.21 ae20 d2_data(07) 6 ae21 d2_data(09) 6 ae22 d6_data(14) 6 ae23 d6_data(09) 6.1 ae24 d6_addr(02) 7.3 ae25 mgrant_b(1) 7.15 ae26 pci_frame 8.75 ae27 pci_irdy 9.65 ae28 pci_trdy 10.25 ae29 pci_devsel 10.05 ae30 pci_stop 10.55 ae31 pci_perr 10.75 ae32 pci_serr 11.05 ae33 pci_par 11.55 af07 lu_addr(13) 7.91 table 14-2. input capacitance (pf) (t a = 25 c, f = 1 mhz, v dd = 3.3 v 0.3 v) (page 4 of 18) grid position signal name total incap ibm powernp np2g preliminary network processor np2_ds_sec14_elec.fm.01 february 12, 2003 electrical and thermal specifications page 507 of 539 af09 d0_data(20) 6.5 af11 d0_addr(12) 7.51 af15 d3_data(14) 6.1 af17 d3_addr(02) 7.01 af19 d3_data(15) 6.2 af21 d6_dqs_par(01) 6.3 af23 d6_byteen(1) 7.7 af25 d6_addr(04) 7.5 af27 pci_ad(17) 9.55 af29 pci_ad(16) 10.35 af31 pci_cbe(2) 11.15 af33 pci_clk 11.85 ag03 d0_data(09) 8 ag05 lu_addr(09) 10.01 ag06 lu_addr(10) 8.81 ag07 d0_data(02) 6.7 ag08 d0_data(21) 6.6 ag09 d0_dqs(0) 6.5 ag10 d0_addr(11) 7.71 ag11 db_ba(0) 6.4 ag13 d3_data(00) 6.5 ag14 d3_data(02) 6.5 ag15 d3_data(13) 6.4 ag16 d3_data(10) 6.4 ag17 d3_data(12) 6.2 ag18 d3_addr(04) 7.71 ag19 d3_addr(00) 7.71 ag20 d3_dqs(0) 6 ag21 d6_addr(11) 7.1 ag22 d2_data(10) 6.1 ag23 d2_addr(07) 7.61 ag24 d6_byteen(0) 8.2 ag25 da_ras 8.2 ag26 d6_addr(03) 8.3 ag27 mgrant_b(0) 8.25 ag28 pci_ad(23) 10.45 ag29 pci_ad(22) 11.65 table 14-2. input capacitance (pf) (t a = 25 c, f = 1 mhz, v dd = 3.3 v 0.3 v) (page 5 of 18) grid position signal name total incap ibm powernp np2g network processor preliminary electrical and thermal specifications page 508 of 539 np2_ds_sec14_elec.fm.01 february 12, 2003 ag30 pci_ad(21) 10.95 ag31 pci_ad(20) 11.05 ag32 pci_ad(19) 11.75 ag33 pci_ad(18) 11.85 ah05 de_ba(1) 8.61 ah07 d0_data(10) 7.7 ah09 d0_dqs(3) 6.7 ah17 d3_data(11) 6.1 ah19 db_clk 7.4 ah21 d2_addr(01) 7.71 ah23 d2_addr(04) 8.01 ah25 d6_data(08) 7.3 ah27 d6_addr(12) 9.6 ah29 pci_ad(24) 10.25 ah31 pci_cbe(3) 11.65 ah33 pci_idsel 12.45 aj03 lu_clk 9.51 aj04 de_clk 9 aj05 de_clk 8.7 aj06 d0_data(14) 8.6 aj07 d0_data(16) 7.4 aj08 d0_data(31) 7.2 aj09 d0_addr(02) 8.31 aj12 db_cas 7.8 aj16 d3_addr(01) 7.61 aj17 d3_addr(03) 7.81 aj18 db_clk 7.4 aj19 d2_data(01) 6.8 aj20 d2_data(04) 6.9 aj21 d2_data(14) 7.1 aj22 d2_addr(00) 8.41 aj23 d2_addr(11) 8.61 aj24 d2_we 8.61 aj25 d6_we 8.7 aj26 d6_data(12) 7.9 aj27 d6_addr(07) 9.1 aj28 d6_addr(09) 10.4 table 14-2. input capacitance (pf) (t a = 25 c, f = 1 mhz, v dd = 3.3 v 0.3 v) (page 6 of 18) grid position signal name total incap ibm powernp np2g preliminary network processor np2_ds_sec14_elec.fm.01 february 12, 2003 electrical and thermal specifications page 509 of 539 aj29 pci_ad(29) 10.65 aj30 pci_ad(28) 10.95 aj31 pci_ad(27) 11.35 aj32 pci_ad(26) 12.15 aj33 pci_ad(25) 12.25 ak03 de_ras 9.91 ak05 d0_data(15) 8 ak07 d0_data(30) 8.1 ak15 d3_data(07) 7.3 ak17 d3_addr(11) 8.11 ak19 d3_addr(08) 8.71 ak21 d2_data(13) 7.5 ak23 d2_addr(10) 8.81 ak25 d2_dqs(1) 8.3 ak27 d6_data(13) 8.7 ak29 d6_addr(08) 9.8 ak31 pci_ad(31) 11.65 ak33 pci_ad(30) 12.95 al01 spare_tst_rcvr(4) 8.25 al02 de_cas 10.61 al03 d0_data(12) 9.2 al04 d0_data(08) 8.8 al05 iew_clk_a 7.87 al06 d0_data(26) 8.5 al07 d0_data(19) 8.2 al08 d0_addr(07) 9.11 al09 d0_data(25) 7.7 al10 d0_addr(00) 9.01 al11 d0_addr(09) 6.61 al15 d3_data(06) 5.1 al17 d3_data(04) 7.5 al18 d3_cs 8.91 al19 d3_addr(09) 9.11 al20 d2_data(05) 7.7 al21 d2_addr(09) 8.91 al22 d2_cs 9.21 al23 d6_data(00) 7.9 table 14-2. input capacitance (pf) (t a = 25 c, f = 1 mhz, v dd = 3.3 v 0.3 v) (page 7 of 18) grid position signal name total incap ibm powernp np2g network processor preliminary electrical and thermal specifications page 510 of 539 np2_ds_sec14_elec.fm.01 february 12, 2003 al24 d6_data(07) 8.3 al25 da_clk 9.2 al26 d6_data(02) 8.4 al27 d6_addr(05) 9.8 al28 d6_addr(00) 10.2 al29 d6_addr(10) 10.3 al30 d6_dqs(0) 9.5 al31 d6_cs 11 al32 pci_grant 12.35 al33 pci_request 13.05 am01 de_ba(0) 11.31 am03 d0_data(05) 9.5 am05 d0_data(27) 9.4 am07 d0_addr(06) 9.91 am09 d0_we 9.71 am11 d0_addr(08) 9.51 am17 d3_data(05) 8.2 am19 d2_data(12) 8 am21 d2_addr(03) 9.41 am23 d6_data(01) 8.6 am25 da_clk 9.9 am27 d6_data(03) 9.3 am29 d6_parity(00) 10 am31 d6_dqs(3) 10.2 am33 pci_inta 13.05 an01 d0_data(06) 9.3 an02 d0_data(04) 10.1 an03 d0_data(07) 9.9 an04 d0_data(17) 9.8 an05 iew_clk_a 7.77 an06 d0_addr(03) 10.81 an07 d0_data(18) 9 an08 d0_data(24) 9.1 an09 d0_cs 9.41 an10 d0_addr(01) 9.91 an17 d3_addr(10) 9.91 an18 d2_data(00) 8.5 table 14-2. input capacitance (pf) (t a = 25 c, f = 1 mhz, v dd = 3.3 v 0.3 v) (page 8 of 18) grid position signal name total incap ibm powernp np2g preliminary network processor np2_ds_sec14_elec.fm.01 february 12, 2003 electrical and thermal specifications page 511 of 539 an19 d2_data(06) 8.8 an20 d2_data(11) 8.7 an21 d2_addr(02) 10.21 an22 d2_addr(08) 10.31 an23 d6_parity(01) 9 an24 d6_data(06) 9 an25 d6_data(11) 9.2 an26 d6_addr(01) 10.5 an27 da_cas 10.5 an28 d6_data(05) 10.2 an29 da_ba(0) 11 an30 d6_addr(06) 11.4 an31 d6_dqs(1) 10.6 an32 d6_dqs_par(00) 10.8 an33 d6_dqs(2) 11.7 b01 sch_addr(16) 11.31 b03 sch_addr(13) 10.71 b05 sch_addr(01) 10.61 b07 d4_addr(12) 9.91 b09 sch_data(06) 9.71 b11 d4_addr(07) 9.51 b13 dd_clk 9 b15 d4_data(25) 8 b17 ds1_dqs(0) 8.2 b19 ds1_data(13) 8 b21 ds1_data(05) 8.2 b23 ds0_addr(05) 9.81 b25 ds0_data(29) 8.9 b27 ds0_addr(03) 10.51 b29 ds0_data(23) 10 b31 ds0_data(02) 10.2 b33 clock125 11.65 c01 sch_addr(17) 11.31 c02 sch_addr(14) 10.61 c03 sch_addr(09) 10.41 c04 sch_addr(12) 10.01 c05 iew_clk_b 7.87 table 14-2. input capacitance (pf) (t a = 25 c, f = 1 mhz, v dd = 3.3 v 0.3 v) (page 9 of 18) grid position signal name total incap ibm powernp np2g network processor preliminary electrical and thermal specifications page 512 of 539 np2_ds_sec14_elec.fm.01 february 12, 2003 c06 sch_data(12) 9.71 c07 sch_clk 9.41 c08 d4_addr(09) 9.11 c09 sch_data(14) 8.91 c10 sch_data(01) 9.01 c11 d4_addr(06) 8.81 c12 d4_addr(00) 8.91 c13 dd_clk 8.4 c14 d4_data(17) 7.6 c15 d4_data(03) 7.7 c16 d4_data(10) 7.7 c17 ds1_we 8.61 c18 ds1_data(27) 7.7 c19 ds1_dqs(1) 7.9 c20 ds1_data(21) 7.7 c21 dc_ras 8.7 c22 ds0_addr(11) 9.21 c23 ds0_addr(06) 9.11 c24 ds0_dqs(1) 8.3 c25 ds0_data(21) 8.2 c26 ds0_addr(04) 9.61 c27 ds0_data(15) 8.8 c28 ds0_data(22) 9.2 c29 ds0_data(08) 9.3 c30 ds0_data(04) 9.5 c31 ds0_data(05) 10 c32 operational 10.95 c33 core_clock 11.65 d03 sch_addr(15) 9.91 d05 sch_addr(10) 9.21 d07 sch_data(13) 9.31 d09 d4_addr(08) 8.91 d11 d4_dqs(0) 7.2 d13 d4_data(26) 7.2 d15 d4_data(02) 7.3 d17 d4_data(05) 7 d19 ds1_dqs(2) 7.5 table 14-2. input capacitance (pf) (t a = 25 c, f = 1 mhz, v dd = 3.3 v 0.3 v) (page 10 of 18) grid position signal name total incap ibm powernp np2g preliminary network processor np2_ds_sec14_elec.fm.01 february 12, 2003 electrical and thermal specifications page 513 of 539 d21 ds1_data(12) 7.5 d23 dc_clk 8.6 d25 dc_ba(0) 9.3 d27 ds0_data(26) 8.7 d29 ds0_data(11) 8.8 d31 dmu_d(01) 10.25 d33 dmu_d(00) 11.55 e03 spare_tst_rcvr(1) 7.81 e04 sch_addr(05) 9.21 e05 sch_addr(18) 8.91 e06 sch_addr(03) 9.81 e07 sch_addr(04) 8.61 e08 sch_data(09) 8.41 e09 d4_data(18) 7.1 e10 d4_cs 8.11 e11 d4_dqs(1) 6.9 e12 d4_data(29) 6.8 e13 d4_data(27) 6.8 e14 d4_data(16) 6.7 e15 d4_data(12) 6.7 e16 ds1_cs 7.61 e17 ds1_addr(03) 7.81 e18 ds1_data(20) 6.4 e19 ds1_data(25) 6.8 e20 ds1_data(22) 6.9 e21 ds1_data(11) 7.1 e22 ds1_data(08) 7.2 e23 dc_clk 8.4 e24 ds0_addr(12) 8.61 e25 ds0_dqs(3) 7.7 e26 ds0_data(27) 7.9 e27 ds0_data(12) 8.1 e28 ds0_data(10) 9.4 e29 reset 9.25 e30 dmu_d(04) 9.55 e31 dmu_d(29) 9.95 e32 dmu_d(12) 10.75 table 14-2. input capacitance (pf) (t a = 25 c, f = 1 mhz, v dd = 3.3 v 0.3 v) (page 11 of 18) grid position signal name total incap ibm powernp np2g network processor preliminary electrical and thermal specifications page 514 of 539 np2_ds_sec14_elec.fm.01 february 12, 2003 f05 sch_addr(07) 8.61 f07 sch_addr(08) 8.91 f09 sch_data(02) 7.91 f11 d4_we 7.51 f13 d4_data(30) 6.2 f15 d4_data(13) 6.2 f17 ds1_addr(10) 7.31 f19 ds1_data(24) 6.4 f21 ds1_data(07) 6.5 f23 ds1_data(04) 6.8 f25 ds0_dqs(0) 7.3 f27 ds0_data(06) 8.6 f29 dmu_d(07) 8.85 f31 dmu_d(06) 10.25 f33 dmu_d(05) 11.05 g03 spare_tst_rcvr(5) 7.51 g05 sch_r_wrt 10.01 g06 sch_data(10) 8.81 g07 sch_data(11) 7.91 g08 sch_data(17) 7.81 g09 sch_data(05) 7.71 g10 d4_addr(04) 7.71 g11 dd_cas 7.81 g12 d4_data(22) 6.4 g13 d4_data(08) 6.5 g14 d4_data(07) 6.5 g15 ds1_addr(08) 7.61 g16 ds1_addr(11) 7.61 g17 ds1_addr(09) 7.41 g18 ds1_addr(02) 7.71 g19 ds1_addr(05) 7.71 g20 ds1_data(30) 6 g21 ds1_data(29) 6.1 g22 ds1_data(15) 6.1 g23 ds1_data(01) 6.4 g24 ds0_addr(07) 8.41 g25 ds0_data(30) 7.2 table 14-2. input capacitance (pf) (t a = 25 c, f = 1 mhz, v dd = 3.3 v 0.3 v) (page 12 of 18) grid position signal name total incap ibm powernp np2g preliminary network processor np2_ds_sec14_elec.fm.01 february 12, 2003 electrical and thermal specifications page 515 of 539 g26 ds0_data(17) 7.3 g27 pci_bus_nm_int 9.65 g28 dmu_d(02) 9.05 g29 dmu_d(11) 10.25 g30 dmu_d(10) 9.55 g31 dmu_d(30) 9.65 g32 dmu_d(08) 10.35 h07 sch_addr(06) 7.91 h09 d4_data(06) 6.5 h11 d4_addr(03) 7.51 h13 d4_data(23) 6 h15 ds1_addr(07) 7.31 h17 ds1_addr(04) 7.11 h19 ds1_addr(06) 7.41 h21 ds0_data(07) 6.3 h23 ds0_addr(08) 7.91 h25 ds0_data(16) 6.5 h27 dmu_d(16) 8.15 h29 dmu_d(15) 8.95 h31 dmu_d(14) 9.75 h33 dmu_d(13) 10.45 j06 mg_data 7.88 j07 mg_clk 7.28 j08 mg_nintr 6.98 j10 sch_data(16) 7.11 j11 sch_data(03) 7.01 j12 d4_addr(02) 6.91 j13 dd_ba(1) 6.91 j14 d4_data(21) 5.7 j15 ds1_data(17) 5.8 j16 ds1_addr(12) 6.91 j17 dc_ba(1) 6.9 j18 ds1_addr(01) 7.11 j19 ds1_data(31) 6 j20 ds1_data(18) 6 j21 ds1_data(16) 6 j22 ds0_addr(09) 7.21 table 14-2. input capacitance (pf) (t a = 25 c, f = 1 mhz, v dd = 3.3 v 0.3 v) (page 13 of 18) grid position signal name total incap ibm powernp np2g network processor preliminary electrical and thermal specifications page 516 of 539 np2_ds_sec14_elec.fm.01 february 12, 2003 j23 ds0_we 7.31 j24 ds0_data(18) 6.3 j25 dmu_d(25) 7.15 j26 dmu_d(24) 7.35 j27 dmu_d(23) 8.35 j28 dmu_d(22) 8.85 j29 dmu_d(03) 8.65 j30 dmu_d(20) 9.15 j31 dmu_d(19) 9.35 j32 dmu_d(18) 9.65 j33 dmu_d(17) 10.15 k07 boot_picocode 6.98 k13 dd_ras 6.71 k15 d4_data(09) 5.4 k19 ds1_data(28) 5.6 k21 ds1_data(02) 5.6 k23 ds0_data(19) 5.5 k25 dmu_d(09) 7.15 k27 dmu_d(21) 8.05 k29 dmu_d(28) 8.55 k31 dmu_d(27) 9.25 k33 dmu_d(26) 10.05 l04 boot_ppc 7.68 l12 sch_data(04) 6.21 l13 d4_addr(05) 6.31 l15 d4_data(20) 5.1 l16 d4_data(01) 5.1 l17 ds1_data(10) 5.2 l18 ds1_data(09) 5.2 l19 ds0_data(25) 5.2 l20 ds1_data(03) 5.3 l22 ds0_data(31) 5.1 l23 dmu_c(10) 6.05 l24 dmu_c(09) 6.75 l25 dmu_c(08) 7.15 l26 dmu_c(07) 7.05 l27 dmu_c(06) 7.25 table 14-2. input capacitance (pf) (t a = 25 c, f = 1 mhz, v dd = 3.3 v 0.3 v) (page 14 of 18) grid position signal name total incap ibm powernp np2g preliminary network processor np2_ds_sec14_elec.fm.01 february 12, 2003 electrical and thermal specifications page 517 of 539 l28 dmu_c(05) 7.85 l29 dmu_c(04) 8.25 l30 dmu_c(03) 8.95 l31 dmu_c(02) 9.05 l32 dmu_c(01) 9.45 l33 dmu_c(00) 9.95 m07 pci_speed 6.78 m13 d4_addr(10) 6.21 m15 d4_dqs(3) 4.9 m17 d4_data(00) 4.9 m19 ds0_addr(02) 6.31 m21 ds0_data(24) 5 m23 dmu_c(16) 6.15 m25 dmu_c(15) 7.15 m27 dmu_c(14) 7.15 m29 dmu_c(13) 8.35 m31 dmu_c(12) 8.85 m33 dmu_c(11) 9.95 n06 pio(2) 12.51 n07 cam_cp_response(13) 8.31 n08 pio(1) 12.31 n09 pio(0) 7.11 n14 d4_addr(11) 6.11 n15 d4_dqs(2) 5 n16 d4_data(15) 5.1 n17 ds1_addr(00) 6.31 n18 ds1_data(23) 5 n19 dc_cas 6 n20 ds0_addr(01) 6.31 n23 dmu_c(27) 6.15 n24 dmu_c(26) 6.55 n25 dmu_c(25) 7.05 n26 dmu_c(24) 7.25 n27 dmu_c(23) 7.15 n28 dmu_c(22) 7.55 n29 dmu_c(21) 7.85 n30 dmu_c(20) 8.45 table 14-2. input capacitance (pf) (t a = 25 c, f = 1 mhz, v dd = 3.3 v 0.3 v) (page 15 of 18) grid position signal name total incap ibm powernp np2g network processor preliminary electrical and thermal specifications page 518 of 539 np2_ds_sec14_elec.fm.01 february 12, 2003 n31 dmu_c(19) 8.95 n32 dmu_c(18) 9.55 n33 dmu_c(17) 9.95 p05 cam_cp_response(2) 9.91 p07 cam_cp_response(5) 9.31 p09 cam_cp_response(9) 7.41 p15 d4_data(28) 5.2 p19 ds0_data(00) 5.3 p29 dmu_c(30) 8.15 p31 dmu_c(29) 8.75 p33 dmu_c(28) 9.85 r01 cam_cp_response(7) 11.51 r04 lu_addr(08) 8.01 r05 lu_data(33) 7.51 r06 cam_cp_response(3) 8.51 r07 lu_data(04) 7.21 r08 lu_data(05) 6.81 r09 cam_cp_response(10) 6.61 r10 cam_cp_response(8) 6.01 r13 cam_cp_response(12) 5.31 r14 cam_cp_response(11) 5.21 r17 d4_data(14) 5.6 r18 ds1_dqs(3) 5.6 t01 spare_tst_rcvr(3) 7.52 t03 spare_tst_rcvr(8) 6.61 t05 cam_cp_response(6) 11.91 t07 lu_data(03) 7.21 t09 lu_data(02) 6.61 t11 cam_cp_response(1) 5.71 t13 cam_cp_response(4) 4.51 t15 lu_data(24) 7.21 t19 send_grant_b 5.95 t21 res_data 5.55 t25 jtag_trst 6.85 u01 lu_data(30) 9.41 u03 lu_data(35) 8.11 u05 spare_tst_rcvr(0) 5.47 table 14-2. input capacitance (pf) (t a = 25 c, f = 1 mhz, v dd = 3.3 v 0.3 v) (page 16 of 18) grid position signal name total incap ibm powernp np2g preliminary network processor np2_ds_sec14_elec.fm.01 february 12, 2003 electrical and thermal specifications page 519 of 539 u06 testmode(1) 5.78 u08 lu_data(08) 6.61 u09 cam_cp_response(0) 9.91 u10 lu_data(34) 6.21 u12 lu_data(11) 6.11 u13 lu_data(01) 6.41 u15 lu_data(00) 7.11 u19 mgrant_a(1) 5.95 u21 res_sync 5.55 u22 jtag_tms 5.75 u33 spare_tst_rcvr(9) 8.12 v01 spare_tst_rcvr(6) 7.51 v03 spare_tst_rcvr(7) 6.58 v05 testmode(0) 5.98 v07 lu_data(09) 7.21 v09 lu_data(10) 6.61 v11 lu_data(14) 5.91 v13 lu_data(18) 6.41 v15 lu_data(12) 7.21 v19 mgrant_a(0) 5.95 v21 i_freeq_th 5.55 v27 dmu_a(02) 6.95 v29 dmu_a(01) 7.65 v31 dmu_a(00) 8.95 w01 lu_data(20) 9.41 w04 lu_data(13) 8.01 w05 lu_data(07) 7.51 w06 lu_data(06) 7.71 w07 lu_data(15) 7.21 w08 lu_data(16) 6.81 w09 lu_data(21) 6.51 w10 lu_data(25) 6.31 w11 lu_data(31) 5.81 w12 lu_data(26) 6.01 w13 lu_data(19) 6.41 w14 lu_data(27) 6.81 w17 d3_data(08) 5.7 table 14-2. input capacitance (pf) (t a = 25 c, f = 1 mhz, v dd = 3.3 v 0.3 v) (page 17 of 18) grid position signal name total incap ibm powernp np2g network processor preliminary electrical and thermal specifications page 520 of 539 np2_ds_sec14_elec.fm.01 february 12, 2003 w18 d2_data(02) 5.6 w20 send_grant_a 5.65 w22 jtag_tdi 5.85 w23 dmu_a(13) 6.15 w24 dmu_a(12) 6.55 w25 dmu_a(11) 6.85 w26 dmu_a(10) 7.15 w27 dmu_a(09) 6.95 w28 dmu_a(08) 7.55 w29 dmu_a(07) 8.15 w30 dmu_a(06) 8.55 w31 dmu_a(05) 8.95 w32 dmu_a(04) 9.45 w33 dmu_a(03) 9.95 y05 lu_data(32) 7.51 y07 lu_data(17) 7.41 y09 lu_data(22) 6.81 y11 lu_addr(01) 5.81 y19 d2_data(15) 5.3 y23 dmu_a(19) 6.15 y25 dmu_a(18) 6.95 y27 dmu_a(17) 7.15 y29 dmu_a(16) 8.15 y31 dmu_a(15) 8.75 y33 dmu_a(14) 9.85 table 14-2. input capacitance (pf) (t a = 25 c, f = 1 mhz, v dd = 3.3 v 0.3 v) (page 18 of 18) grid position signal name total incap ibm powernp np2g preliminary network processor np2_ds_sec14_elec.fm.01 february 12, 2003 electrical and thermal specifications page 521 of 539 table 14-3. operating supply voltages symbol parameter rating units notes min typ max v dd25 v dd3 v dd4 v dd5 2.5 v power supply 2.375 2.5 2.625 v 1 v dd33 v dd2 3.3 v power supply 3.135 3.3 3.465 v 1 v dd 1.8 v power supply 1.71 1.8 1.89 v 1 plla_v dd pllb_v dd pllc_v dd pll voltage reference 1.71 1.8 1.89 v 1, 2 v ref1(2-0) v ref2(8-0) sstl2 power supply (used for sstl2 i/o) 1.1875 1.25 1.3125 v 1 1. important power sequencing requi rements: (the following conditions must be me t at all times, incl uding power-up and power-dow n: v ref *(1.25 v reference) v dd25 +0.4 v pll*_v dd (2.5 v reference) v dd33 +0.4 v v dd18 v dd25 + 0.4 v v dd25 v dd33 + 0.4 v v dd33 v dd25 + 1.9 v v dd33 v dd18 + 2.7 v 2. see also pll filter circuit on page 80. table 14-4. operating supply currents power supply min nominal max units 1.8 v 3.20 a 2.5 v 0.46 a 3.3 v 0.08 a table 14-5. thermal characteristics thermal characteristic min nominal max units estimated power dissipation 7.3 8.6 w operating junction temperature (tj) 1 0 105 c 1. operation up to t j = 125 c is supported for up to 3600 hours. however, the electromigration (em) limit must not exceed 105 c for 88 kpoh equivalent. contact your ibm field applications engineer for em equivalents. ibm powernp np2g network processor preliminary electrical and thermal specifications page 522 of 539 np2_ds_sec14_elec.fm.01 february 12, 2003 14.1 driver specifications table 14-6. definition of terms term definition maul maximum allowable up level. the maximum voltage that can be applied without affecting the specified reliability. cell functionality is not implied. maximu m allowable applies to overshoot only. mpul maximum positive up level. the most positive voltage that ma intains cell functionality. the maximum positive logic level. lpul least positive up level. the least positive voltage that ma intains cell functionality. the minimum positive logic level. mpdl most positive down level. the most positive voltage that maintains cell functionality. the maximum negative logic level. lpdl least positive down level. the least pos itive voltage that maintains cell functi onality. the minimu m negative logic level. madl minimum allowable down level. the minimum voltage that can be applied without affecting the specified reliability. mini- mum allowable applies to undershoot only. cell functionality is not implied. table 14-7. 1.8 v cmos driver dc voltage specifications function maul (v) 1 mpul (v) lpul (v) mpdl (v) lpdl (v) madl (v) 2 cmos v dd 3 + 0.45 v dd 3 v dd 3 - 0.45 0.45 0.00 -0.60 1. maximum allowable applies to overshoot only. 2. minimum allowable applies to undershoot only. 3. v dd ranges as specified in table 14-3 (typical = 1.8 v). table 14-8. 1.8 v cmos driver minimum dc currents at rated voltage v dd = 1.65 v, t = 100c driver type v high (v) i high (ma) v low (v) i low (ma) cmos 50 ohm driver outputs 1.2 8.0/23.0 1 0.45 7.8 1 1. 23 ma is the electromigration limi t for 100k power on hours (poh) = 100 c and 100% duty cycle. this limit can be adjusted for dif- ferent temperature, duty cycle, and poh. consult your ibm application engi neer for further details. table 14-9. 2.5 v cmos driver dc voltage specifications function maul (v) 1 mpul (v) lpul (v) mpdl (v) lpdl (v) madl (v) 2 cmos v dd 3 + 0.6 v dd 3 2.0 0.4 0.00 -0.60 1. maximum allowable applies to overshoot only. 2. minimum allowable applies to undershoot only. 3. v dd ranges as specified in table 14-3 (typical = 2.5 v). table 14-10. 2.5 v cmos driver minimum dc currents at rated voltage v dd = 2.3 v, t = 100c driver type v high (v) i high (ma) v low (v) i low (ma) cmos 50 ohm driver outputs 2.0 5.2/23 1 0.4 6.9 1 1. 23 ma is the electromigration limi t for 100k power on hours (poh) = 100 c and 100% duty cycle. this limit can be adjusted for dif- ferent temperature, duty cycle, and poh. consult your ibm application engi neer for further details. ibm powernp np2g preliminary network processor np2_ds_sec14_elec.fm.01 february 12, 2003 electrical and thermal specifications page 523 of 539 table 14-11. 3.3 v-tolerant 2.5 v cmos driver dc voltage specifications (see note 1) function maul (v) 2 mpul (v) 3 lpul (v) mpdl (v) lpdl (v) madl (v) 4 lvttl 3.9 v dd 5 2.0 0.4 0.00 -0.60 1. all levels adhere to the jedec standard jesd12-6, ?interfa ce standard for semi-custom in tegrated circui ts,? march 1991. 2. maximum allowable applies to overshoot only. output disabled. 3. output active. 4. minimum allowable applies to undershoot only. 5. v dd ranges as specified in table 14-3 (typical = 2.5 v). table 14-12. 3.3 v lvttl driver dc voltage specifications function maul (v) 1 mpul (v) lpul (v) mpdl (v) lpdl (v) madl (v) 2 lvttl v dd330 3 + 0.3 v dd330 3 2.4 0.4 0.00 -0.60 1. maximum allowable applies to overshoot only. 2. minimum allowable applies to undershoot only. 3. v dd 33 ranges as specified in table 14-3 (typical = 3.3 v). table 14-13. 3.3 v lvttl/5.0 v-tolerant driver dc voltage specifications function maul (v) 1 mpul (v) lpul (v) mpdl (v) lpdl (v) madl (v) 2 lvttl v dd330 3 + 0.3 v dd330 3 2.4 0.4 0.00 -0.60 1. maximum allowable applies to overshoot only. 2. minimum allowable applies to undershoot only. 3. v dd 33 ranges as specified in table 14-3 (typical = 3.3 v). table 14-14. 3.3 v lvttl driver mini mum dc currents at rated voltage (v dd = 3.0 v, t = 100c) driver type v high (v) i high (ma) v low (v) i low (ma) lvttl 50 ohm driver outputs 2.40 10.3/23 1 0.4 7.1 1 1. 23 ma is the electromigration limit for 100k power on hours (poh) = 100c and 100% duty cycle. this limit can be adjusted for dif- ferent temperature, duty cycle, and poh. consult your ibm application engi neer for further details. ibm powernp np2g network processor preliminary electrical and thermal specifications page 524 of 539 np2_ds_sec14_elec.fm.01 february 12, 2003 14.2 receiver specifications table 14-15. 1.8 v cmos receiver dc voltage specifications function maul (v) 1 mpul (v) lpul (v) mpdl (v) lpdl (v) madl (v) 2 cmos v dd 3 + 0.45 v dd 3 0.65 v dd 3 0.35 v dd 3 0.00 -0.60 1. maximum allowable applies to overshoot only. 2. minimum allowable applies to undershoot only. 3. v dd ranges as specified in table 14-3 (typical = 1.8 v). table 14-16. 2.5 v cmos receiver dc voltage specifications function maul (v) 1 mpul (v) lpul (v) mpdl (v) lpdl (v) madl (v) 2 cmos v dd 3 + 0.6 v dd 1.7 0.70 0.00 -0.60 1. maximum allowable applies to overshoot only. 2. minimum allowable applies to undershoot only. 3. v dd ranges as specified in table 14-3 (typical = 2.5 v). table 14-17. 3.3 v lvttl receiver dc voltage specifications function maul (v) 1 mpul (v) lpul (v) mpdl (v) lpdl (v) madl (v) 2 lvttl v dd330 3 + 0.3 v dd330 3 2.00 0.80 0.00 -0.60 1. maximum allowable applies to overshoot only. 2. minimum allowable applies to undershoot only. 3. v dd 33 ranges as specified in table 14-3 (typical = 3.3 v). table 14-18. 3.3 v lvttl / 5 v tolerant receiver dc volta ge specifications function maul (v) 1 mpul (v) lpul (v) mpdl (v) lpdl (v) madl (v) 2 lvttl 5.5 v 5.5 v 2.00 0.80 0.00 -0.60 1. maximum allowable applies to overshoot only. 2. minimum allowable applies to undershoot only. table 14-19. receiver maximum input leakage dc current input specifications function i il ( a) i ih ( a) without pull-up element or pull-down element -25 at v in = lpdl 25 at v in = mpul with pull-down element -25 at v in = lpdl 200 at v in = mpul with pull-up element -150 at v in = lpdl 25 at v in = mpul 1. see section 3.3 v lvttl / 5 v tolerant bp33 and ip33 receiver input current/voltage curve on page 525 . ibm powernp np2g preliminary network processor np2_ds_sec14_elec.fm.01 february 12, 2003 electrical and thermal specifications page 525 of 539 figure 14-1. 3.3 v lvttl / 5 v tolerant bp33 and ip33 receiver input current/voltage curve 1. curve shows best case process - 0c, 3.6v 0.00 - 50.00 -100.00 -150.00 -200.00 -250.00 -300.00 0.00 0.50 1.00 1.50 2.50 3.00 i pad ( a) v pad (v) 2.00 ibm powernp np2g network processor preliminary electrical and thermal specifications page 526 of 539 np2_ds_sec14_elec.fm.01 february 12, 2003 14.3 other driver and receiver specifications table 14-20. lvds receiver dc specifications symbol parameter min nom max units comments v dd device supply voltage 1.65 1.8 1.95 v receiver uses only v dd supply. temp temperature range 0 50 100 c rec pwr input buffer power 9.3 mw including on-chip terminator v pad - v padn = 0.4 v v ih receiver input voltage v dd + 0.20 v receiver esd connected to v dd v il receiver input voltage -0.20 v v ih - v il receiver input voltage range 100 mv @600 mhz v icm receiver common mode range 0 1.25 v dd v ri input impedance 80 100 120 ? notes: 1. all dc characteristic s are based on power supply and temper ature ranges as specified above. 2. this receiver using a v dd of 1.8 v nominal is compatible with the 1.5 v spec ification described in the lvds standard: ieee stan- dard for low-voltage differential signal s (lvds) for scalable coherent interface (sci), ieee standard 1596.3,1996. 3. maximum frequency is load and package dependent. 600 mhz (1.2 gbps ) is achievable with a minimum of 100 mv input swing over the wide common range as specified. t he customer is responsible for determining optimal frequency and switching capabili- ties through thorough simulation and analysis. table 14-21. sstl2 dc specifications (page 1 of 2) symbol parameter min nom max units comments v dd device supply voltage 1.65 1.8 1.95 v v ddq output supply voltage 2.3 2.5 2.7 v v ddq = v dd250 v tt termination voltage 1.11 - 1.19 1.25 1.31 - 1.39 v 0.5*v ddq v ref differential input reference voltage 1.15 1.25 1.35 v 0.5*v ddq v oh (class ii) output high voltage 1.95 v i oh = 15.2 ma @ 1.95 v v ol (class ii) output low voltage 0.55 v i ol = 15.2 ma @ 0.55 v r oh max (class ii) max pull-up impedance 36.2 ? notes: 1. all sstl2 specifications are c onsistent with jedec committee re -ballot (jc-16-97-58a), 10/14/97. 2. di/dt and performance are chosen by performance level selection (a and b). a. performance level a is targeted to run at 200 mhz or faster depending on loading conditions. di/dt is comparable to 110 ma/ns 2.5 v/3.3 v lvttl driver. b. performance level b is targeted to run at 250 mhz or faster depending on loading conditions. di/dt is comparable to 150 ma/ns 2.5 v/3.3 v lvttl driver. 3. the differential input reference supply (v ref ) is brought on chip through vsstl2r1 and vsstl2r2 i/o cells. 4. termination voltage (v tt ) is generated off-chip. 5. sstl2 driver is rated at 20 ma @100c and 50% duty cycle for 100k power on hours (poh). ibm powernp np2g preliminary network processor np2_ds_sec14_elec.fm.01 february 12, 2003 electrical and thermal specifications page 527 of 539 r ol max (class ii) max pull-down impedance 36.2 ? v ih input high voltage v ref + 0.18 v ddq + 0.3 v v il input low voltage -0.3 v ref - 0.18 v i oz 3-state leakage current 010 a driver hi-z temp temperature 050100c table 14-21. sstl2 dc specifications (page 2 of 2) symbol parameter min nom max units comments notes: 1. all sstl2 specifications are c onsistent with jedec committee re -ballot (jc-16-97-58a), 10/14/97. 2. di/dt and performance are chosen by performance level selection (a and b). a. performance level a is targeted to run at 200 mhz or faster depending on loading conditions. di/dt is comparable to 110 ma/ns 2.5 v/3.3 v lvttl driver. b. performance level b is targeted to run at 250 mhz or faster depending on loading conditions. di/dt is comparable to 150 ma/ns 2.5 v/3.3 v lvttl driver. 3. the differential input reference supply (v ref ) is brought on chip through vsstl2r1 and vsstl2r2 i/o cells. 4. termination voltage (v tt ) is generated off-chip. 5. sstl2 driver is rated at 20 ma @100c and 50% duty cycle for 100k power on hours (poh). ibm powernp np2g network processor preliminary electrical and thermal specifications page 528 of 539 np2_ds_sec14_elec.fm.01 february 12, 2003 ibm powernp np2g preliminary network processor np2_ds_sec15_glos.fm.01 february 12, 2003 glossary of terms and abbreviations page 529 of 539 15. glossary of terms and abbreviations term definition alu arithmetic and logic unit api application programming interface arb arbitration ardl advance rope with optional delete leaf arp address resolution protocol ath actual threshold bcb buffer control block bci byte count information beb binary exponential back-off bfq buffer free queue bgp border gateway protocol bird an intermediate leaf. it occurs when the pscbline contains an intermediate lcba pointing to this leaf and an npa pointing to the next pscb. bl burst length bsm-ccga bottom surface metallurgy - ceramic column grid array byte 8 bits cab control access bus cba control block address cdm cell data mover chap challenge-handshake authentication protocol cia common instruction address clns connectionless-mode network service clp see core language processor. core language processor (clp) the picoprocessor core, also referred to as coprocessor 0. the clp executes the base instruction set and controls thread swapping and instruction fetching. cp control point cpf control point function cpix common programming interface ibm powernp np2g network processor preliminary glossary of term s and abbreviations page 530 of 539 np2_ds_sec15_glos.fm.01 february 12, 2003 crc see cyclic redundancy check. cs control store csa control store arbiter cyclic redundancy check (crc) a system of error checking performed at both the sending and receiving station after a block-check character has been accumulated. da destination address dashboard a section of the scalar register space in the epc where all threads can access a copy of a master value. data store in the network processor, the place where a frame is stored while waiting for processing or forwarding to its destination. dbgs debug services ddr double data rate diffserv differentiated services distinguishing position (distpos) the index value of a first mismatch bit between the input key and the reference key found in a leaf pattern distpos see distinguishing position (distpos). dlq discard list queue dmu data mover unit doubleword 2 words dppu dyadic protocol processor unit dq discard queue dram dynamic random-access memory ds see data store. dscp diffserv code point dsi distributed software interface dt direct table dvmrp distance vector mu lticast routing protocol e- egress ecc error correcting code ecmp equal-cost multipath term definition ibm powernp np2g preliminary network processor np2_ds_sec15_glos.fm.01 february 12, 2003 glossary of terms and abbreviations page 531 of 539 eds enqueuer / dequeuer / scheduler e-ds egress data store e-gdq discard queue stack. holds frames that need to be discarded. this is used by the hardware to discard frames when the egress ds is congested or to re-walk a frame marked for discard for a half duplex port. used by the picocode to discard frames that do not have header twins allocated. egress eds egress enqueuer / dequeuer / scheduler enet mac ethernet mac eof end-of-frame epc embedded processor complex e-pmm egress-physical mac multiplexer even parity data checking method where a parity bit is added to a data field. even parity is achieved when the number of bits (dat a + parity) that contain a ?1? is even. ewma exponentially weighted moving average exponentially weighted average see exponentially weighted moving average. exponentially weighted moving average a method of smoothing a sequence of instantaneous measurements. typically, the average a(t) at time t is combined with the measurement m(t) at time t to yield the next average value: a(t + dt) = w * m(t) + (1 - w) * a(t) here weight w is a number with 0 < w 1. if the weight is 1, then the average is just the previous value of the measurement and no smoothing occurs. else previous values of m contribute to the current value of a with more recent m values being more influential. fcb frame control block ffa flexible frame alternation fhe frame header extension fhf frame header format fm full match fpga field-programmable gate array fta first twin-buffer address gdh see general data handler . term definition ibm powernp np2g network processor preliminary glossary of term s and abbreviations page 532 of 539 np2_ds_sec15_glos.fm.01 february 12, 2003 general data handler (gdh) a type of thread used to forward frames in the epc. there are 28 gdh threads. general powerpc handler request (gph-req) a type of thread in the epc that processes frames bound to the embedded powerpc. work for this thread is usually the result of a reenqueue action to the ppc queue (it processes data frames when there are no entries to process in the ppc queue). general powerpc handler response (gph-resp) a type of thread in the epc that processes responses from the embedded powerpc. work for this thread is dispatched due to an interrupt and does not use dispatcher memory. general table handler (gth) the gth executes commands not available to a gdh or gfh thread, including hardware assist to perform tree inserts, tree deletes, tree aging, and rope management. it processes data frames when there are no tree management functions to perform. gfh see guided frame handler . gfq guided frame queue gmii gigabit media-independent interface gph-req see general powerpc handler request . gph-resp see general powerpc handler response . gpp general-purpose processor gpq powerpc queue. the queue that contains frames re-enqueued for delivery to the gph for processing. gpr general-purpose register gth see general table handler . gui graphical user interface guided frame handler (gfh) there is one gfh thread available in the epc. a guided frame can be processed only by the gfh thread, but it can be configured to enable it to process data frames like a gdh thre ad. the gfh executes guided frame- related picocode, runs device management-related picocode, and exchanges control information with a control point function or a remote network processor. when there is no such task to perform and the option is enabled, the gfh can execute frame forwarding-related picocode. gxh generalized reference to any of the defined threads of the epc halfword 2 bytes hc hardware classifier hdlc see high-level data link control . term definition ibm powernp np2g preliminary network processor np2_ds_sec15_glos.fm.01 february 12, 2003 glossary of terms and abbreviations page 533 of 539 high-level data link control (hdlc) in data communication, the use of a specified series of bits to control data links in accordance with the international standards for hdlc: iso 3309 frame structure and iso 4335 elements of procedures. i- ingress i-cdm ingress cell data mover icmp internet control message protocol i-ds ingress data store iew ingress-to-egress wrap; wraps frames from the ingress side to the egress side. ims interface manager services ingress eds ingress enqueuer / dequeuer / scheduler ingress gdq ingress general data queue ipc interprocess communication i-pmm ingress-physica l mac multiplexer ipps internet protocol version 4 protocol services ipv4 internet protocol version 4 k 2 10 , or 1024 in decimal notation kb kilobit kb kilobyte lcba leaf control block address ldp label distribution protocol leaf a control block that contains the corresponding key as a reference pattern and other user data such as target port number, qos, and so on. lh latched high (a characteristic of a regist er or a bit in a regi ster (facility)). when an operational conditio n sets the facility to a value of 1, the chan ges to the oper- ational condition do not affect the state of the facility until the facility is read. lid lookup identifier ll latched low (a characteristic of a register or a bit in a register (facility)). when an operational condition sets the facility to a value of 0, the changes to the opera- tional condition do not affect the state of the facility until th e facility is read. lls low-latency sustainable bandwidth lpm longest prefix match term definition ibm powernp np2g network processor preliminary glossary of term s and abbreviations page 534 of 539 np2_ds_sec15_glos.fm.01 february 12, 2003 lsb least significant bit lsb least significant byte lsp label-switched path lu_def look-up definition m 2 20 , or 1 048 576 in decimal notation mac medium access control management information base (mib) in osi, the conceptual repository of management information within an open system. maximum burst size (mbs) in the network processor egress scheduler, the duration a flow can exceed its guaranteed minimum bandwidth before it is constrained to its guaranteed mini- mum bandwidth. maximum transmission unit (mtu) in lans, the largest possible unit of data that can be sent on a given physical medium in a single frame. for example, the mtu for ethernet is 1500 bytes. mbs see maximum burst size. mcc multicast count mcca multicast count address mh mid handler mib see management information base. mid multicast id mm mid manager mms mid manager services mpls multiprotocol label switching mpps million packets per second msb most significant bit msb most significant byte msc message sequence charts mtu see maximum transmission unit. nbt next bit to test nfa next frame control block (fcb) address term definition ibm powernp np2g preliminary network processor np2_ds_sec15_glos.fm.01 february 12, 2003 glossary of terms and abbreviations page 535 of 539 nla next leaf address nls normal latency sustainable bandwidth np network processor npa next pcsb address pointer npasm ibm network pr ocessor assembler npdd network processor device driver npddis network processor device driver initialization services npms network processor manager services npscope ibm network processor debugger npsim ibm network pr ocessor simulator nptest ibm network processor test case generator ns nanosecond nta next twin-buffer address oqg output queue grant pap password authentication protocol pbs peak bandwidth service pc program counter pcb port control block pcs physical coding sublayer pct port configuration table phy see physical layer . may also refer to a physical layer device. physical layer in the open systems interconnection reference model, the layer that provides the mechanical, electrical, functional, and procedural means to establish, main- tain, and release physical connections over the transmission medium. (t) plb processor local bus pll phase-locked loop pma physical medium attachment pmm physical mac multiplexer polcb policing control block term definition ibm powernp np2g network processor preliminary glossary of term s and abbreviations page 536 of 539 np2_ds_sec15_glos.fm.01 february 12, 2003 pos packet over sonet (also ip over sonet) post power-on self-test postcondition an action or series of actions that the user program or the npdd must perform after the function has been called and completed. for example, when the func- tion that defines a table in the npdd has been completed, the npdd must dispatch a guided frame from the powerpc core to instruct one or more epcs to define the table. ppc powerpc ppp point-to-point protocol pprev previous dis card probability precondition a requirement that must be met before the user program calls the api function. for example, a precondition exists if the user program must call one function and allow it to be completed before a second function is called. one function that has a precondition is the function that der egisters the user program. the user program must call the register function to obtain a user_handle before calling the deregistering function. ps picosecond pscb pattern search control block ptl physical transport layer pts physical transport services qcb queue control block qos see quality of service. quadword 4 words quality of service (qos) for a network connection, a set of communication characteristics such as end- to-end delay, jitter, and packet loss ratio. r/w access type ?read/write? rbuf raw buffer rcb reassembly control block rclr read current leaf from rope red random early detection rmon remote network monitoring rope leaves in a tree linked together in a circular list term definition ibm powernp np2g preliminary network processor np2_ds_sec15_glos.fm.01 february 12, 2003 glossary of terms and abbreviations page 537 of 539 rpc remote procedure call rtp real-time transport protocol rum access type ?reset under mask? rwr access type ?read with reset? sa source address sap service access point sc self-clearing (a characteristic of a regist er or a bit in a regi ster (facility)). when written to a value of 1, will automatically reset to a value of 0 when the indicated operation completes. scb scheduler control block sci switch cell interface smii serial media-independent interface smt software-managed tree sof start-of-frame sonet synchronous optical network spm serial/parallel manager sram static random-access memory ss system services sum access type ?set under mask? tbi ten-bit interface tcp transmission control protocol tdmu target dmu thread a stream of pico code instructions that utilizes a private set of registers and shared computational resources within a dppu. in the network processor, a dppu provides both shared and private resources for four threads. two threads are bound to a single picoprocessor, allowing for concurrent execution of two threads within a dppu. the coprocessors are designed to support all four threads. in general, the computational resources (alu, hardware-assist state machines, and so on) are shared among the threads. the private resources provided by each picoprocessor or coprocessor include the register set that makes up its architecture (gprs, program counters, link stacks, datapool, and so on). term definition ibm powernp np2g network processor preliminary glossary of term s and abbreviations page 538 of 539 np2_ds_sec15_glos.fm.01 february 12, 2003 tlir tree leaf insert rope tlv type length vectors tms table management services tp target port ts transport services tsdqfl tree search dequeue free list tse tree search engine tsenqfl tree search enqueue free list tsfl_id tree search free list identifier tsr tree search result ttl time to live uc unicast udp user datagram protocol wfq weighted fair queueing word 4 bytes zbt zero bus turnaround term definition ibm powernp np2g preliminary network processor np2_ds_sec15_glos.fm.01 february 12, 2003 revision log page 539 of 539 revision log rev description of modification april 9, 2002 initial release of datashee t for ibm32np160epxcaa133 (revision 00). february 12, 2003 revision 01 of datasheet for ibm32np160epxcaa133. section 2. physical description section 3. physical mac multiplexer table 3-5. receive counter ram addresses for ingress pos mac : corrected signal name (rx_err). section 7. embedded processor complex globally corrected number of coprocessors (ten). table 7-66. counter coprocessor address map : updated ctrcontrol description. 7.4.8 counter coprocessor : clarified definition of ctrcontrol input ; changed ?blockindex? input to ?setindex.? section 14. electrical and thermal specifications table 14-19. receiver maximum input leakage dc current input specifications : updated values. section 15. glossary added ?dashboard.? |
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